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7dec62e9 PM |
1 | /* |
2 | * SH4-202 Setup | |
3 | * | |
4 | * Copyright (C) 2006 Paul Mundt | |
67d889bd | 5 | * Copyright (C) 2009 Magnus Damm |
7dec62e9 PM |
6 | * |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/serial.h> | |
96de1a8f | 14 | #include <linux/serial_sci.h> |
5f8a29ba | 15 | #include <linux/sh_timer.h> |
67d889bd | 16 | #include <linux/io.h> |
7dec62e9 PM |
17 | |
18 | static struct plat_sci_port sci_platform_data[] = { | |
19 | { | |
20 | .mapbase = 0xffe80000, | |
21 | .flags = UPF_BOOT_AUTOCONF, | |
22 | .type = PORT_SCIF, | |
23 | .irqs = { 40, 41, 43, 42 }, | |
24 | }, { | |
25 | .flags = 0, | |
26 | } | |
27 | }; | |
28 | ||
29 | static struct platform_device sci_device = { | |
30 | .name = "sh-sci", | |
31 | .id = -1, | |
32 | .dev = { | |
33 | .platform_data = sci_platform_data, | |
34 | }, | |
35 | }; | |
36 | ||
5f8a29ba MD |
37 | static struct sh_timer_config tmu0_platform_data = { |
38 | .name = "TMU0", | |
39 | .channel_offset = 0x04, | |
40 | .timer_bit = 0, | |
af777ce4 | 41 | .clk = "peripheral_clk", |
5f8a29ba MD |
42 | .clockevent_rating = 200, |
43 | }; | |
44 | ||
45 | static struct resource tmu0_resources[] = { | |
46 | [0] = { | |
47 | .name = "TMU0", | |
48 | .start = 0xffd80008, | |
49 | .end = 0xffd80013, | |
50 | .flags = IORESOURCE_MEM, | |
51 | }, | |
52 | [1] = { | |
53 | .start = 16, | |
54 | .flags = IORESOURCE_IRQ, | |
55 | }, | |
56 | }; | |
57 | ||
58 | static struct platform_device tmu0_device = { | |
59 | .name = "sh_tmu", | |
60 | .id = 0, | |
61 | .dev = { | |
62 | .platform_data = &tmu0_platform_data, | |
63 | }, | |
64 | .resource = tmu0_resources, | |
65 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
66 | }; | |
67 | ||
68 | static struct sh_timer_config tmu1_platform_data = { | |
69 | .name = "TMU1", | |
70 | .channel_offset = 0x10, | |
71 | .timer_bit = 1, | |
af777ce4 | 72 | .clk = "peripheral_clk", |
5f8a29ba MD |
73 | .clocksource_rating = 200, |
74 | }; | |
75 | ||
76 | static struct resource tmu1_resources[] = { | |
77 | [0] = { | |
78 | .name = "TMU1", | |
79 | .start = 0xffd80014, | |
80 | .end = 0xffd8001f, | |
81 | .flags = IORESOURCE_MEM, | |
82 | }, | |
83 | [1] = { | |
84 | .start = 17, | |
85 | .flags = IORESOURCE_IRQ, | |
86 | }, | |
87 | }; | |
88 | ||
89 | static struct platform_device tmu1_device = { | |
90 | .name = "sh_tmu", | |
91 | .id = 1, | |
92 | .dev = { | |
93 | .platform_data = &tmu1_platform_data, | |
94 | }, | |
95 | .resource = tmu1_resources, | |
96 | .num_resources = ARRAY_SIZE(tmu1_resources), | |
97 | }; | |
98 | ||
99 | static struct sh_timer_config tmu2_platform_data = { | |
100 | .name = "TMU2", | |
101 | .channel_offset = 0x1c, | |
102 | .timer_bit = 2, | |
af777ce4 | 103 | .clk = "peripheral_clk", |
5f8a29ba MD |
104 | }; |
105 | ||
106 | static struct resource tmu2_resources[] = { | |
107 | [0] = { | |
108 | .name = "TMU2", | |
109 | .start = 0xffd80020, | |
110 | .end = 0xffd8002f, | |
111 | .flags = IORESOURCE_MEM, | |
112 | }, | |
113 | [1] = { | |
114 | .start = 18, | |
115 | .flags = IORESOURCE_IRQ, | |
116 | }, | |
117 | }; | |
118 | ||
119 | static struct platform_device tmu2_device = { | |
120 | .name = "sh_tmu", | |
121 | .id = 2, | |
122 | .dev = { | |
123 | .platform_data = &tmu2_platform_data, | |
124 | }, | |
125 | .resource = tmu2_resources, | |
126 | .num_resources = ARRAY_SIZE(tmu2_resources), | |
127 | }; | |
128 | ||
7dec62e9 PM |
129 | static struct platform_device *sh4202_devices[] __initdata = { |
130 | &sci_device, | |
5f8a29ba MD |
131 | &tmu0_device, |
132 | &tmu1_device, | |
133 | &tmu2_device, | |
7dec62e9 PM |
134 | }; |
135 | ||
136 | static int __init sh4202_devices_setup(void) | |
137 | { | |
138 | return platform_add_devices(sh4202_devices, | |
139 | ARRAY_SIZE(sh4202_devices)); | |
140 | } | |
ba9a6337 | 141 | arch_initcall(sh4202_devices_setup); |
b58d134c | 142 | |
5f8a29ba MD |
143 | static struct platform_device *sh4202_early_devices[] __initdata = { |
144 | &tmu0_device, | |
145 | &tmu1_device, | |
146 | &tmu2_device, | |
147 | }; | |
148 | ||
149 | void __init plat_early_device_setup(void) | |
150 | { | |
151 | early_platform_add_devices(sh4202_early_devices, | |
152 | ARRAY_SIZE(sh4202_early_devices)); | |
153 | } | |
154 | ||
67d889bd MD |
155 | enum { |
156 | UNUSED = 0, | |
157 | ||
158 | /* interrupt sources */ | |
159 | IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */ | |
160 | HUDI, TMU0, TMU1, TMU2, RTC, SCIF, WDT, | |
161 | }; | |
162 | ||
163 | static struct intc_vect vectors[] __initdata = { | |
164 | INTC_VECT(HUDI, 0x600), | |
165 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | |
166 | INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2, 0x460), | |
167 | INTC_VECT(RTC, 0x480), INTC_VECT(RTC, 0x4a0), | |
168 | INTC_VECT(RTC, 0x4c0), | |
169 | INTC_VECT(SCIF, 0x700), INTC_VECT(SCIF, 0x720), | |
170 | INTC_VECT(SCIF, 0x740), INTC_VECT(SCIF, 0x760), | |
171 | INTC_VECT(WDT, 0x560), | |
172 | }; | |
173 | ||
174 | static struct intc_prio_reg prio_registers[] __initdata = { | |
175 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | |
176 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, 0, 0, 0 } }, | |
177 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { 0, 0, SCIF, HUDI } }, | |
178 | { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, | |
179 | }; | |
180 | ||
181 | static DECLARE_INTC_DESC(intc_desc, "sh4-202", vectors, NULL, | |
182 | NULL, prio_registers, NULL); | |
183 | ||
184 | static struct intc_vect vectors_irlm[] __initdata = { | |
185 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), | |
186 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), | |
187 | }; | |
188 | ||
189 | static DECLARE_INTC_DESC(intc_desc_irlm, "sh4-202_irlm", vectors_irlm, NULL, | |
190 | NULL, prio_registers, NULL); | |
191 | ||
b58d134c MD |
192 | void __init plat_irq_setup(void) |
193 | { | |
67d889bd MD |
194 | register_intc_controller(&intc_desc); |
195 | } | |
196 | ||
197 | #define INTC_ICR 0xffd00000UL | |
198 | #define INTC_ICR_IRLM (1<<7) | |
199 | ||
200 | void __init plat_irq_setup_pins(int mode) | |
201 | { | |
202 | switch (mode) { | |
203 | case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ | |
204 | ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); | |
205 | register_intc_controller(&intc_desc_irlm); | |
206 | break; | |
207 | default: | |
208 | BUG(); | |
209 | } | |
b58d134c | 210 | } |