[mirror_ubuntu-kernels.git] / arch / sh / kernel / cpu / sh4 / setup-sh7750.c

/*
 * SH7750/SH7751 Setup
 *
 *  Copyright (C) 2006  Paul Mundt
 *  Copyright (C) 2006  Jamie Lenehan
 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/io.h>
#include <linux/serial_sci.h>

static struct resource rtc_resources[] = {
	[0] = {
		.start	= 0xffc80000,
		.end	= 0xffc80000 + 0x58 - 1,
		.flags	= IORESOURCE_IO,
	},
	[1] = {
		/* Period IRQ */
		.start	= 21,
		.flags	= IORESOURCE_IRQ,
	},
	[2] = {
		/* Carry IRQ */
		.start	= 22,
		.flags	= IORESOURCE_IRQ,
	},
	[3] = {
		/* Alarm IRQ */
		.start	= 20,
		.flags	= IORESOURCE_IRQ,
	},
};

static struct platform_device rtc_device = {
	.name		= "sh-rtc",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(rtc_resources),
	.resource	= rtc_resources,
};

static struct plat_sci_port sci_platform_data[] = {
	{
#ifndef CONFIG_SH_RTS7751R2D
		.mapbase	= 0xffe00000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCI,
		.irqs		= { 23, 24, 25, 0 },
	}, {
#endif
		.mapbase	= 0xffe80000,
		.flags		= UPF_BOOT_AUTOCONF,
		.type		= PORT_SCIF,
		.irqs		= { 40, 41, 43, 42 },
	}, {
		.flags = 0,
	}
};

static struct platform_device sci_device = {
	.name		= "sh-sci",
	.id		= -1,
	.dev		= {
		.platform_data	= sci_platform_data,
	},
};

static struct platform_device *sh7750_devices[] __initdata = {
	&rtc_device,
	&sci_device,
};

static int __init sh7750_devices_setup(void)
{
	return platform_add_devices(sh7750_devices,
				    ARRAY_SIZE(sh7750_devices));
}
__initcall(sh7750_devices_setup);

enum {
	UNUSED = 0,

	/* interrupt sources */
	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
	HUDI, GPIOI,
	DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
	DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
	DMAC_DMAE,
	PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
	TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
	RTC_ATI, RTC_PRI, RTC_CUI,
	SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
	SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
	WDT,
	REF_RCMI, REF_ROVI,

	/* interrupt groups */
	DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
	INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
	INTC_VECT(RTC_CUI, 0x4c0),
	INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
	INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
	INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
	INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
	INTC_VECT(WDT, 0x560),
	INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
	INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
	INTC_GROUP(REF, REF_RCMI, REF_ROVI),
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
						 TMU4, TMU3,
						 PCIC1, PCIC0_PCISERR } },
};

static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
			 NULL, prio_registers, NULL);

/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
	defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
	defined(CONFIG_CPU_SUBTYPE_SH7091)
static struct intc_vect vectors_dma4[] __initdata = {
	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
	INTC_VECT(DMAC_DMAE, 0x6c0),
};

static struct intc_group groups_dma4[] __initdata = {
	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
		   DMAC_DMTE3, DMAC_DMAE),
};

static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
			 vectors_dma4, groups_dma4,
			 NULL, prio_registers, NULL);
#endif

/* SH7750R and SH7751R both have 8-channel DMA controllers */
#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
static struct intc_vect vectors_dma8[] __initdata = {
	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
	INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
	INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
	INTC_VECT(DMAC_DMAE, 0x6c0),
};

static struct intc_group groups_dma8[] __initdata = {
	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
		   DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
		   DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
};

static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
			 vectors_dma8, groups_dma8,
			 NULL, prio_registers, NULL);
#endif

/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
#if defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
	defined(CONFIG_CPU_SUBTYPE_SH7751) || \
	defined(CONFIG_CPU_SUBTYPE_SH7751R)
static struct intc_vect vectors_tmu34[] __initdata = {
	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	    0, 0, 0, 0, 0, 0, TMU4, TMU3,
	    PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	    PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
	    PCIC1_PCIDMA3, PCIC0_PCISERR } },
};

static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
			 vectors_tmu34, NULL,
			 mask_registers, prio_registers, NULL);
#endif

/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
static struct intc_vect vectors_irlm[] __initdata = {
	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
};

static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
			 NULL, prio_registers, NULL);

/* SH7751 and SH7751R both have PCI */
#if defined(CONFIG_CPU_SUBTYPE_SH7751) || defined(CONFIG_CPU_SUBTYPE_SH7751R)
static struct intc_vect vectors_pci[] __initdata = {
	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
};

static struct intc_group groups_pci[] __initdata = {
	INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
		   PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
};

static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
			 mask_registers, prio_registers, NULL);
#endif

#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
	defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
	defined(CONFIG_CPU_SUBTYPE_SH7091)
void __init plat_irq_setup(void)
{
	/*
	 * same vectors for SH7750, SH7750S and SH7091 except for IRLM,
	 * see below..
	 */
	register_intc_controller(&intc_desc);
	register_intc_controller(&intc_desc_dma4);
}
#endif

#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
	register_intc_controller(&intc_desc_dma8);
	register_intc_controller(&intc_desc_tmu34);
}
#endif

#if defined(CONFIG_CPU_SUBTYPE_SH7751)
void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
	register_intc_controller(&intc_desc_dma4);
	register_intc_controller(&intc_desc_tmu34);
	register_intc_controller(&intc_desc_pci);
}
#endif

#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
	register_intc_controller(&intc_desc_dma8);
	register_intc_controller(&intc_desc_tmu34);
	register_intc_controller(&intc_desc_pci);
}
#endif

#define INTC_ICR	0xffd00000UL
#define INTC_ICR_IRLM   (1<<7)

void __init plat_irq_setup_pins(int mode)
{
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7091)
	BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
	return;
#endif

	switch (mode) {
	case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
		ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
		register_intc_controller(&intc_desc_irlm);
		break;
	default:
		BUG();
	}
}
Commit	Line	Data
7dec62e9 PM	1	/*
	2	* SH7750/SH7751 Setup
	3	*
	4	* Copyright (C) 2006 Paul Mundt
ea0f8fea	5	* Copyright (C) 2006 Jamie Lenehan
7dec62e9 PM	6	*
	7	* This file is subject to the terms and conditions of the GNU General Public
	8	* License. See the file "COPYING" in the main directory of this archive
	9	* for more details.
	10	*/
	11	#include <linux/platform_device.h>
	12	#include <linux/init.h>
	13	#include <linux/serial.h>
ea0f8fea	14	#include <linux/io.h>
96de1a8f	15	#include <linux/serial_sci.h>
7dec62e9	16
417d6b9e JL	17	static struct resource rtc_resources[] = {
	18	[0] = {
	19	.start = 0xffc80000,
	20	.end = 0xffc80000 + 0x58 - 1,
	21	.flags = IORESOURCE_IO,
	22	},
	23	[1] = {
	24	/* Period IRQ */
	25	.start = 21,
	26	.flags = IORESOURCE_IRQ,
	27	},
	28	[2] = {
	29	/* Carry IRQ */
	30	.start = 22,
	31	.flags = IORESOURCE_IRQ,
	32	},
	33	[3] = {
	34	/* Alarm IRQ */
	35	.start = 20,
	36	.flags = IORESOURCE_IRQ,
	37	},
	38	};
	39
	40	static struct platform_device rtc_device = {
	41	.name = "sh-rtc",
	42	.id = -1,
	43	.num_resources = ARRAY_SIZE(rtc_resources),
	44	.resource = rtc_resources,
	45	};
	46
7dec62e9 PM	47	static struct plat_sci_port sci_platform_data[] = {
7dec62e9 PM	48	{
9c57548f	49	#ifndef CONFIG_SH_RTS7751R2D
7dec62e9 PM	50	.mapbase = 0xffe00000,
	51	.flags = UPF_BOOT_AUTOCONF,
	52	.type = PORT_SCI,
	53	.irqs = { 23, 24, 25, 0 },
	54	}, {
9c57548f	55	#endif
7dec62e9 PM	56	.mapbase = 0xffe80000,
	57	.flags = UPF_BOOT_AUTOCONF,
	58	.type = PORT_SCIF,
	59	.irqs = { 40, 41, 43, 42 },
	60	}, {
	61	.flags = 0,
	62	}
	63	};
	64
	65	static struct platform_device sci_device = {
	66	.name = "sh-sci",
	67	.id = -1,
	68	.dev = {
	69	.platform_data = sci_platform_data,
	70	},
	71	};
	72
	73	static struct platform_device *sh7750_devices[] __initdata = {
417d6b9e	74	&rtc_device,
7dec62e9 PM	75	&sci_device,
	76	};
	77
	78	static int __init sh7750_devices_setup(void)
	79	{
	80	return platform_add_devices(sh7750_devices,
	81	ARRAY_SIZE(sh7750_devices));
	82	}
	83	__initcall(sh7750_devices_setup);
ea0f8fea	84
56386f64 MD	85	enum {
	86	UNUSED = 0,
	87
	88	/* interrupt sources */
	89	IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
	90	HUDI, GPIOI,
	91	DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
	92	DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
	93	DMAC_DMAE,
	94	PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	95	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
	96	TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
	97	RTC_ATI, RTC_PRI, RTC_CUI,
	98	SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
	99	SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
	100	WDT,
	101	REF_RCMI, REF_ROVI,
	102
	103	/* interrupt groups */
	104	DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
68abdbbb MD	105	};
68abdbbb MD	106
5c37e025	107	static struct intc_vect vectors[] __initdata = {
56386f64 MD	108	INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
	109	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	110	INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
	111	INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
	112	INTC_VECT(RTC_CUI, 0x4c0),
	113	INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
	114	INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
	115	INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
	116	INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
	117	INTC_VECT(WDT, 0x560),
	118	INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
ea0f8fea JL	119	};
ea0f8fea JL	120
5c37e025	121	static struct intc_group groups[] __initdata = {
56386f64 MD	122	INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
	123	INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
	124	INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
	125	INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
	126	INTC_GROUP(REF, REF_RCMI, REF_ROVI),
	127	};
68abdbbb	128
5c37e025	129	static struct intc_prio_reg prio_registers[] __initdata = {
6ef5fb2c MD	130	{ 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
	131	{ 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } },
	132	{ 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } },
	133	{ 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } },
	134	{ 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0,
	135	TMU4, TMU3,
	136	PCIC1, PCIC0_PCISERR } },
56386f64 MD	137	};
	138
	139	static DECLARE_INTC_DESC(intc_desc, "sh7750", vectors, groups,
7f3edee8	140	NULL, prio_registers, NULL);
56386f64 MD	141
	142	/* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */
	143	#if defined(CONFIG_CPU_SUBTYPE_SH7750) \|\| \
	144	defined(CONFIG_CPU_SUBTYPE_SH7750S) \|\| \
	145	defined(CONFIG_CPU_SUBTYPE_SH7751) \|\| \
	146	defined(CONFIG_CPU_SUBTYPE_SH7091)
5c37e025	147	static struct intc_vect vectors_dma4[] __initdata = {
56386f64 MD	148	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
	149	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
	150	INTC_VECT(DMAC_DMAE, 0x6c0),
	151	};
	152
5c37e025	153	static struct intc_group groups_dma4[] __initdata = {
56386f64 MD	154	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
	155	DMAC_DMTE3, DMAC_DMAE),
	156	};
	157
	158	static DECLARE_INTC_DESC(intc_desc_dma4, "sh7750_dma4",
	159	vectors_dma4, groups_dma4,
7f3edee8	160	NULL, prio_registers, NULL);
56386f64 MD	161	#endif
	162
	163	/* SH7750R and SH7751R both have 8-channel DMA controllers */
	164	#if defined(CONFIG_CPU_SUBTYPE_SH7750R) \|\| defined(CONFIG_CPU_SUBTYPE_SH7751R)
5c37e025	165	static struct intc_vect vectors_dma8[] __initdata = {
56386f64 MD	166	INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
	167	INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
	168	INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
	169	INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
	170	INTC_VECT(DMAC_DMAE, 0x6c0),
	171	};
	172
5c37e025	173	static struct intc_group groups_dma8[] __initdata = {
56386f64 MD	174	INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
	175	DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
	176	DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
	177	};
	178
	179	static DECLARE_INTC_DESC(intc_desc_dma8, "sh7750_dma8",
	180	vectors_dma8, groups_dma8,
7f3edee8	181	NULL, prio_registers, NULL);
56386f64 MD	182	#endif
	183
	184	/* SH7750R, SH7751 and SH7751R all have two extra timer channels */
	185	#if defined(CONFIG_CPU_SUBTYPE_SH7750R) \|\| \
	186	defined(CONFIG_CPU_SUBTYPE_SH7751) \|\| \
	187	defined(CONFIG_CPU_SUBTYPE_SH7751R)
5c37e025	188	static struct intc_vect vectors_tmu34[] __initdata = {
56386f64 MD	189	INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
	190	};
	191
5c37e025	192	static struct intc_mask_reg mask_registers[] __initdata = {
56386f64 MD	193	{ 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */
	194	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
	195	0, 0, 0, 0, 0, 0, TMU4, TMU3,
	196	PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
	197	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
	198	PCIC1_PCIDMA3, PCIC0_PCISERR } },
	199	};
	200
	201	static DECLARE_INTC_DESC(intc_desc_tmu34, "sh7750_tmu34",
7f3edee8	202	vectors_tmu34, NULL,
56386f64 MD	203	mask_registers, prio_registers, NULL);
	204	#endif
	205
	206	/* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */
5c37e025	207	static struct intc_vect vectors_irlm[] __initdata = {
56386f64 MD	208	INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
	209	INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
	210	};
	211
	212	static DECLARE_INTC_DESC(intc_desc_irlm, "sh7750_irlm", vectors_irlm, NULL,
7f3edee8	213	NULL, prio_registers, NULL);
56386f64 MD	214
	215	/* SH7751 and SH7751R both have PCI */
	216	#if defined(CONFIG_CPU_SUBTYPE_SH7751) \|\| defined(CONFIG_CPU_SUBTYPE_SH7751R)
5c37e025	217	static struct intc_vect vectors_pci[] __initdata = {
56386f64 MD	218	INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
	219	INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
	220	INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
	221	INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
	222	};
	223
5c37e025	224	static struct intc_group groups_pci[] __initdata = {
56386f64 MD	225	INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
56386f64 MD	226	PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
ea0f8fea	227	};
56386f64 MD	228
56386f64 MD	229	static DECLARE_INTC_DESC(intc_desc_pci, "sh7750_pci", vectors_pci, groups_pci,
7f3edee8	230	mask_registers, prio_registers, NULL);
68abdbbb	231	#endif
ea0f8fea	232
56386f64 MD	233	#if defined(CONFIG_CPU_SUBTYPE_SH7750) \|\| \
	234	defined(CONFIG_CPU_SUBTYPE_SH7750S) \|\| \
	235	defined(CONFIG_CPU_SUBTYPE_SH7091)
90015c89	236	void __init plat_irq_setup(void)
ea0f8fea	237	{
56386f64 MD	238	/*
	239	* same vectors for SH7750, SH7750S and SH7091 except for IRLM,
	240	* see below..
	241	*/
	242	register_intc_controller(&intc_desc);
	243	register_intc_controller(&intc_desc_dma4);
	244	}
68abdbbb	245	#endif
56386f64 MD	246
	247	#if defined(CONFIG_CPU_SUBTYPE_SH7750R)
	248	void __init plat_irq_setup(void)
	249	{
	250	register_intc_controller(&intc_desc);
	251	register_intc_controller(&intc_desc_dma8);
	252	register_intc_controller(&intc_desc_tmu34);
ea0f8fea	253	}
56386f64 MD	254	#endif
	255
	256	#if defined(CONFIG_CPU_SUBTYPE_SH7751)
	257	void __init plat_irq_setup(void)
	258	{
	259	register_intc_controller(&intc_desc);
	260	register_intc_controller(&intc_desc_dma4);
	261	register_intc_controller(&intc_desc_tmu34);
	262	register_intc_controller(&intc_desc_pci);
	263	}
	264	#endif
	265
	266	#if defined(CONFIG_CPU_SUBTYPE_SH7751R)
	267	void __init plat_irq_setup(void)
	268	{
	269	register_intc_controller(&intc_desc);
	270	register_intc_controller(&intc_desc_dma8);
	271	register_intc_controller(&intc_desc_tmu34);
	272	register_intc_controller(&intc_desc_pci);
	273	}
	274	#endif
ea0f8fea JL	275
	276	#define INTC_ICR 0xffd00000UL
	277	#define INTC_ICR_IRLM (1<<7)
	278
d59645d6	279	void __init plat_irq_setup_pins(int mode)
ea0f8fea	280	{
56386f64 MD	281	#if defined(CONFIG_CPU_SUBTYPE_SH7750) \|\| defined(CONFIG_CPU_SUBTYPE_SH7091)
56386f64 MD	282	BUG(); /* impossible to mask interrupts on SH7750 and SH7091 */
d59645d6	283	return;
56386f64	284	#endif
56386f64	285
d59645d6 MD	286	switch (mode) {
	287	case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
	288	ctrl_outw(ctrl_inw(INTC_ICR) \| INTC_ICR_IRLM, INTC_ICR);
	289	register_intc_controller(&intc_desc_irlm);
	290	break;
	291	default:
	292	BUG();
	293	}
ea0f8fea	294	}