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b621370a MD |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7724.c | |
3 | * | |
4 | * SH7724 clock framework support | |
5 | * | |
6 | * Copyright (C) 2009 Magnus Damm | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
20 | */ | |
21 | #include <linux/init.h> | |
22 | #include <linux/kernel.h> | |
23 | #include <linux/io.h> | |
f4cff0d0 | 24 | #include <linux/clk.h> |
6d803ba7 | 25 | #include <linux/clkdev.h> |
8cc88a55 | 26 | #include <linux/sh_clk.h> |
b621370a | 27 | #include <asm/clock.h> |
6ba4a8f0 | 28 | #include <cpu/sh7724.h> |
b621370a MD |
29 | |
30 | /* SH7724 registers */ | |
31 | #define FRQCRA 0xa4150000 | |
32 | #define FRQCRB 0xa4150004 | |
33 | #define VCLKCR 0xa4150048 | |
34 | #define FCLKACR 0xa4150008 | |
35 | #define FCLKBCR 0xa415000c | |
36 | #define IRDACLKCR 0xa4150018 | |
37 | #define PLLCR 0xa4150024 | |
8cc88a55 GL |
38 | #define MSTPCR0 0xa4150030 |
39 | #define MSTPCR1 0xa4150034 | |
40 | #define MSTPCR2 0xa4150038 | |
b621370a MD |
41 | #define SPUCLKCR 0xa415003c |
42 | #define FLLFRQ 0xa4150050 | |
43 | #define LSTATS 0xa4150060 | |
44 | ||
45 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | |
46 | static struct clk r_clk = { | |
b621370a MD |
47 | .rate = 32768, |
48 | }; | |
49 | ||
50 | /* | |
51 | * Default rate for the root input clock, reset this with clk_set_rate() | |
52 | * from the platform code. | |
53 | */ | |
d0013c9e | 54 | static struct clk extal_clk = { |
b621370a MD |
55 | .rate = 33333333, |
56 | }; | |
57 | ||
58 | /* The fll multiplies the 32khz r_clk, may be used instead of extal */ | |
59 | static unsigned long fll_recalc(struct clk *clk) | |
60 | { | |
61 | unsigned long mult = 0; | |
62 | unsigned long div = 1; | |
63 | ||
64 | if (__raw_readl(PLLCR) & 0x1000) | |
65 | mult = __raw_readl(FLLFRQ) & 0x3ff; | |
66 | ||
67 | if (__raw_readl(FLLFRQ) & 0x4000) | |
68 | div = 2; | |
69 | ||
70 | return (clk->parent->rate * mult) / div; | |
71 | } | |
72 | ||
73 | static struct clk_ops fll_clk_ops = { | |
74 | .recalc = fll_recalc, | |
75 | }; | |
76 | ||
77 | static struct clk fll_clk = { | |
b621370a MD |
78 | .ops = &fll_clk_ops, |
79 | .parent = &r_clk, | |
80 | .flags = CLK_ENABLE_ON_INIT, | |
81 | }; | |
82 | ||
83 | static unsigned long pll_recalc(struct clk *clk) | |
84 | { | |
85 | unsigned long mult = 1; | |
86 | ||
87 | if (__raw_readl(PLLCR) & 0x4000) | |
88 | mult = (((__raw_readl(FRQCRA) >> 24) & 0x3f) + 1) * 2; | |
89 | ||
90 | return clk->parent->rate * mult; | |
91 | } | |
92 | ||
93 | static struct clk_ops pll_clk_ops = { | |
94 | .recalc = pll_recalc, | |
95 | }; | |
96 | ||
97 | static struct clk pll_clk = { | |
b621370a MD |
98 | .ops = &pll_clk_ops, |
99 | .flags = CLK_ENABLE_ON_INIT, | |
100 | }; | |
101 | ||
102 | /* A fixed divide-by-3 block use by the div6 clocks */ | |
103 | static unsigned long div3_recalc(struct clk *clk) | |
104 | { | |
105 | return clk->parent->rate / 3; | |
106 | } | |
107 | ||
108 | static struct clk_ops div3_clk_ops = { | |
109 | .recalc = div3_recalc, | |
110 | }; | |
111 | ||
112 | static struct clk div3_clk = { | |
b621370a MD |
113 | .ops = &div3_clk_ops, |
114 | .parent = &pll_clk, | |
115 | }; | |
116 | ||
171f1bc7 | 117 | /* External input clock (pin name: FSIMCKA/FSIMCKB/DV_CLKI ) */ |
4bd5d259 KM |
118 | struct clk sh7724_fsimcka_clk = { |
119 | }; | |
120 | ||
121 | struct clk sh7724_fsimckb_clk = { | |
122 | }; | |
123 | ||
171f1bc7 KM |
124 | struct clk sh7724_dv_clki = { |
125 | }; | |
126 | ||
d0013c9e | 127 | static struct clk *main_clks[] = { |
b621370a MD |
128 | &r_clk, |
129 | &extal_clk, | |
130 | &fll_clk, | |
131 | &pll_clk, | |
132 | &div3_clk, | |
4bd5d259 KM |
133 | &sh7724_fsimcka_clk, |
134 | &sh7724_fsimckb_clk, | |
171f1bc7 | 135 | &sh7724_dv_clki, |
b621370a MD |
136 | }; |
137 | ||
7be85c6e MD |
138 | static void div4_kick(struct clk *clk) |
139 | { | |
140 | unsigned long value; | |
141 | ||
142 | /* set KICK bit in FRQCRA to update hardware setting */ | |
143 | value = __raw_readl(FRQCRA); | |
144 | value |= (1 << 31); | |
145 | __raw_writel(value, FRQCRA); | |
146 | } | |
147 | ||
b2ea8b42 | 148 | static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 0, 24, 32, 36, 48, 0, 72 }; |
b621370a | 149 | |
0a5f337e | 150 | static struct clk_div_mult_table div4_div_mult_table = { |
b621370a MD |
151 | .divisors = divisors, |
152 | .nr_divisors = ARRAY_SIZE(divisors), | |
153 | }; | |
154 | ||
0a5f337e MD |
155 | static struct clk_div4_table div4_table = { |
156 | .div_mult_table = &div4_div_mult_table, | |
7be85c6e | 157 | .kick = div4_kick, |
0a5f337e MD |
158 | }; |
159 | ||
b621370a MD |
160 | enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_P, DIV4_M1, DIV4_NR }; |
161 | ||
914ebf0b MD |
162 | #define DIV4(_reg, _bit, _mask, _flags) \ |
163 | SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags) | |
b621370a MD |
164 | |
165 | struct clk div4_clks[DIV4_NR] = { | |
914ebf0b MD |
166 | [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT), |
167 | [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT), | |
168 | [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT), | |
169 | [DIV4_P] = DIV4(FRQCRA, 0, 0x2f7c, 0), | |
170 | [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT), | |
b621370a MD |
171 | }; |
172 | ||
171f1bc7 | 173 | enum { DIV6_V, DIV6_I, DIV6_S, DIV6_FA, DIV6_FB, DIV6_NR }; |
098ec49b | 174 | |
171f1bc7 KM |
175 | /* Indices are important - they are the actual src selecting values */ |
176 | static struct clk *common_parent[] = { | |
177 | [0] = &div3_clk, | |
178 | [1] = NULL, | |
b621370a MD |
179 | }; |
180 | ||
171f1bc7 KM |
181 | static struct clk *vclkcr_parent[8] = { |
182 | [0] = &div3_clk, | |
183 | [2] = &sh7724_dv_clki, | |
184 | [4] = &extal_clk, | |
185 | }; | |
4bd5d259 | 186 | |
4bd5d259 KM |
187 | static struct clk *fclkacr_parent[] = { |
188 | [0] = &div3_clk, | |
189 | [1] = NULL, | |
190 | [2] = &sh7724_fsimcka_clk, | |
191 | [3] = NULL, | |
192 | }; | |
193 | ||
194 | static struct clk *fclkbcr_parent[] = { | |
195 | [0] = &div3_clk, | |
196 | [1] = NULL, | |
197 | [2] = &sh7724_fsimckb_clk, | |
198 | [3] = NULL, | |
199 | }; | |
200 | ||
171f1bc7 KM |
201 | static struct clk div6_clks[DIV6_NR] = { |
202 | [DIV6_V] = SH_CLK_DIV6_EXT(VCLKCR, 0, | |
203 | vclkcr_parent, ARRAY_SIZE(vclkcr_parent), 12, 3), | |
204 | [DIV6_I] = SH_CLK_DIV6_EXT(IRDACLKCR, 0, | |
205 | common_parent, ARRAY_SIZE(common_parent), 6, 1), | |
206 | [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT, | |
207 | common_parent, ARRAY_SIZE(common_parent), 6, 1), | |
56242a1f | 208 | [DIV6_FA] = SH_CLK_DIV6_EXT(FCLKACR, 0, |
4bd5d259 | 209 | fclkacr_parent, ARRAY_SIZE(fclkacr_parent), 6, 2), |
56242a1f | 210 | [DIV6_FB] = SH_CLK_DIV6_EXT(FCLKBCR, 0, |
4bd5d259 KM |
211 | fclkbcr_parent, ARRAY_SIZE(fclkbcr_parent), 6, 2), |
212 | }; | |
213 | ||
f3d51e13 | 214 | static struct clk mstp_clks[HWBLK_NR] = { |
8cc88a55 GL |
215 | [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT), |
216 | [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT), | |
217 | [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT), | |
218 | [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT), | |
219 | [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT), | |
220 | [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT), | |
221 | [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT), | |
222 | [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT), | |
223 | [HWBLK_DMAC0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 21, 0), | |
224 | [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT), | |
225 | [HWBLK_HUDI] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 19, 0), | |
226 | [HWBLK_UBC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 17, 0), | |
227 | [HWBLK_TMU0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0), | |
228 | [HWBLK_CMT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 14, 0), | |
229 | [HWBLK_RWDT] = SH_CLK_MSTP32(&r_clk, MSTPCR0, 13, 0), | |
230 | [HWBLK_DMAC1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 12, 0), | |
231 | [HWBLK_TMU1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0), | |
232 | [HWBLK_SCIF0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0), | |
233 | [HWBLK_SCIF1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0), | |
234 | [HWBLK_SCIF2] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 7, 0), | |
235 | [HWBLK_SCIF3] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 6, 0), | |
236 | [HWBLK_SCIF4] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 5, 0), | |
237 | [HWBLK_SCIF5] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 4, 0), | |
238 | [HWBLK_MSIOF0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 2, 0), | |
239 | [HWBLK_MSIOF1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 1, 0), | |
240 | ||
241 | [HWBLK_KEYSC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 12, 0), | |
242 | [HWBLK_RTC] = SH_CLK_MSTP32(&r_clk, MSTPCR1, 11, 0), | |
243 | [HWBLK_IIC0] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 9, 0), | |
244 | [HWBLK_IIC1] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 8, 0), | |
245 | ||
246 | [HWBLK_MMC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 29, 0), | |
247 | [HWBLK_ETHER] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 28, 0), | |
248 | [HWBLK_ATAPI] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 26, 0), | |
249 | [HWBLK_TPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 25, 0), | |
250 | [HWBLK_IRDA] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR2, 24, 0), | |
251 | [HWBLK_TSIF] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 22, 0), | |
252 | [HWBLK_USB1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, 0), | |
253 | [HWBLK_USB0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 20, 0), | |
254 | [HWBLK_2DG] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 19, 0), | |
255 | [HWBLK_SDHI0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 18, 0), | |
256 | [HWBLK_SDHI1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 17, 0), | |
257 | [HWBLK_VEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 15, 0), | |
258 | [HWBLK_CEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 13, 0), | |
259 | [HWBLK_BEU1] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 12, 0), | |
260 | [HWBLK_2DDMAC] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR2, 10, 0), | |
261 | [HWBLK_SPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 9, 0), | |
262 | [HWBLK_JPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 6, 0), | |
263 | [HWBLK_VOU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 5, 0), | |
264 | [HWBLK_BEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 4, 0), | |
265 | [HWBLK_CEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 3, 0), | |
266 | [HWBLK_VEU0] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 2, 0), | |
267 | [HWBLK_VPU] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 1, 0), | |
268 | [HWBLK_LCDC] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 0, 0), | |
b621370a MD |
269 | }; |
270 | ||
f4cff0d0 | 271 | static struct clk_lookup lookups[] = { |
b3f9f630 MD |
272 | /* main clocks */ |
273 | CLKDEV_CON_ID("rclk", &r_clk), | |
274 | CLKDEV_CON_ID("extal", &extal_clk), | |
275 | CLKDEV_CON_ID("fll_clk", &fll_clk), | |
276 | CLKDEV_CON_ID("pll_clk", &pll_clk), | |
277 | CLKDEV_CON_ID("div3_clk", &div3_clk), | |
278 | ||
1c4cde2e MD |
279 | /* DIV4 clocks */ |
280 | CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]), | |
281 | CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]), | |
282 | CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]), | |
283 | CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]), | |
284 | CLKDEV_CON_ID("vpu_clk", &div4_clks[DIV4_M1]), | |
285 | ||
098ec49b MD |
286 | /* DIV6 clocks */ |
287 | CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]), | |
171f1bc7 KM |
288 | CLKDEV_CON_ID("fsia_clk", &div6_clks[DIV6_FA]), |
289 | CLKDEV_CON_ID("fsib_clk", &div6_clks[DIV6_FB]), | |
098ec49b MD |
290 | CLKDEV_CON_ID("irda_clk", &div6_clks[DIV6_I]), |
291 | CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_S]), | |
292 | ||
fd30401b MD |
293 | /* MSTP clocks */ |
294 | CLKDEV_CON_ID("tlb0", &mstp_clks[HWBLK_TLB]), | |
295 | CLKDEV_CON_ID("ic0", &mstp_clks[HWBLK_IC]), | |
296 | CLKDEV_CON_ID("oc0", &mstp_clks[HWBLK_OC]), | |
297 | CLKDEV_CON_ID("rs0", &mstp_clks[HWBLK_RSMEM]), | |
298 | CLKDEV_CON_ID("ilmem0", &mstp_clks[HWBLK_ILMEM]), | |
299 | CLKDEV_CON_ID("l2c0", &mstp_clks[HWBLK_L2C]), | |
300 | CLKDEV_CON_ID("fpu0", &mstp_clks[HWBLK_FPU]), | |
301 | CLKDEV_CON_ID("intc0", &mstp_clks[HWBLK_INTC]), | |
8cc88a55 | 302 | CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[HWBLK_DMAC0]), |
fd30401b MD |
303 | CLKDEV_CON_ID("sh0", &mstp_clks[HWBLK_SHYWAY]), |
304 | CLKDEV_CON_ID("hudi0", &mstp_clks[HWBLK_HUDI]), | |
305 | CLKDEV_CON_ID("ubc0", &mstp_clks[HWBLK_UBC]), | |
23bcc04d KM |
306 | |
307 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.0", &mstp_clks[HWBLK_TMU0]), | |
308 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.1", &mstp_clks[HWBLK_TMU0]), | |
309 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.2", &mstp_clks[HWBLK_TMU0]), | |
310 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.3", &mstp_clks[HWBLK_TMU1]), | |
311 | ||
fd30401b | 312 | CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]), |
8cc88a55 GL |
313 | CLKDEV_DEV_ID("sh-wdt.0", &mstp_clks[HWBLK_RWDT]), |
314 | CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[HWBLK_DMAC1]), | |
23bcc04d KM |
315 | |
316 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.4", &mstp_clks[HWBLK_TMU1]), | |
317 | CLKDEV_ICK_ID("tmu_fck", "sh_tmu.5", &mstp_clks[HWBLK_TMU1]), | |
8cc88a55 GL |
318 | CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[HWBLK_SCIF0]), |
319 | CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[HWBLK_SCIF1]), | |
320 | CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[HWBLK_SCIF2]), | |
321 | CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[HWBLK_SCIF3]), | |
322 | CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[HWBLK_SCIF4]), | |
323 | CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[HWBLK_SCIF5]), | |
324 | ||
325 | CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[HWBLK_MSIOF0]), | |
326 | CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[HWBLK_MSIOF1]), | |
327 | CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[HWBLK_KEYSC]), | |
fd30401b | 328 | CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]), |
1ec353a0 KM |
329 | CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[HWBLK_IIC0]), |
330 | CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[HWBLK_IIC1]), | |
8cc88a55 GL |
331 | CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[HWBLK_MMC]), |
332 | CLKDEV_DEV_ID("sh-eth.0", &mstp_clks[HWBLK_ETHER]), | |
fd30401b MD |
333 | CLKDEV_CON_ID("atapi0", &mstp_clks[HWBLK_ATAPI]), |
334 | CLKDEV_CON_ID("tpu0", &mstp_clks[HWBLK_TPU]), | |
335 | CLKDEV_CON_ID("irda0", &mstp_clks[HWBLK_IRDA]), | |
336 | CLKDEV_CON_ID("tsif0", &mstp_clks[HWBLK_TSIF]), | |
337 | CLKDEV_CON_ID("usb1", &mstp_clks[HWBLK_USB1]), | |
338 | CLKDEV_CON_ID("usb0", &mstp_clks[HWBLK_USB0]), | |
339 | CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]), | |
8cc88a55 GL |
340 | CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[HWBLK_SDHI0]), |
341 | CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[HWBLK_SDHI1]), | |
fd30401b | 342 | CLKDEV_CON_ID("veu1", &mstp_clks[HWBLK_VEU1]), |
8cc88a55 | 343 | CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[HWBLK_CEU1]), |
fd30401b MD |
344 | CLKDEV_CON_ID("beu1", &mstp_clks[HWBLK_BEU1]), |
345 | CLKDEV_CON_ID("2ddmac0", &mstp_clks[HWBLK_2DDMAC]), | |
833218f1 | 346 | CLKDEV_DEV_ID("sh_fsi.0", &mstp_clks[HWBLK_SPU]), |
fd30401b | 347 | CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]), |
8cc88a55 | 348 | CLKDEV_DEV_ID("sh-vou.0", &mstp_clks[HWBLK_VOU]), |
fd30401b | 349 | CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU0]), |
8cc88a55 | 350 | CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[HWBLK_CEU0]), |
fd30401b MD |
351 | CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU0]), |
352 | CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]), | |
8cc88a55 | 353 | CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[HWBLK_LCDC]), |
f4cff0d0 PM |
354 | }; |
355 | ||
b621370a MD |
356 | int __init arch_clk_init(void) |
357 | { | |
358 | int k, ret = 0; | |
359 | ||
360 | /* autodetect extal or fll configuration */ | |
361 | if (__raw_readl(PLLCR) & 0x1000) | |
362 | pll_clk.parent = &fll_clk; | |
363 | else | |
364 | pll_clk.parent = &extal_clk; | |
365 | ||
366 | for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++) | |
367 | ret = clk_register(main_clks[k]); | |
368 | ||
f4cff0d0 PM |
369 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
370 | ||
b621370a MD |
371 | if (!ret) |
372 | ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table); | |
373 | ||
374 | if (!ret) | |
171f1bc7 | 375 | ret = sh_clk_div6_reparent_register(div6_clks, DIV6_NR); |
4bd5d259 | 376 | |
b621370a | 377 | if (!ret) |
8cc88a55 | 378 | ret = sh_clk_mstp32_register(mstp_clks, HWBLK_NR); |
b621370a MD |
379 | |
380 | return ret; | |
381 | } |