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Commit | Line | Data |
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7d740a06 YS |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7763.c | |
3 | * | |
4 | * SH7763 support for the clock framework | |
5 | * | |
6 | * Copyright (C) 2005 Paul Mundt | |
7 | * Copyright (C) 2007 Yoshihiro Shimoda | |
8 | * | |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/kernel.h> | |
d6a94217 | 15 | #include <linux/io.h> |
6d803ba7 | 16 | #include <linux/clkdev.h> |
7d740a06 YS |
17 | #include <asm/clock.h> |
18 | #include <asm/freq.h> | |
19 | #include <asm/io.h> | |
20 | ||
21 | static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; | |
22 | static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; | |
7d740a06 YS |
23 | static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 }; |
24 | ||
25 | static void master_clk_init(struct clk *clk) | |
26 | { | |
9d56dd3b | 27 | clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; |
7d740a06 YS |
28 | } |
29 | ||
30 | static struct clk_ops sh7763_master_clk_ops = { | |
31 | .init = master_clk_init, | |
32 | }; | |
33 | ||
b68d8201 | 34 | static unsigned long module_clk_recalc(struct clk *clk) |
7d740a06 | 35 | { |
9d56dd3b | 36 | int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); |
b68d8201 | 37 | return clk->parent->rate / p0fc_divisors[idx]; |
7d740a06 YS |
38 | } |
39 | ||
40 | static struct clk_ops sh7763_module_clk_ops = { | |
41 | .recalc = module_clk_recalc, | |
42 | }; | |
43 | ||
b68d8201 | 44 | static unsigned long bus_clk_recalc(struct clk *clk) |
7d740a06 | 45 | { |
9d56dd3b | 46 | int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); |
b68d8201 | 47 | return clk->parent->rate / bfc_divisors[idx]; |
7d740a06 YS |
48 | } |
49 | ||
50 | static struct clk_ops sh7763_bus_clk_ops = { | |
51 | .recalc = bus_clk_recalc, | |
52 | }; | |
53 | ||
7d740a06 | 54 | static struct clk_ops sh7763_cpu_clk_ops = { |
a02cb230 | 55 | .recalc = followparent_recalc, |
7d740a06 YS |
56 | }; |
57 | ||
58 | static struct clk_ops *sh7763_clk_ops[] = { | |
59 | &sh7763_master_clk_ops, | |
60 | &sh7763_module_clk_ops, | |
61 | &sh7763_bus_clk_ops, | |
62 | &sh7763_cpu_clk_ops, | |
63 | }; | |
64 | ||
65 | void __init arch_init_clk_ops(struct clk_ops **ops, int idx) | |
66 | { | |
67 | if (idx < ARRAY_SIZE(sh7763_clk_ops)) | |
68 | *ops = sh7763_clk_ops[idx]; | |
69 | } | |
70 | ||
b68d8201 | 71 | static unsigned long shyway_clk_recalc(struct clk *clk) |
7d740a06 | 72 | { |
9d56dd3b | 73 | int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); |
b68d8201 | 74 | return clk->parent->rate / cfc_divisors[idx]; |
7d740a06 YS |
75 | } |
76 | ||
77 | static struct clk_ops sh7763_shyway_clk_ops = { | |
78 | .recalc = shyway_clk_recalc, | |
79 | }; | |
80 | ||
81 | static struct clk sh7763_shyway_clk = { | |
4ff29ff8 | 82 | .flags = CLK_ENABLE_ON_INIT, |
7d740a06 YS |
83 | .ops = &sh7763_shyway_clk_ops, |
84 | }; | |
85 | ||
86 | /* | |
87 | * Additional SH7763-specific on-chip clocks that aren't already part of the | |
88 | * clock framework | |
89 | */ | |
90 | static struct clk *sh7763_onchip_clocks[] = { | |
91 | &sh7763_shyway_clk, | |
92 | }; | |
93 | ||
d6a94217 MD |
94 | static struct clk_lookup lookups[] = { |
95 | /* main clocks */ | |
96 | CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk), | |
97 | }; | |
98 | ||
9fe5ee0e | 99 | int __init arch_clk_init(void) |
7d740a06 | 100 | { |
253b0887 | 101 | struct clk *clk; |
f5c84cf5 | 102 | int i, ret = 0; |
7d740a06 | 103 | |
253b0887 PM |
104 | cpg_clk_init(); |
105 | ||
106 | clk = clk_get(NULL, "master_clk"); | |
7d740a06 YS |
107 | for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) { |
108 | struct clk *clkp = sh7763_onchip_clocks[i]; | |
109 | ||
110 | clkp->parent = clk; | |
f5c84cf5 | 111 | ret |= clk_register(clkp); |
7d740a06 YS |
112 | } |
113 | ||
7d740a06 YS |
114 | clk_put(clk); |
115 | ||
d6a94217 MD |
116 | clkdev_add_table(lookups, ARRAY_SIZE(lookups)); |
117 | ||
f5c84cf5 | 118 | return ret; |
7d740a06 | 119 | } |