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7d740a06 YS |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7763.c | |
3 | * | |
4 | * SH7763 support for the clock framework | |
5 | * | |
6 | * Copyright (C) 2005 Paul Mundt | |
7 | * Copyright (C) 2007 Yoshihiro Shimoda | |
8 | * | |
9 | * This file is subject to the terms and conditions of the GNU General Public | |
10 | * License. See the file "COPYING" in the main directory of this archive | |
11 | * for more details. | |
12 | */ | |
13 | #include <linux/init.h> | |
14 | #include <linux/kernel.h> | |
15 | #include <asm/clock.h> | |
16 | #include <asm/freq.h> | |
17 | #include <asm/io.h> | |
18 | ||
19 | static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; | |
20 | static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 }; | |
7d740a06 YS |
21 | static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 }; |
22 | ||
23 | static void master_clk_init(struct clk *clk) | |
24 | { | |
9d56dd3b | 25 | clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07]; |
7d740a06 YS |
26 | } |
27 | ||
28 | static struct clk_ops sh7763_master_clk_ops = { | |
29 | .init = master_clk_init, | |
30 | }; | |
31 | ||
b68d8201 | 32 | static unsigned long module_clk_recalc(struct clk *clk) |
7d740a06 | 33 | { |
9d56dd3b | 34 | int idx = ((__raw_readl(FRQCR) >> 4) & 0x07); |
b68d8201 | 35 | return clk->parent->rate / p0fc_divisors[idx]; |
7d740a06 YS |
36 | } |
37 | ||
38 | static struct clk_ops sh7763_module_clk_ops = { | |
39 | .recalc = module_clk_recalc, | |
40 | }; | |
41 | ||
b68d8201 | 42 | static unsigned long bus_clk_recalc(struct clk *clk) |
7d740a06 | 43 | { |
9d56dd3b | 44 | int idx = ((__raw_readl(FRQCR) >> 16) & 0x07); |
b68d8201 | 45 | return clk->parent->rate / bfc_divisors[idx]; |
7d740a06 YS |
46 | } |
47 | ||
48 | static struct clk_ops sh7763_bus_clk_ops = { | |
49 | .recalc = bus_clk_recalc, | |
50 | }; | |
51 | ||
7d740a06 | 52 | static struct clk_ops sh7763_cpu_clk_ops = { |
a02cb230 | 53 | .recalc = followparent_recalc, |
7d740a06 YS |
54 | }; |
55 | ||
56 | static struct clk_ops *sh7763_clk_ops[] = { | |
57 | &sh7763_master_clk_ops, | |
58 | &sh7763_module_clk_ops, | |
59 | &sh7763_bus_clk_ops, | |
60 | &sh7763_cpu_clk_ops, | |
61 | }; | |
62 | ||
63 | void __init arch_init_clk_ops(struct clk_ops **ops, int idx) | |
64 | { | |
65 | if (idx < ARRAY_SIZE(sh7763_clk_ops)) | |
66 | *ops = sh7763_clk_ops[idx]; | |
67 | } | |
68 | ||
b68d8201 | 69 | static unsigned long shyway_clk_recalc(struct clk *clk) |
7d740a06 | 70 | { |
9d56dd3b | 71 | int idx = ((__raw_readl(FRQCR) >> 20) & 0x07); |
b68d8201 | 72 | return clk->parent->rate / cfc_divisors[idx]; |
7d740a06 YS |
73 | } |
74 | ||
75 | static struct clk_ops sh7763_shyway_clk_ops = { | |
76 | .recalc = shyway_clk_recalc, | |
77 | }; | |
78 | ||
79 | static struct clk sh7763_shyway_clk = { | |
80 | .name = "shyway_clk", | |
4ff29ff8 | 81 | .flags = CLK_ENABLE_ON_INIT, |
7d740a06 YS |
82 | .ops = &sh7763_shyway_clk_ops, |
83 | }; | |
84 | ||
85 | /* | |
86 | * Additional SH7763-specific on-chip clocks that aren't already part of the | |
87 | * clock framework | |
88 | */ | |
89 | static struct clk *sh7763_onchip_clocks[] = { | |
90 | &sh7763_shyway_clk, | |
91 | }; | |
92 | ||
9fe5ee0e | 93 | int __init arch_clk_init(void) |
7d740a06 | 94 | { |
253b0887 | 95 | struct clk *clk; |
f5c84cf5 | 96 | int i, ret = 0; |
7d740a06 | 97 | |
253b0887 PM |
98 | cpg_clk_init(); |
99 | ||
100 | clk = clk_get(NULL, "master_clk"); | |
7d740a06 YS |
101 | for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) { |
102 | struct clk *clkp = sh7763_onchip_clocks[i]; | |
103 | ||
104 | clkp->parent = clk; | |
f5c84cf5 | 105 | ret |= clk_register(clkp); |
7d740a06 YS |
106 | } |
107 | ||
7d740a06 YS |
108 | clk_put(clk); |
109 | ||
f5c84cf5 | 110 | return ret; |
7d740a06 | 111 | } |