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36ddf31b | 1 | /* |
58862699 | 2 | * arch/sh/kernel/cpu/sh4a/clock-sh7780.c |
36ddf31b PM |
3 | * |
4 | * SH7780 support for the clock framework | |
5 | * | |
6 | * Copyright (C) 2005 Paul Mundt | |
7 | * | |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/kernel.h> | |
14 | #include <asm/clock.h> | |
15 | #include <asm/freq.h> | |
16 | #include <asm/io.h> | |
17 | ||
18 | static int ifc_divisors[] = { 2, 4 }; | |
19 | static int bfc_divisors[] = { 1, 1, 1, 8, 12, 16, 24, 1 }; | |
20 | static int pfc_divisors[] = { 1, 24, 24, 1 }; | |
21 | static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 }; | |
22 | ||
23 | static void master_clk_init(struct clk *clk) | |
24 | { | |
25 | clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003]; | |
26 | } | |
27 | ||
28 | static struct clk_ops sh7780_master_clk_ops = { | |
29 | .init = master_clk_init, | |
30 | }; | |
31 | ||
32 | static void module_clk_recalc(struct clk *clk) | |
33 | { | |
34 | int idx = (ctrl_inl(FRQCR) & 0x0003); | |
35 | clk->rate = clk->parent->rate / pfc_divisors[idx]; | |
36 | } | |
37 | ||
38 | static struct clk_ops sh7780_module_clk_ops = { | |
39 | .recalc = module_clk_recalc, | |
40 | }; | |
41 | ||
42 | static void bus_clk_recalc(struct clk *clk) | |
43 | { | |
44 | int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007); | |
45 | clk->rate = clk->parent->rate / bfc_divisors[idx]; | |
46 | } | |
47 | ||
48 | static struct clk_ops sh7780_bus_clk_ops = { | |
49 | .recalc = bus_clk_recalc, | |
50 | }; | |
51 | ||
52 | static void cpu_clk_recalc(struct clk *clk) | |
53 | { | |
54 | int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001); | |
55 | clk->rate = clk->parent->rate / ifc_divisors[idx]; | |
56 | } | |
57 | ||
58 | static struct clk_ops sh7780_cpu_clk_ops = { | |
59 | .recalc = cpu_clk_recalc, | |
60 | }; | |
61 | ||
62 | static struct clk_ops *sh7780_clk_ops[] = { | |
63 | &sh7780_master_clk_ops, | |
64 | &sh7780_module_clk_ops, | |
65 | &sh7780_bus_clk_ops, | |
66 | &sh7780_cpu_clk_ops, | |
67 | }; | |
68 | ||
69 | void __init arch_init_clk_ops(struct clk_ops **ops, int idx) | |
70 | { | |
71 | if (idx < ARRAY_SIZE(sh7780_clk_ops)) | |
72 | *ops = sh7780_clk_ops[idx]; | |
73 | } | |
74 | ||
75 | static void shyway_clk_recalc(struct clk *clk) | |
76 | { | |
77 | int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007); | |
78 | clk->rate = clk->parent->rate / cfc_divisors[idx]; | |
79 | } | |
80 | ||
81 | static struct clk_ops sh7780_shyway_clk_ops = { | |
82 | .recalc = shyway_clk_recalc, | |
83 | }; | |
84 | ||
85 | static struct clk sh7780_shyway_clk = { | |
86 | .name = "shyway_clk", | |
87 | .flags = CLK_ALWAYS_ENABLED, | |
88 | .ops = &sh7780_shyway_clk_ops, | |
89 | }; | |
90 | ||
91 | /* | |
92 | * Additional SH7780-specific on-chip clocks that aren't already part of the | |
93 | * clock framework | |
94 | */ | |
95 | static struct clk *sh7780_onchip_clocks[] = { | |
96 | &sh7780_shyway_clk, | |
97 | }; | |
98 | ||
99 | static int __init sh7780_clk_init(void) | |
100 | { | |
1d118562 | 101 | struct clk *clk = clk_get(NULL, "master_clk"); |
36ddf31b PM |
102 | int i; |
103 | ||
104 | for (i = 0; i < ARRAY_SIZE(sh7780_onchip_clocks); i++) { | |
105 | struct clk *clkp = sh7780_onchip_clocks[i]; | |
106 | ||
107 | clkp->parent = clk; | |
108 | clk_register(clkp); | |
109 | clk_enable(clkp); | |
110 | } | |
111 | ||
112 | /* | |
113 | * Now that we have the rest of the clocks registered, we need to | |
114 | * force the parent clock to propagate so that these clocks will | |
115 | * automatically figure out their rate. We cheat by handing the | |
116 | * parent clock its current rate and forcing child propagation. | |
117 | */ | |
118 | clk_set_rate(clk, clk_get_rate(clk)); | |
119 | ||
120 | clk_put(clk); | |
121 | ||
122 | return 0; | |
123 | } | |
124 | ||
125 | arch_initcall(sh7780_clk_init); | |
126 |