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55ba99eb KM |
1 | /* |
2 | * arch/sh/kernel/cpu/sh4a/clock-sh7786.c | |
3 | * | |
4 | * SH7786 support for the clock framework | |
5 | * | |
43a1839c | 6 | * Copyright (C) 2010 Paul Mundt |
55ba99eb KM |
7 | * |
8 | * This file is subject to the terms and conditions of the GNU General Public | |
9 | * License. See the file "COPYING" in the main directory of this archive | |
10 | * for more details. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/kernel.h> | |
43a1839c PM |
14 | #include <linux/clk.h> |
15 | #include <linux/io.h> | |
55ba99eb KM |
16 | #include <asm/clock.h> |
17 | #include <asm/freq.h> | |
55ba99eb | 18 | |
43a1839c PM |
19 | /* |
20 | * Default rate for the root input clock, reset this with clk_set_rate() | |
21 | * from the platform code. | |
22 | */ | |
23 | static struct clk extal_clk = { | |
24 | .name = "extal", | |
25 | .id = -1, | |
26 | .rate = 33333333, | |
55ba99eb KM |
27 | }; |
28 | ||
43a1839c | 29 | static unsigned long pll_recalc(struct clk *clk) |
55ba99eb | 30 | { |
43a1839c | 31 | int multiplier; |
55ba99eb | 32 | |
43a1839c PM |
33 | /* |
34 | * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1, | |
35 | * while modes 3, 4, and 5 use an x32. | |
36 | */ | |
37 | multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32; | |
55ba99eb | 38 | |
43a1839c | 39 | return clk->parent->rate * multiplier; |
55ba99eb KM |
40 | } |
41 | ||
43a1839c PM |
42 | static struct clk_ops pll_clk_ops = { |
43 | .recalc = pll_recalc, | |
55ba99eb KM |
44 | }; |
45 | ||
43a1839c PM |
46 | static struct clk pll_clk = { |
47 | .name = "pll_clk", | |
48 | .id = -1, | |
49 | .ops = &pll_clk_ops, | |
50 | .parent = &extal_clk, | |
51 | .flags = CLK_ENABLE_ON_INIT, | |
55ba99eb KM |
52 | }; |
53 | ||
43a1839c PM |
54 | static struct clk *clks[] = { |
55 | &extal_clk, | |
56 | &pll_clk, | |
55ba99eb KM |
57 | }; |
58 | ||
43a1839c PM |
59 | static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18, |
60 | 24, 32, 36, 48 }; | |
55ba99eb | 61 | |
43a1839c PM |
62 | static struct clk_div_mult_table div4_table = { |
63 | .divisors = div2, | |
64 | .nr_divisors = ARRAY_SIZE(div2), | |
55ba99eb KM |
65 | }; |
66 | ||
43a1839c | 67 | enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR }; |
55ba99eb | 68 | |
43a1839c PM |
69 | #define DIV4(_str, _bit, _mask, _flags) \ |
70 | SH_CLK_DIV4(_str, &pll_clk, FRQMR1, _bit, _mask, _flags) | |
55ba99eb | 71 | |
43a1839c PM |
72 | struct clk div4_clks[DIV4_NR] = { |
73 | [DIV4_P] = DIV4("peripheral_clk", 0, 0x0b40, 0), | |
74 | [DIV4_DU] = DIV4("du_clk", 4, 0x0010, 0), | |
75 | [DIV4_DDR] = DIV4("ddr_clk", 12, 0x0002, CLK_ENABLE_ON_INIT), | |
76 | [DIV4_B] = DIV4("bus_clk", 16, 0x0360, CLK_ENABLE_ON_INIT), | |
77 | [DIV4_SH] = DIV4("shyway_clk", 20, 0x0002, CLK_ENABLE_ON_INIT), | |
78 | [DIV4_I] = DIV4("cpu_clk", 28, 0x0006, CLK_ENABLE_ON_INIT), | |
55ba99eb KM |
79 | }; |
80 | ||
43a1839c PM |
81 | #define MSTPCR0 0xffc40030 |
82 | #define MSTPCR1 0xffc40034 | |
83 | ||
84 | static struct clk mstp_clks[] = { | |
85 | /* MSTPCR0 */ | |
86 | SH_CLK_MSTP32("scif_fck", 5, &div4_clks[DIV4_P], MSTPCR0, 29, 0), | |
87 | SH_CLK_MSTP32("scif_fck", 4, &div4_clks[DIV4_P], MSTPCR0, 28, 0), | |
88 | SH_CLK_MSTP32("scif_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 27, 0), | |
89 | SH_CLK_MSTP32("scif_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 26, 0), | |
90 | SH_CLK_MSTP32("scif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 25, 0), | |
91 | SH_CLK_MSTP32("scif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 24, 0), | |
92 | SH_CLK_MSTP32("ssi_fck", 3, &div4_clks[DIV4_P], MSTPCR0, 23, 0), | |
93 | SH_CLK_MSTP32("ssi_fck", 2, &div4_clks[DIV4_P], MSTPCR0, 22, 0), | |
94 | SH_CLK_MSTP32("ssi_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 21, 0), | |
95 | SH_CLK_MSTP32("ssi_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 20, 0), | |
96 | SH_CLK_MSTP32("hac_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 17, 0), | |
97 | SH_CLK_MSTP32("hac_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 16, 0), | |
98 | SH_CLK_MSTP32("i2c_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 15, 0), | |
99 | SH_CLK_MSTP32("i2c_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 14, 0), | |
100 | SH_CLK_MSTP32("tmu9_11_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 11, 0), | |
101 | SH_CLK_MSTP32("tmu678_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 10, 0), | |
102 | SH_CLK_MSTP32("tmu345_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 9, 0), | |
103 | SH_CLK_MSTP32("tmu012_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 8, 0), | |
104 | SH_CLK_MSTP32("sdif_fck", 1, &div4_clks[DIV4_P], MSTPCR0, 5, 0), | |
105 | SH_CLK_MSTP32("sdif_fck", 0, &div4_clks[DIV4_P], MSTPCR0, 4, 0), | |
106 | SH_CLK_MSTP32("hspi_fck", -1, &div4_clks[DIV4_P], MSTPCR0, 2, 0), | |
107 | ||
108 | /* MSTPCR1 */ | |
109 | SH_CLK_MSTP32("usb_fck", -1, NULL, MSTPCR1, 12, 0), | |
110 | SH_CLK_MSTP32("pcie_fck", 2, NULL, MSTPCR1, 10, 0), | |
111 | SH_CLK_MSTP32("pcie_fck", 1, NULL, MSTPCR1, 9, 0), | |
112 | SH_CLK_MSTP32("pcie_fck", 0, NULL, MSTPCR1, 8, 0), | |
113 | SH_CLK_MSTP32("dmac_11_6_fck", -1, NULL, MSTPCR1, 5, 0), | |
114 | SH_CLK_MSTP32("dmac_5_0_fck", -1, NULL, MSTPCR1, 4, 0), | |
115 | SH_CLK_MSTP32("du_fck", -1, NULL, MSTPCR1, 3, 0), | |
116 | SH_CLK_MSTP32("ether_fck", -1, NULL, MSTPCR1, 2, 0), | |
55ba99eb KM |
117 | }; |
118 | ||
9fe5ee0e | 119 | int __init arch_clk_init(void) |
55ba99eb | 120 | { |
f5c84cf5 | 121 | int i, ret = 0; |
55ba99eb | 122 | |
43a1839c PM |
123 | for (i = 0; i < ARRAY_SIZE(clks); i++) |
124 | ret |= clk_register(clks[i]); | |
55ba99eb | 125 | |
43a1839c PM |
126 | if (!ret) |
127 | ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks), | |
128 | &div4_table); | |
129 | if (!ret) | |
130 | ret = sh_clk_mstp32_register(mstp_clks, ARRAY_SIZE(mstp_clks)); | |
55ba99eb | 131 | |
f5c84cf5 | 132 | return ret; |
55ba99eb | 133 | } |