[mirror_ubuntu-jammy-kernel.git] / arch / sh / kernel / cpu / sh4a / clock-sh7786.c

// SPDX-License-Identifier: GPL-2.0
/*
 * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
 *
 * SH7786 support for the clock framework
 *
 *  Copyright (C) 2010  Paul Mundt
 */
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/clkdev.h>
#include <asm/clock.h>
#include <asm/freq.h>

/*
 * Default rate for the root input clock, reset this with clk_set_rate()
 * from the platform code.
 */
static struct clk extal_clk = {
	.rate		= 33333333,
};

static unsigned long pll_recalc(struct clk *clk)
{
	int multiplier;

	/*
	 * Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
	 * while modes 3, 4, and 5 use an x32.
	 */
	multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;

	return clk->parent->rate * multiplier;
}

static struct sh_clk_ops pll_clk_ops = {
	.recalc		= pll_recalc,
};

static struct clk pll_clk = {
	.ops		= &pll_clk_ops,
	.parent		= &extal_clk,
	.flags		= CLK_ENABLE_ON_INIT,
};

static struct clk *clks[] = {
	&extal_clk,
	&pll_clk,
};

static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
			       24, 32, 36, 48 };

static struct clk_div_mult_table div4_div_mult_table = {
	.divisors = div2,
	.nr_divisors = ARRAY_SIZE(div2),
};

static struct clk_div4_table div4_table = {
	.div_mult_table = &div4_div_mult_table,
};

enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };

#define DIV4(_bit, _mask, _flags) \
  SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)

struct clk div4_clks[DIV4_NR] = {
	[DIV4_P] = DIV4(0, 0x0b40, 0),
	[DIV4_DU] = DIV4(4, 0x0010, 0),
	[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
	[DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
	[DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
	[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
};

#define MSTPCR0		0xffc40030
#define MSTPCR1		0xffc40034

enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
       MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
       MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
       MSTP005, MSTP004, MSTP002,
       MSTP112, MSTP110, MSTP109, MSTP108,
       MSTP105, MSTP104, MSTP103, MSTP102,
       MSTP_NR };

static struct clk mstp_clks[MSTP_NR] = {
	/* MSTPCR0 */
	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
	[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
	[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
	[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
	[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
	[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
	[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
	[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
	[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
	[MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
	[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
	[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),

	/* MSTPCR1 */
	[MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
	[MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
	[MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
	[MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
	[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
	[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
	[MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
	[MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
};

static struct clk_lookup lookups[] = {
	/* main clocks */
	CLKDEV_CON_ID("extal", &extal_clk),
	CLKDEV_CON_ID("pll_clk", &pll_clk),

	/* DIV4 clocks */
	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),

	/* MSTP32 clocks */
	CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
	CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
	CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
	CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
	CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
	CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP024]),

	CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
	CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
	CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
	CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
	CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
	CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
	CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
	CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),

	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
	CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
	CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP010]),
	CLKDEV_ICK_ID("fck", "sh-tmu.3", &mstp_clks[MSTP011]),

	CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
	CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
	CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
	CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
	CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
	CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
	CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
	CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
	CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
	CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
	CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
};

int __init arch_clk_init(void)
{
	int i, ret = 0;

	for (i = 0; i < ARRAY_SIZE(clks); i++)
		ret |= clk_register(clks[i]);

	clkdev_add_table(lookups, ARRAY_SIZE(lookups));

	if (!ret)
		ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
					   &div4_table);
	if (!ret)
		ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);

	return ret;
}
Commit	Line	Data
add5ca2c	1	// SPDX-License-Identifier: GPL-2.0
55ba99eb KM	2	/*
	3	* arch/sh/kernel/cpu/sh4a/clock-sh7786.c
	4	*
	5	* SH7786 support for the clock framework
	6	*
43a1839c	7	* Copyright (C) 2010 Paul Mundt
55ba99eb KM	8	*/
	9	#include <linux/init.h>
	10	#include <linux/kernel.h>
43a1839c PM	11	#include <linux/clk.h>
43a1839c PM	12	#include <linux/io.h>
6d803ba7	13	#include <linux/clkdev.h>
55ba99eb KM	14	#include <asm/clock.h>
55ba99eb KM	15	#include <asm/freq.h>
55ba99eb	16
43a1839c PM	17	/*
	18	* Default rate for the root input clock, reset this with clk_set_rate()
	19	* from the platform code.
	20	*/
	21	static struct clk extal_clk = {
43a1839c	22	.rate = 33333333,
55ba99eb KM	23	};
55ba99eb KM	24
43a1839c	25	static unsigned long pll_recalc(struct clk *clk)
55ba99eb	26	{
43a1839c	27	int multiplier;
55ba99eb	28
43a1839c PM	29	/*
	30	* Clock modes 0, 1, and 2 use an x64 multiplier against PLL1,
	31	* while modes 3, 4, and 5 use an x32.
	32	*/
	33	multiplier = (sh_mv.mv_mode_pins() & 0xf) < 3 ? 64 : 32;
55ba99eb	34
43a1839c	35	return clk->parent->rate * multiplier;
55ba99eb KM	36	}
55ba99eb KM	37
33cb61a4	38	static struct sh_clk_ops pll_clk_ops = {
43a1839c	39	.recalc = pll_recalc,
55ba99eb KM	40	};
55ba99eb KM	41
43a1839c	42	static struct clk pll_clk = {
43a1839c PM	43	.ops = &pll_clk_ops,
	44	.parent = &extal_clk,
	45	.flags = CLK_ENABLE_ON_INIT,
55ba99eb KM	46	};
55ba99eb KM	47
43a1839c PM	48	static struct clk *clks[] = {
	49	&extal_clk,
	50	&pll_clk,
55ba99eb KM	51	};
55ba99eb KM	52
43a1839c PM	53	static unsigned int div2[] = { 1, 2, 4, 6, 8, 12, 16, 18,
43a1839c PM	54	24, 32, 36, 48 };
55ba99eb	55
0a5f337e	56	static struct clk_div_mult_table div4_div_mult_table = {
43a1839c PM	57	.divisors = div2,
43a1839c PM	58	.nr_divisors = ARRAY_SIZE(div2),
55ba99eb KM	59	};
55ba99eb KM	60
0a5f337e MD	61	static struct clk_div4_table div4_table = {
	62	.div_mult_table = &div4_div_mult_table,
	63	};
	64
43a1839c	65	enum { DIV4_I, DIV4_SH, DIV4_B, DIV4_DDR, DIV4_DU, DIV4_P, DIV4_NR };
55ba99eb	66
914ebf0b MD	67	#define DIV4(_bit, _mask, _flags) \
914ebf0b MD	68	SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
55ba99eb	69
43a1839c	70	struct clk div4_clks[DIV4_NR] = {
914ebf0b MD	71	[DIV4_P] = DIV4(0, 0x0b40, 0),
	72	[DIV4_DU] = DIV4(4, 0x0010, 0),
	73	[DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
	74	[DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
	75	[DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
	76	[DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
55ba99eb KM	77	};
55ba99eb KM	78
43a1839c PM	79	#define MSTPCR0 0xffc40030
	80	#define MSTPCR1 0xffc40034
	81
8bc23d95 MD	82	enum { MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024,
	83	MSTP023, MSTP022, MSTP021, MSTP020, MSTP017, MSTP016,
	84	MSTP015, MSTP014, MSTP011, MSTP010, MSTP009, MSTP008,
	85	MSTP005, MSTP004, MSTP002,
	86	MSTP112, MSTP110, MSTP109, MSTP108,
	87	MSTP105, MSTP104, MSTP103, MSTP102,
	88	MSTP_NR };
	89
	90	static struct clk mstp_clks[MSTP_NR] = {
43a1839c	91	/* MSTPCR0 */
c77a9c3e MD	92	[MSTP029] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 29, 0),
	93	[MSTP028] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 28, 0),
	94	[MSTP027] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 27, 0),
	95	[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0),
	96	[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0),
	97	[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0),
	98	[MSTP023] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 23, 0),
	99	[MSTP022] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, 0),
	100	[MSTP021] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 21, 0),
	101	[MSTP020] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 20, 0),
	102	[MSTP017] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 17, 0),
	103	[MSTP016] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 16, 0),
	104	[MSTP015] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 15, 0),
	105	[MSTP014] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 14, 0),
	106	[MSTP011] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 11, 0),
	107	[MSTP010] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 10, 0),
	108	[MSTP009] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 9, 0),
	109	[MSTP008] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 8, 0),
	110	[MSTP005] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 5, 0),
	111	[MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
	112	[MSTP002] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 2, 0),
43a1839c PM	113
43a1839c PM	114	/* MSTPCR1 */
c77a9c3e MD	115	[MSTP112] = SH_CLK_MSTP32(NULL, MSTPCR1, 12, 0),
	116	[MSTP110] = SH_CLK_MSTP32(NULL, MSTPCR1, 10, 0),
	117	[MSTP109] = SH_CLK_MSTP32(NULL, MSTPCR1, 9, 0),
	118	[MSTP108] = SH_CLK_MSTP32(NULL, MSTPCR1, 8, 0),
	119	[MSTP105] = SH_CLK_MSTP32(NULL, MSTPCR1, 5, 0),
	120	[MSTP104] = SH_CLK_MSTP32(NULL, MSTPCR1, 4, 0),
	121	[MSTP103] = SH_CLK_MSTP32(NULL, MSTPCR1, 3, 0),
	122	[MSTP102] = SH_CLK_MSTP32(NULL, MSTPCR1, 2, 0),
55ba99eb KM	123	};
55ba99eb KM	124
e21d2aa7	125	static struct clk_lookup lookups[] = {
2cf79bea MD	126	/* main clocks */
	127	CLKDEV_CON_ID("extal", &extal_clk),
	128	CLKDEV_CON_ID("pll_clk", &pll_clk),
	129
1fe3d198 MD	130	/* DIV4 clocks */
	131	CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
	132	CLKDEV_CON_ID("du_clk", &div4_clks[DIV4_DU]),
	133	CLKDEV_CON_ID("ddr_clk", &div4_clks[DIV4_DDR]),
	134	CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
	135	CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
	136	CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
	137
d8ef3ccc	138	/* MSTP32 clocks */
fa3d39bf LP	139	CLKDEV_ICK_ID("fck", "sh-sci.5", &mstp_clks[MSTP029]),
	140	CLKDEV_ICK_ID("fck", "sh-sci.4", &mstp_clks[MSTP028]),
	141	CLKDEV_ICK_ID("fck", "sh-sci.3", &mstp_clks[MSTP027]),
	142	CLKDEV_ICK_ID("fck", "sh-sci.2", &mstp_clks[MSTP026]),
	143	CLKDEV_ICK_ID("fck", "sh-sci.1", &mstp_clks[MSTP025]),
	144	CLKDEV_ICK_ID("fck", "sh-sci.0", &mstp_clks[MSTP024]),
1f17e2a0	145
d8ef3ccc MD	146	CLKDEV_CON_ID("ssi3_fck", &mstp_clks[MSTP023]),
	147	CLKDEV_CON_ID("ssi2_fck", &mstp_clks[MSTP022]),
	148	CLKDEV_CON_ID("ssi1_fck", &mstp_clks[MSTP021]),
	149	CLKDEV_CON_ID("ssi0_fck", &mstp_clks[MSTP020]),
	150	CLKDEV_CON_ID("hac1_fck", &mstp_clks[MSTP017]),
	151	CLKDEV_CON_ID("hac0_fck", &mstp_clks[MSTP016]),
	152	CLKDEV_CON_ID("i2c1_fck", &mstp_clks[MSTP015]),
	153	CLKDEV_CON_ID("i2c0_fck", &mstp_clks[MSTP014]),
1f17e2a0	154
1399c195 LP	155	CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP008]),
	156	CLKDEV_ICK_ID("fck", "sh-tmu.1", &mstp_clks[MSTP009]),
	157	CLKDEV_ICK_ID("fck", "sh-tmu.2", &mstp_clks[MSTP010]),
	158	CLKDEV_ICK_ID("fck", "sh-tmu.3", &mstp_clks[MSTP011]),
1f17e2a0	159
d8ef3ccc MD	160	CLKDEV_CON_ID("sdif1_fck", &mstp_clks[MSTP005]),
	161	CLKDEV_CON_ID("sdif0_fck", &mstp_clks[MSTP004]),
	162	CLKDEV_CON_ID("hspi_fck", &mstp_clks[MSTP002]),
	163	CLKDEV_CON_ID("usb_fck", &mstp_clks[MSTP112]),
	164	CLKDEV_CON_ID("pcie2_fck", &mstp_clks[MSTP110]),
	165	CLKDEV_CON_ID("pcie1_fck", &mstp_clks[MSTP109]),
	166	CLKDEV_CON_ID("pcie0_fck", &mstp_clks[MSTP108]),
	167	CLKDEV_CON_ID("dmac_11_6_fck", &mstp_clks[MSTP105]),
	168	CLKDEV_CON_ID("dmac_5_0_fck", &mstp_clks[MSTP104]),
	169	CLKDEV_CON_ID("du_fck", &mstp_clks[MSTP103]),
	170	CLKDEV_CON_ID("ether_fck", &mstp_clks[MSTP102]),
e21d2aa7 PM	171	};
e21d2aa7 PM	172
9fe5ee0e	173	int __init arch_clk_init(void)
55ba99eb	174	{
f5c84cf5	175	int i, ret = 0;
55ba99eb	176
43a1839c PM	177	for (i = 0; i < ARRAY_SIZE(clks); i++)
43a1839c PM	178	ret \|= clk_register(clks[i]);
8a7711fc RK	179
8a7711fc RK	180	clkdev_add_table(lookups, ARRAY_SIZE(lookups));
55ba99eb	181
43a1839c PM	182	if (!ret)
	183	ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
	184	&div4_table);
	185	if (!ret)
ad3337cb	186	ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
55ba99eb	187
f5c84cf5	188	return ret;
55ba99eb	189	}