[mirror_ubuntu-jammy-kernel.git] / arch / sh / kernel / cpu / sh4a / setup-sh7366.c

// SPDX-License-Identifier: GPL-2.0
/*
 * SH7366 Setup
 *
 *  Copyright (C) 2008 Renesas Solutions
 *
 * Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
 */
#include <linux/platform_device.h>
#include <linux/init.h>
#include <linux/serial.h>
#include <linux/serial_sci.h>
#include <linux/uio_driver.h>
#include <linux/sh_timer.h>
#include <linux/sh_intc.h>
#include <linux/usb/r8a66597.h>
#include <asm/clock.h>

static struct plat_sci_port scif0_platform_data = {
	.scscr		= SCSCR_REIE,
	.type		= PORT_SCIF,
};

static struct resource scif0_resources[] = {
	DEFINE_RES_MEM(0xffe00000, 0x100),
	DEFINE_RES_IRQ(evt2irq(0xc00)),
};

static struct platform_device scif0_device = {
	.name		= "sh-sci",
	.id		= 0,
	.resource	= scif0_resources,
	.num_resources	= ARRAY_SIZE(scif0_resources),
	.dev		= {
		.platform_data	= &scif0_platform_data,
	},
};

static struct resource iic_resources[] = {
	[0] = {
		.name	= "IIC",
		.start  = 0x04470000,
		.end    = 0x04470017,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0xe00),
		.end    = evt2irq(0xe60),
		.flags  = IORESOURCE_IRQ,
       },
};

static struct platform_device iic_device = {
	.name           = "i2c-sh_mobile",
	.id             = 0, /* "i2c0" clock */
	.num_resources  = ARRAY_SIZE(iic_resources),
	.resource       = iic_resources,
};

static struct r8a66597_platdata r8a66597_data = {
	.on_chip = 1,
};

static struct resource usb_host_resources[] = {
	[0] = {
		.start  = 0xa4d80000,
		.end    = 0xa4d800ff,
		.flags  = IORESOURCE_MEM,
	},
	[1] = {
		.start  = evt2irq(0xa20),
		.end    = evt2irq(0xa20),
		.flags	= IORESOURCE_IRQ | IRQF_TRIGGER_LOW,
	},
};

static struct platform_device usb_host_device = {
	.name	= "r8a66597_hcd",
	.id	= -1,
	.dev = {
		.dma_mask		= NULL,
		.coherent_dma_mask	= 0xffffffff,
		.platform_data		= &r8a66597_data,
	},
	.num_resources	= ARRAY_SIZE(usb_host_resources),
	.resource	= usb_host_resources,
};

static struct uio_info vpu_platform_data = {
	.name = "VPU5",
	.version = "0",
	.irq = evt2irq(0x980),
};

static struct resource vpu_resources[] = {
	[0] = {
		.name	= "VPU",
		.start	= 0xfe900000,
		.end	= 0xfe902807,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device vpu_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 0,
	.dev = {
		.platform_data	= &vpu_platform_data,
	},
	.resource	= vpu_resources,
	.num_resources	= ARRAY_SIZE(vpu_resources),
};

static struct uio_info veu0_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = evt2irq(0x8c0),
};

static struct resource veu0_resources[] = {
	[0] = {
		.name	= "VEU(1)",
		.start	= 0xfe920000,
		.end	= 0xfe9200b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu0_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 1,
	.dev = {
		.platform_data	= &veu0_platform_data,
	},
	.resource	= veu0_resources,
	.num_resources	= ARRAY_SIZE(veu0_resources),
};

static struct uio_info veu1_platform_data = {
	.name = "VEU",
	.version = "0",
	.irq = evt2irq(0x560),
};

static struct resource veu1_resources[] = {
	[0] = {
		.name	= "VEU(2)",
		.start	= 0xfe924000,
		.end	= 0xfe9240b7,
		.flags	= IORESOURCE_MEM,
	},
	[1] = {
		/* place holder for contiguous memory */
	},
};

static struct platform_device veu1_device = {
	.name		= "uio_pdrv_genirq",
	.id		= 2,
	.dev = {
		.platform_data	= &veu1_platform_data,
	},
	.resource	= veu1_resources,
	.num_resources	= ARRAY_SIZE(veu1_resources),
};

static struct sh_timer_config cmt_platform_data = {
	.channels_mask = 0x20,
};

static struct resource cmt_resources[] = {
	DEFINE_RES_MEM(0x044a0000, 0x70),
	DEFINE_RES_IRQ(evt2irq(0xf00)),
};

static struct platform_device cmt_device = {
	.name		= "sh-cmt-32",
	.id		= 0,
	.dev = {
		.platform_data	= &cmt_platform_data,
	},
	.resource	= cmt_resources,
	.num_resources	= ARRAY_SIZE(cmt_resources),
};

static struct sh_timer_config tmu0_platform_data = {
	.channels_mask = 7,
};

static struct resource tmu0_resources[] = {
	DEFINE_RES_MEM(0xffd80000, 0x2c),
	DEFINE_RES_IRQ(evt2irq(0x400)),
	DEFINE_RES_IRQ(evt2irq(0x420)),
	DEFINE_RES_IRQ(evt2irq(0x440)),
};

static struct platform_device tmu0_device = {
	.name		= "sh-tmu",
	.id		= 0,
	.dev = {
		.platform_data	= &tmu0_platform_data,
	},
	.resource	= tmu0_resources,
	.num_resources	= ARRAY_SIZE(tmu0_resources),
};

static struct platform_device *sh7366_devices[] __initdata = {
	&scif0_device,
	&cmt_device,
	&tmu0_device,
	&iic_device,
	&usb_host_device,
	&vpu_device,
	&veu0_device,
	&veu1_device,
};

static int __init sh7366_devices_setup(void)
{
	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);

	return platform_add_devices(sh7366_devices,
				    ARRAY_SIZE(sh7366_devices));
}
arch_initcall(sh7366_devices_setup);

static struct platform_device *sh7366_early_devices[] __initdata = {
	&scif0_device,
	&cmt_device,
	&tmu0_device,
};

void __init plat_early_device_setup(void)
{
	early_platform_add_devices(sh7366_early_devices,
				   ARRAY_SIZE(sh7366_early_devices));
}

enum {
	UNUSED=0,
	ENABLED,
	DISABLED,

	/* interrupt sources */
	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	ICB,
	DMAC0, DMAC1, DMAC2, DMAC3,
	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	MFI, VPU, USB,
	MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
	DMAC4, DMAC5, DMAC_DADERR,
	SCIF, SCIFA1, SCIFA2,
	DENC, MSIOF,
	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
	SDHI, CMT, TSIF, SIU,
	TMU0, TMU1, TMU2,
	VEU2, LCDC,

	/* interrupt groups */

	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
};

static struct intc_vect vectors[] __initdata = {
	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	INTC_VECT(ICB, 0x700),
	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
	INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
	INTC_VECT(MMC_MMC3I, 0xb40),
	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	INTC_VECT(DMAC_DADERR, 0xbc0),
	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
	INTC_VECT(SCIFA2, 0xc40),
	INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	INTC_VECT(SIU, 0xf80),
	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	INTC_VECT(TMU2, 0x440),
	INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
};

static struct intc_group groups[] __initdata = {
	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
		   FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
};

static struct intc_mask_reg mask_registers[] __initdata = {
	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	  { } },
	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	  { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	  { 0, 0, 0, VPU, 0, 0, 0, MFI } },
	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	  { 0, 0, 0, ICB } },
	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	  { 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	  { 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	  { 0, 0, 0, 0, 0, 0, 0, MSIOF } },
	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	  { I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	    FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
	  { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	  { 0, 0, 0, CMT, 0, USB, } },
	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	  { 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	  { 0, 0, 0, 0, 0, 0, 0, TSIF } },
	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_prio_reg prio_registers[] __initdata = {
	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	{ 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
	{ 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	{ 0xa408002c, 0, 16, 4, /* IPRL */ { } },
	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_sense_reg sense_registers[] __initdata = {
	{ 0xa414001c, 16, 2, /* ICR1 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_mask_reg ack_registers[] __initdata = {
	{ 0xa4140024, 0, 8, /* INTREQ00 */
	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
};

static struct intc_desc intc_desc __initdata = {
	.name = "sh7366",
	.force_enable = ENABLED,
	.force_disable = DISABLED,
	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
			   prio_registers, sense_registers, ack_registers),
};

void __init plat_irq_setup(void)
{
	register_intc_controller(&intc_desc);
}

void __init plat_mem_setup(void)
{
	/* TODO: Register Node 1 */
}
Commit	Line	Data
add5ca2c	1	// SPDX-License-Identifier: GPL-2.0
9109a30e MD	2	/*
	3	* SH7366 Setup
	4	*
	5	* Copyright (C) 2008 Renesas Solutions
	6	*
	7	* Based on linux/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
9109a30e MD	8	*/
	9	#include <linux/platform_device.h>
	10	#include <linux/init.h>
	11	#include <linux/serial.h>
96de1a8f	12	#include <linux/serial_sci.h>
714750dd	13	#include <linux/uio_driver.h>
46a12f74	14	#include <linux/sh_timer.h>
58749400	15	#include <linux/sh_intc.h>
6b64929c	16	#include <linux/usb/r8a66597.h>
d7f1a9ad	17	#include <asm/clock.h>
9109a30e	18
bcac24d0	19	static struct plat_sci_port scif0_platform_data = {
c3fa400b	20	.scscr = SCSCR_REIE,
bcac24d0	21	.type = PORT_SCIF,
d850acf9 LP	22	};
	23
	24	static struct resource scif0_resources[] = {
	25	DEFINE_RES_MEM(0xffe00000, 0x100),
	26	DEFINE_RES_IRQ(evt2irq(0xc00)),
bcac24d0 MD	27	};
	28
	29	static struct platform_device scif0_device = {
	30	.name = "sh-sci",
	31	.id = 0,
d850acf9 LP	32	.resource = scif0_resources,
d850acf9 LP	33	.num_resources = ARRAY_SIZE(scif0_resources),
bcac24d0 MD	34	.dev = {
	35	.platform_data = &scif0_platform_data,
	36	},
	37	};
	38
0fff76f2 MD	39	static struct resource iic_resources[] = {
	40	[0] = {
	41	.name = "IIC",
	42	.start = 0x04470000,
	43	.end = 0x04470017,
	44	.flags = IORESOURCE_MEM,
	45	},
	46	[1] = {
58749400 PM	47	.start = evt2irq(0xe00),
58749400 PM	48	.end = evt2irq(0xe60),
0fff76f2 MD	49	.flags = IORESOURCE_IRQ,
	50	},
	51	};
	52
	53	static struct platform_device iic_device = {
	54	.name = "i2c-sh_mobile",
a5616bd0	55	.id = 0, /* "i2c0" clock */
0fff76f2 MD	56	.num_resources = ARRAY_SIZE(iic_resources),
	57	.resource = iic_resources,
	58	};
	59
6b64929c	60	static struct r8a66597_platdata r8a66597_data = {
719a72b7	61	.on_chip = 1,
6b64929c YS	62	};
6b64929c YS	63
47c2968c KM	64	static struct resource usb_host_resources[] = {
47c2968c KM	65	[0] = {
47c2968c KM	66	.start = 0xa4d80000,
	67	.end = 0xa4d800ff,
	68	.flags = IORESOURCE_MEM,
	69	},
	70	[1] = {
58749400 PM	71	.start = evt2irq(0xa20),
58749400 PM	72	.end = evt2irq(0xa20),
6b64929c	73	.flags = IORESOURCE_IRQ \| IRQF_TRIGGER_LOW,
47c2968c KM	74	},
	75	};
	76
	77	static struct platform_device usb_host_device = {
	78	.name = "r8a66597_hcd",
	79	.id = -1,
	80	.dev = {
	81	.dma_mask = NULL,
	82	.coherent_dma_mask = 0xffffffff,
6b64929c	83	.platform_data = &r8a66597_data,
47c2968c KM	84	},
	85	.num_resources = ARRAY_SIZE(usb_host_resources),
	86	.resource = usb_host_resources,
	87	};
	88
714750dd MD	89	static struct uio_info vpu_platform_data = {
	90	.name = "VPU5",
	91	.version = "0",
58749400	92	.irq = evt2irq(0x980),
714750dd MD	93	};
	94
	95	static struct resource vpu_resources[] = {
	96	[0] = {
	97	.name = "VPU",
	98	.start = 0xfe900000,
	99	.end = 0xfe902807,
	100	.flags = IORESOURCE_MEM,
	101	},
1eca5c92 MD	102	[1] = {
	103	/* place holder for contiguous memory */
	104	},
714750dd MD	105	};
	106
	107	static struct platform_device vpu_device = {
	108	.name = "uio_pdrv_genirq",
	109	.id = 0,
	110	.dev = {
	111	.platform_data = &vpu_platform_data,
	112	},
	113	.resource = vpu_resources,
	114	.num_resources = ARRAY_SIZE(vpu_resources),
	115	};
	116
	117	static struct uio_info veu0_platform_data = {
	118	.name = "VEU",
	119	.version = "0",
58749400	120	.irq = evt2irq(0x8c0),
714750dd MD	121	};
	122
	123	static struct resource veu0_resources[] = {
	124	[0] = {
	125	.name = "VEU(1)",
	126	.start = 0xfe920000,
	127	.end = 0xfe9200b7,
	128	.flags = IORESOURCE_MEM,
	129	},
1eca5c92 MD	130	[1] = {
	131	/* place holder for contiguous memory */
	132	},
714750dd MD	133	};
	134
	135	static struct platform_device veu0_device = {
	136	.name = "uio_pdrv_genirq",
	137	.id = 1,
	138	.dev = {
	139	.platform_data = &veu0_platform_data,
	140	},
	141	.resource = veu0_resources,
	142	.num_resources = ARRAY_SIZE(veu0_resources),
	143	};
	144
	145	static struct uio_info veu1_platform_data = {
	146	.name = "VEU",
	147	.version = "0",
58749400	148	.irq = evt2irq(0x560),
714750dd MD	149	};
	150
	151	static struct resource veu1_resources[] = {
	152	[0] = {
	153	.name = "VEU(2)",
	154	.start = 0xfe924000,
	155	.end = 0xfe9240b7,
	156	.flags = IORESOURCE_MEM,
	157	},
1eca5c92 MD	158	[1] = {
	159	/* place holder for contiguous memory */
	160	},
714750dd MD	161	};
	162
	163	static struct platform_device veu1_device = {
	164	.name = "uio_pdrv_genirq",
	165	.id = 2,
	166	.dev = {
	167	.platform_data = &veu1_platform_data,
	168	},
	169	.resource = veu1_resources,
	170	.num_resources = ARRAY_SIZE(veu1_resources),
	171	};
	172
46a12f74	173	static struct sh_timer_config cmt_platform_data = {
9b17e48c	174	.channels_mask = 0x20,
424f59d0 MD	175	};
	176
	177	static struct resource cmt_resources[] = {
9b17e48c LP	178	DEFINE_RES_MEM(0x044a0000, 0x70),
9b17e48c LP	179	DEFINE_RES_IRQ(evt2irq(0xf00)),
424f59d0 MD	180	};
	181
	182	static struct platform_device cmt_device = {
9b17e48c	183	.name = "sh-cmt-32",
424f59d0 MD	184	.id = 0,
	185	.dev = {
	186	.platform_data = &cmt_platform_data,
	187	},
	188	.resource = cmt_resources,
	189	.num_resources = ARRAY_SIZE(cmt_resources),
	190	};
	191
f2710ebc	192	static struct sh_timer_config tmu0_platform_data = {
1399c195	193	.channels_mask = 7,
f2710ebc MD	194	};
	195
	196	static struct resource tmu0_resources[] = {
1399c195 LP	197	DEFINE_RES_MEM(0xffd80000, 0x2c),
	198	DEFINE_RES_IRQ(evt2irq(0x400)),
	199	DEFINE_RES_IRQ(evt2irq(0x420)),
	200	DEFINE_RES_IRQ(evt2irq(0x440)),
f2710ebc MD	201	};
	202
	203	static struct platform_device tmu0_device = {
1399c195	204	.name = "sh-tmu",
f2710ebc MD	205	.id = 0,
	206	.dev = {
	207	.platform_data = &tmu0_platform_data,
	208	},
	209	.resource = tmu0_resources,
	210	.num_resources = ARRAY_SIZE(tmu0_resources),
	211	};
	212
9109a30e	213	static struct platform_device *sh7366_devices[] __initdata = {
bcac24d0	214	&scif0_device,
424f59d0	215	&cmt_device,
f2710ebc	216	&tmu0_device,
0fff76f2	217	&iic_device,
47c2968c	218	&usb_host_device,
714750dd MD	219	&vpu_device,
	220	&veu0_device,
	221	&veu1_device,
9109a30e MD	222	};
	223
	224	static int __init sh7366_devices_setup(void)
	225	{
1eca5c92 MD	226	platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
	227	platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
	228	platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
d7f1a9ad	229
9109a30e MD	230	return platform_add_devices(sh7366_devices,
	231	ARRAY_SIZE(sh7366_devices));
	232	}
955c9863	233	arch_initcall(sh7366_devices_setup);
9109a30e	234
28fde686	235	static struct platform_device *sh7366_early_devices[] __initdata = {
bcac24d0	236	&scif0_device,
28fde686	237	&cmt_device,
f2710ebc	238	&tmu0_device,
28fde686 MD	239	};
	240
	241	void __init plat_early_device_setup(void)
	242	{
	243	early_platform_add_devices(sh7366_early_devices,
	244	ARRAY_SIZE(sh7366_early_devices));
	245	}
	246
9109a30e MD	247	enum {
9109a30e MD	248	UNUSED=0,
9bbe7b98 MD	249	ENABLED,
9bbe7b98 MD	250	DISABLED,
9109a30e MD	251
	252	/* interrupt sources */
	253	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
	254	ICB,
	255	DMAC0, DMAC1, DMAC2, DMAC3,
	256	VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
	257	MFI, VPU, USB,
	258	MMC_MMC1I, MMC_MMC2I, MMC_MMC3I,
	259	DMAC4, DMAC5, DMAC_DADERR,
	260	SCIF, SCIFA1, SCIFA2,
	261	DENC, MSIOF,
	262	FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
	263	I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI,
9bbe7b98	264	SDHI, CMT, TSIF, SIU,
9109a30e MD	265	TMU0, TMU1, TMU2,
	266	VEU2, LCDC,
	267
	268	/* interrupt groups */
	269
9bbe7b98	270	DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C,
9109a30e MD	271	};
	272
	273	static struct intc_vect vectors[] __initdata = {
	274	INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
	275	INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
	276	INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
	277	INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
	278	INTC_VECT(ICB, 0x700),
	279	INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
	280	INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
	281	INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
	282	INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
	283	INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980), INTC_VECT(USB, 0xa20),
	284	INTC_VECT(MMC_MMC1I, 0xb00), INTC_VECT(MMC_MMC2I, 0xb20),
	285	INTC_VECT(MMC_MMC3I, 0xb40),
	286	INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
	287	INTC_VECT(DMAC_DADERR, 0xbc0),
	288	INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIFA1, 0xc20),
	289	INTC_VECT(SCIFA2, 0xc40),
	290	INTC_VECT(DENC, 0xc60), INTC_VECT(MSIOF, 0xc80),
	291	INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
	292	INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
	293	INTC_VECT(I2C_ALI, 0xe00), INTC_VECT(I2C_TACKI, 0xe20),
	294	INTC_VECT(I2C_WAITI, 0xe40), INTC_VECT(I2C_DTEI, 0xe60),
9bbe7b98 MD	295	INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
9bbe7b98 MD	296	INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
9109a30e MD	297	INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
	298	INTC_VECT(SIU, 0xf80),
	299	INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
	300	INTC_VECT(TMU2, 0x440),
714750dd	301	INTC_VECT(VEU2, 0x560), INTC_VECT(LCDC, 0x580),
9109a30e MD	302	};
	303
	304	static struct intc_group groups[] __initdata = {
	305	INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
	306	INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
	307	INTC_GROUP(MMC, MMC_MMC1I, MMC_MMC2I, MMC_MMC3I),
	308	INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
	309	INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
	310	FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
	311	INTC_GROUP(I2C, I2C_ALI, I2C_TACKI, I2C_WAITI, I2C_DTEI),
9109a30e MD	312	};
	313
	314	static struct intc_mask_reg mask_registers[] __initdata = {
	315	{ 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
	316	{ } },
	317	{ 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
	318	{ VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
	319	{ 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
	320	{ 0, 0, 0, VPU, 0, 0, 0, MFI } },
	321	{ 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
	322	{ 0, 0, 0, ICB } },
	323	{ 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
	324	{ 0, TMU2, TMU1, TMU0, VEU2, 0, 0, LCDC } },
	325	{ 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
	326	{ 0, DMAC_DADERR, DMAC5, DMAC4, DENC, SCIFA2, SCIFA1, SCIF } },
	327	{ 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
	328	{ 0, 0, 0, 0, 0, 0, 0, MSIOF } },
	329	{ 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
	330	{ I2C_DTEI, I2C_WAITI, I2C_TACKI, I2C_ALI,
	331	FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
	332	{ 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
9bbe7b98	333	{ DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
9109a30e MD	334	{ 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
	335	{ 0, 0, 0, CMT, 0, USB, } },
	336	{ 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
	337	{ 0, MMC_MMC3I, MMC_MMC2I, MMC_MMC1I } },
	338	{ 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
	339	{ 0, 0, 0, 0, 0, 0, 0, TSIF } },
	340	{ 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
	341	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	342	};
	343
	344	static struct intc_prio_reg prio_registers[] __initdata = {
	345	{ 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
	346	{ 0xa4080004, 0, 16, 4, /* IPRB */ { VEU2, LCDC, ICB } },
	347	{ 0xa4080008, 0, 16, 4, /* IPRC */ { } },
	348	{ 0xa408000c, 0, 16, 4, /* IPRD */ { } },
	349	{ 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
	350	{ 0xa4080014, 0, 16, 4, /* IPRF */ { 0, DMAC45, USB, CMT } },
	351	{ 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIFA1, SCIFA2, DENC } },
	352	{ 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF, 0, FLCTL, I2C } },
	353	{ 0xa4080020, 0, 16, 4, /* IPRI */ { 0, 0, TSIF, } },
	354	{ 0xa4080024, 0, 16, 4, /* IPRJ */ { 0, 0, SIU } },
	355	{ 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
	356	{ 0xa408002c, 0, 16, 4, /* IPRL */ { } },
	357	{ 0xa4140010, 0, 32, 4, /* INTPRI00 */
	358	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	359	};
	360
	361	static struct intc_sense_reg sense_registers[] __initdata = {
	362	{ 0xa414001c, 16, 2, /* ICR1 */
	363	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	364	};
	365
6bdfb22a YS	366	static struct intc_mask_reg ack_registers[] __initdata = {
	367	{ 0xa4140024, 0, 8, /* INTREQ00 */
	368	{ IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
	369	};
	370
9bbe7b98 MD	371	static struct intc_desc intc_desc __initdata = {
	372	.name = "sh7366",
	373	.force_enable = ENABLED,
	374	.force_disable = DISABLED,
	375	.hw = INTC_HW_DESC(vectors, groups, mask_registers,
	376	prio_registers, sense_registers, ack_registers),
	377	};
9109a30e MD	378
	379	void __init plat_irq_setup(void)
	380	{
	381	register_intc_controller(&intc_desc);
	382	}
	383
	384	void __init plat_mem_setup(void)
	385	{
	386	/* TODO: Register Node 1 */
	387	}