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sh: add mmc clock in clock-sh7757
[mirror_ubuntu-zesty-kernel.git] / arch / sh / kernel / cpu / sh4a / setup-sh7757.c
CommitLineData
c01f0f1a
YS		 1/*
2 * SH7757 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/serial.h>
15#include <linux/serial_sci.h>
16#include <linux/io.h>
17#include <linux/mm.h>
18#include <linux/sh_timer.h>
19
a9571d7b
MD		 20static struct plat_sci_port scif2_platform_data = {
21 .mapbase = 0xfe4b0000, /* SCIF2 */
22 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 23 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
24 .scbrr_algo_id = SCBRR_ALGO_2,
a9571d7b
MD		 25 .type = PORT_SCIF,
26 .irqs = { 40, 40, 40, 40 },
27};
28
29static struct platform_device scif2_device = {
30 .name = "sh-sci",
a7f5551c 31 .id = 0,
a9571d7b
MD		 32 .dev = {
33 .platform_data = &scif2_platform_data,
34 },
35};
36
37static struct plat_sci_port scif3_platform_data = {
38 .mapbase = 0xfe4c0000, /* SCIF3 */
39 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 40 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
41 .scbrr_algo_id = SCBRR_ALGO_2,
a9571d7b
MD		 42 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 },
44};
45
46static struct platform_device scif3_device = {
47 .name = "sh-sci",
a7f5551c 48 .id = 1,
a9571d7b
MD		 49 .dev = {
50 .platform_data = &scif3_platform_data,
51 },
52};
53
54static struct plat_sci_port scif4_platform_data = {
55 .mapbase = 0xfe4d0000, /* SCIF4 */
56 .flags = UPF_BOOT_AUTOCONF,
f43dc23d
PM		 57 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
58 .scbrr_algo_id = SCBRR_ALGO_2,
a9571d7b
MD		 59 .type = PORT_SCIF,
60 .irqs = { 104, 104, 104, 104 },
61};
62
63static struct platform_device scif4_device = {
64 .name = "sh-sci",
a7f5551c 65 .id = 2,
a9571d7b
MD		 66 .dev = {
67 .platform_data = &scif4_platform_data,
68 },
69};
70
c01f0f1a 71static struct sh_timer_config tmu0_platform_data = {
c01f0f1a
YS		 72 .channel_offset = 0x04,
73 .timer_bit = 0,
c01f0f1a
YS		 74 .clockevent_rating = 200,
75};
76
77static struct resource tmu0_resources[] = {
78 [0] = {
c01f0f1a
YS		 79 .start = 0xfe430008,
80 .end = 0xfe430013,
81 .flags = IORESOURCE_MEM,
82 },
83 [1] = {
84 .start = 28,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89static struct platform_device tmu0_device = {
90 .name = "sh_tmu",
91 .id = 0,
92 .dev = {
93 .platform_data = &tmu0_platform_data,
94 },
95 .resource = tmu0_resources,
96 .num_resources = ARRAY_SIZE(tmu0_resources),
97};
98
99static struct sh_timer_config tmu1_platform_data = {
c01f0f1a
YS		 100 .channel_offset = 0x10,
101 .timer_bit = 1,
c01f0f1a
YS		 102 .clocksource_rating = 200,
103};
104
105static struct resource tmu1_resources[] = {
106 [0] = {
c01f0f1a
YS		 107 .start = 0xfe430014,
108 .end = 0xfe43001f,
109 .flags = IORESOURCE_MEM,
110 },
111 [1] = {
112 .start = 29,
113 .flags = IORESOURCE_IRQ,
114 },
115};
116
117static struct platform_device tmu1_device = {
118 .name = "sh_tmu",
119 .id = 1,
120 .dev = {
121 .platform_data = &tmu1_platform_data,
122 },
123 .resource = tmu1_resources,
124 .num_resources = ARRAY_SIZE(tmu1_resources),
125};
126
d0371667
YS		 127static struct resource spi0_resources[] = {
128 [0] = {
129 .start = 0xfe002000,
130 .end = 0xfe0020ff,
131 .flags = IORESOURCE_MEM,
132 },
133 [1] = {
134 .start = 86,
135 .flags = IORESOURCE_IRQ,
136 },
137};
138
139static struct platform_device spi0_device = {
140 .name = "sh_spi",
141 .id = 0,
142 .dev = {
143 .dma_mask = NULL,
144 .coherent_dma_mask = 0xffffffff,
145 },
146 .num_resources = ARRAY_SIZE(spi0_resources),
147 .resource = spi0_resources,
148};
149
c01f0f1a 150static struct platform_device *sh7757_devices[] __initdata = {
a9571d7b
MD		 151 &scif2_device,
152 &scif3_device,
153 &scif4_device,
c01f0f1a
YS		 154 &tmu0_device,
155 &tmu1_device,
d0371667 156 &spi0_device,
c01f0f1a
YS		 157};
158
159static int __init sh7757_devices_setup(void)
160{
161 return platform_add_devices(sh7757_devices,
162 ARRAY_SIZE(sh7757_devices));
163}
164arch_initcall(sh7757_devices_setup);
165
a9571d7b
MD		 166static struct platform_device *sh7757_early_devices[] __initdata = {
167 &scif2_device,
168 &scif3_device,
169 &scif4_device,
170 &tmu0_device,
171 &tmu1_device,
172};
173
174void __init plat_early_device_setup(void)
175{
176 early_platform_add_devices(sh7757_early_devices,
177 ARRAY_SIZE(sh7757_early_devices));
178}
179
c01f0f1a
YS		 180enum {
181 UNUSED = 0,
182
183 /* interrupt sources */
184
185 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
186 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
187 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
188 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
189
190 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
191 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
192 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
193 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
194 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
195
c3721d5b
YS		 196 SDHI, DVC,
197 IRQ8, IRQ9, IRQ11, IRQ10, IRQ12, IRQ13, IRQ14, IRQ15,
198 TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
c01f0f1a 199 HUDI,
c01f0f1a 200 ARC4,
c3721d5b
YS		 201 DMAC0_5, DMAC6_7, DMAC8_11,
202 SCIF0, SCIF1, SCIF2, SCIF3, SCIF4,
203 USB0, USB1,
c01f0f1a 204 JMC,
c3721d5b 205 SPI0, SPI1,
c01f0f1a 206 TMR01, TMR23, TMR45,
c01f0f1a 207 FRT,
c3721d5b
YS		 208 LPC, LPC5, LPC6, LPC7, LPC8,
209 PECI0, PECI1, PECI2, PECI3, PECI4, PECI5,
c01f0f1a 210 ETHERC,
c3721d5b 211 ADC0, ADC1,
c01f0f1a 212 SIM,
c01f0f1a
YS		 213 IIC0_0, IIC0_1, IIC0_2, IIC0_3,
214 IIC1_0, IIC1_1, IIC1_2, IIC1_3,
215 IIC2_0, IIC2_1, IIC2_2, IIC2_3,
216 IIC3_0, IIC3_1, IIC3_2, IIC3_3,
217 IIC4_0, IIC4_1, IIC4_2, IIC4_3,
218 IIC5_0, IIC5_1, IIC5_2, IIC5_3,
219 IIC6_0, IIC6_1, IIC6_2, IIC6_3,
220 IIC7_0, IIC7_1, IIC7_2, IIC7_3,
221 IIC8_0, IIC8_1, IIC8_2, IIC8_3,
222 IIC9_0, IIC9_1, IIC9_2, IIC9_3,
c3721d5b
YS		 223 ONFICTL,
224 MMC1, MMC2,
225 ECCU,
226 PCIC,
227 G200,
228 RSPI,
c01f0f1a 229 SGPIO,
c3721d5b
YS		 230 DMINT12, DMINT13, DMINT14, DMINT15, DMINT16, DMINT17, DMINT18, DMINT19,
231 DMINT20, DMINT21, DMINT22, DMINT23,
232 DDRECC,
233 TSIP,
234 PCIE_BRIDGE,
235 WDT0B, WDT1B, WDT2B, WDT3B, WDT4B, WDT5B, WDT6B, WDT7B, WDT8B,
236 GETHER0, GETHER1, GETHER2,
237 PBIA, PBIB, PBIC,
238 DMAE2, DMAE3,
239 SERMUX2, SERMUX3,
c01f0f1a
YS		 240
241 /* interrupt groups */
242
243 TMU012, TMU345,
244};
245
246static struct intc_vect vectors[] __initdata = {
247 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
248 INTC_VECT(SDHI, 0x4c0),
249 INTC_VECT(DVC, 0x4e0),
250 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
251 INTC_VECT(IRQ10, 0x540),
c01f0f1a
YS		 252 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
253 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
254 INTC_VECT(HUDI, 0x600),
255 INTC_VECT(ARC4, 0x620),
c3721d5b
YS		 256 INTC_VECT(DMAC0_5, 0x640), INTC_VECT(DMAC0_5, 0x660),
257 INTC_VECT(DMAC0_5, 0x680), INTC_VECT(DMAC0_5, 0x6a0),
258 INTC_VECT(DMAC0_5, 0x6c0),
c01f0f1a
YS		 259 INTC_VECT(IRQ11, 0x6e0),
260 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
261 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
c3721d5b
YS		 262 INTC_VECT(DMAC0_5, 0x780), INTC_VECT(DMAC0_5, 0x7a0),
263 INTC_VECT(DMAC6_7, 0x7c0), INTC_VECT(DMAC6_7, 0x7e0),
c01f0f1a
YS		 264 INTC_VECT(USB0, 0x840),
265 INTC_VECT(IRQ12, 0x880),
266 INTC_VECT(JMC, 0x8a0),
267 INTC_VECT(SPI1, 0x8c0),
268 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
269 INTC_VECT(USB1, 0x920),
270 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
271 INTC_VECT(TMR45, 0xa40),
c01f0f1a
YS		 272 INTC_VECT(FRT, 0xa80),
273 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
274 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
275 INTC_VECT(LPC, 0xb20),
276 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
277 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
278 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
c3721d5b
YS		 279 INTC_VECT(PECI0, 0xc00), INTC_VECT(PECI1, 0xc20),
280 INTC_VECT(PECI2, 0xc40),
c01f0f1a
YS		 281 INTC_VECT(IRQ15, 0xc60),
282 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
283 INTC_VECT(SPI0, 0xcc0),
284 INTC_VECT(ADC1, 0xce0),
c3721d5b
YS		 285 INTC_VECT(DMAC8_11, 0xd00), INTC_VECT(DMAC8_11, 0xd20),
286 INTC_VECT(DMAC8_11, 0xd40), INTC_VECT(DMAC8_11, 0xd60),
c01f0f1a
YS		 287 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
288 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
289 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
290 INTC_VECT(TMU5, 0xe40),
291 INTC_VECT(ADC0, 0xe60),
292 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
293 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
294 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
295 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
296 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
297 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
298 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
299 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
300 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
301 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
302 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
303 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
304 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
305 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
306 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
c3721d5b
YS		 307 INTC_VECT(IIC6_2, 0x1920),
308 INTC_VECT(ONFICTL, 0x1960),
309 INTC_VECT(IIC6_3, 0x1980),
c01f0f1a
YS		 310 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
311 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
312 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
313 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
314 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
315 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
c3721d5b
YS		 316 INTC_VECT(MMC1, 0x1c60), INTC_VECT(MMC2, 0x1c80),
317 INTC_VECT(ECCU, 0x1cc0),
318 INTC_VECT(PCIC, 0x1ce0),
319 INTC_VECT(G200, 0x1d00),
320 INTC_VECT(RSPI, 0x1d80), INTC_VECT(RSPI, 0x1da0),
321 INTC_VECT(RSPI, 0x1dc0), INTC_VECT(RSPI, 0x1de0),
322 INTC_VECT(PECI3, 0x1ec0), INTC_VECT(PECI4, 0x1ee0),
323 INTC_VECT(PECI5, 0x1f00),
324 INTC_VECT(SGPIO, 0x1f80), INTC_VECT(SGPIO, 0x1fa0),
325 INTC_VECT(SGPIO, 0x1fc0),
326 INTC_VECT(DMINT12, 0x2400), INTC_VECT(DMINT13, 0x2420),
327 INTC_VECT(DMINT14, 0x2440), INTC_VECT(DMINT15, 0x2460),
328 INTC_VECT(DMINT16, 0x2480), INTC_VECT(DMINT17, 0x24e0),
329 INTC_VECT(DMINT18, 0x2500), INTC_VECT(DMINT19, 0x2520),
330 INTC_VECT(DMINT20, 0x2540), INTC_VECT(DMINT21, 0x2560),
331 INTC_VECT(DMINT22, 0x2580), INTC_VECT(DMINT23, 0x2600),
332 INTC_VECT(DDRECC, 0x2620),
333 INTC_VECT(TSIP, 0x2640),
334 INTC_VECT(PCIE_BRIDGE, 0x27c0),
335 INTC_VECT(WDT0B, 0x2800), INTC_VECT(WDT1B, 0x2820),
336 INTC_VECT(WDT2B, 0x2840), INTC_VECT(WDT3B, 0x2860),
337 INTC_VECT(WDT4B, 0x2880), INTC_VECT(WDT5B, 0x28a0),
338 INTC_VECT(WDT6B, 0x28c0), INTC_VECT(WDT7B, 0x28e0),
339 INTC_VECT(WDT8B, 0x2900),
340 INTC_VECT(GETHER0, 0x2960), INTC_VECT(GETHER1, 0x2980),
341 INTC_VECT(GETHER2, 0x29a0),
342 INTC_VECT(PBIA, 0x2a00), INTC_VECT(PBIB, 0x2a20),
343 INTC_VECT(PBIC, 0x2a40),
344 INTC_VECT(DMAE2, 0x2a60), INTC_VECT(DMAE3, 0x2a80),
345 INTC_VECT(SERMUX2, 0x2aa0), INTC_VECT(SERMUX3, 0x2b40),
346 INTC_VECT(LPC5, 0x2b60), INTC_VECT(LPC6, 0x2b80),
347 INTC_VECT(LPC7, 0x2c00), INTC_VECT(LPC8, 0x2c20),
c01f0f1a
YS		 348};
349
350static struct intc_group groups[] __initdata = {
351 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
352 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
353};
354
355static struct intc_mask_reg mask_registers[] __initdata = {
356 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
357 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
358
359 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
360 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
361 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
362 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
363 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
364 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
365 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
366 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
367 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
368
369 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
370 { 0, 0, 0, 0, 0, 0, 0, 0,
c3721d5b
YS		 371 0, DMAC8_11, 0, PECI0, LPC, FRT, 0, TMR45,
372 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0_5,
373 HUDI, 0, 0, SCIF3, SCIF2, SDHI, TMU345, TMU012
c01f0f1a
YS		 374 } },
375
376 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
377 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
378 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
c3721d5b 379 ADC1, 0, DMAC6_7, ADC0, SPI0, SIM, PECI2, PECI1,
c01f0f1a
YS		 380 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
381 } },
382
383 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
c3721d5b
YS		 384 { IIC4_1, IIC4_2, IIC5_0, ONFICTL, 0, 0, SGPIO, 0,
385 0, G200, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
c01f0f1a 386 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
c3721d5b 387 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, 0, IIC2_2
c01f0f1a
YS		 388 } },
389
c3721d5b
YS		 390 { 0xffd100d0, 0xffd100d4, 32, /* INT2MSKR3 / INT2MSKCR3 */
391 { MMC1, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, PECI5, MMC2,
c01f0f1a 392 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
c3721d5b 393 PCIC, 0, IIC4_0, 0, ECCU, RSPI, 0, IIC9_3,
c01f0f1a
YS		 394 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
395 } },
c3721d5b
YS		 396
397 { 0xffd20038, 0xffd2003c, 32, /* INT2MSKR4 / INT2MSKCR4 */
398 { WDT0B, WDT1B, WDT3B, GETHER0, 0, 0, 0, 0,
399 0, 0, 0, LPC7, SERMUX2, DMAE3, DMAE2, PBIC,
400 PBIB, PBIA, GETHER1, DMINT12, DMINT13, DMINT14, DMINT15, TSIP,
401 DMINT23, 0, DMINT21, LPC6, 0, DMINT16, 0, DMINT22
402 } },
403
404 { 0xffd200d0, 0xffd200d4, 32, /* INT2MSKR5 / INT2MSKCR5 */
405 { 0, WDT8B, WDT7B, WDT4B, 0, DMINT20, 0, 0,
406 DMINT19, DMINT18, LPC5, SERMUX3, WDT2B, GETHER2, 0, 0,
407 0, 0, PCIE_BRIDGE, 0, 0, 0, 0, LPC8,
408 DDRECC, 0, WDT6B, WDT5B, 0, 0, 0, DMINT17
409 } },
c01f0f1a
YS		 410};
411
412#define INTPRI 0xffd00010
413#define INT2PRI0 0xffd40000
414#define INT2PRI1 0xffd40004
415#define INT2PRI2 0xffd40008
416#define INT2PRI3 0xffd4000c
417#define INT2PRI4 0xffd40010
418#define INT2PRI5 0xffd40014
419#define INT2PRI6 0xffd40018
420#define INT2PRI7 0xffd4001c
421#define INT2PRI8 0xffd400a0
422#define INT2PRI9 0xffd400a4
423#define INT2PRI10 0xffd400a8
424#define INT2PRI11 0xffd400ac
425#define INT2PRI12 0xffd400b0
426#define INT2PRI13 0xffd400b4
427#define INT2PRI14 0xffd400b8
428#define INT2PRI15 0xffd400bc
429#define INT2PRI16 0xffd10000
430#define INT2PRI17 0xffd10004
431#define INT2PRI18 0xffd10008
432#define INT2PRI19 0xffd1000c
433#define INT2PRI20 0xffd10010
434#define INT2PRI21 0xffd10014
435#define INT2PRI22 0xffd10018
436#define INT2PRI23 0xffd1001c
437#define INT2PRI24 0xffd100a0
438#define INT2PRI25 0xffd100a4
439#define INT2PRI26 0xffd100a8
440#define INT2PRI27 0xffd100ac
441#define INT2PRI28 0xffd100b0
442#define INT2PRI29 0xffd100b4
443#define INT2PRI30 0xffd100b8
444#define INT2PRI31 0xffd100bc
c3721d5b
YS		 445#define INT2PRI32 0xffd20000
446#define INT2PRI33 0xffd20004
447#define INT2PRI34 0xffd20008
448#define INT2PRI35 0xffd2000c
449#define INT2PRI36 0xffd20010
450#define INT2PRI37 0xffd20014
451#define INT2PRI38 0xffd20018
452#define INT2PRI39 0xffd2001c
453#define INT2PRI40 0xffd200a0
454#define INT2PRI41 0xffd200a4
455#define INT2PRI42 0xffd200a8
456#define INT2PRI43 0xffd200ac
457#define INT2PRI44 0xffd200b0
458#define INT2PRI45 0xffd200b4
459#define INT2PRI46 0xffd200b8
460#define INT2PRI47 0xffd200bc
c01f0f1a
YS		 461
462static struct intc_prio_reg prio_registers[] __initdata = {
463 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
464 IRQ4, IRQ5, IRQ6, IRQ7 } },
465
466 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
467 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
c3721d5b
YS		 468 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, 0, IRQ8 } },
469 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0_5, ADC0, IRQ9 } },
c01f0f1a 470 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
c3721d5b
YS		 471 { INT2PRI5, 0, 32, 8, { TMR45, 0, FRT, LPC } },
472 { INT2PRI6, 0, 32, 8, { PECI0, ETHERC, DMAC8_11, 0 } },
c01f0f1a
YS		 473 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
474 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
475 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
c3721d5b
YS		 476 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2, PECI1 } },
477 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC6_7, IRQ14 } },
c01f0f1a
YS		 478 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
479 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
480
481 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
c3721d5b 482 { INT2PRI17, 0, 32, 8, { 0, 0, 0, IIC1_0 } },
c01f0f1a
YS		 483 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
484 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
485 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
486 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
c3721d5b
YS		 487 { INT2PRI22, 0, 32, 8, { IIC9_2, MMC2, G200, 0 } },
488 { INT2PRI23, 0, 32, 8, { PECI5, SGPIO, IIC3_2, IIC5_1 } },
489 { INT2PRI24, 0, 32, 8, { PECI4, PECI3, 0, IIC1_1 } },
c01f0f1a 490 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
c3721d5b
YS		 491 { INT2PRI26, 0, 32, 8, { ECCU, RSPI, 0, IIC9_3 } },
492 { INT2PRI27, 0, 32, 8, { PCIC, IIC6_0, IIC4_0, IIC6_1 } },
493 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, MMC1, IIC6_2 } },
c01f0f1a 494 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
c3721d5b 495 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, ONFICTL } },
c01f0f1a 496 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
c3721d5b
YS		 497 { INT2PRI32, 0, 32, 8, { DMINT22, 0, 0, 0 } },
498 { INT2PRI33, 0, 32, 8, { 0, 0, 0, DMINT16 } },
499 { INT2PRI34, 0, 32, 8, { 0, LPC6, DMINT21, DMINT18 } },
500 { INT2PRI35, 0, 32, 8, { DMINT23, TSIP, 0, DMINT19 } },
501 { INT2PRI36, 0, 32, 8, { DMINT20, GETHER1, PBIA, PBIB } },
502 { INT2PRI37, 0, 32, 8, { PBIC, DMAE2, DMAE3, SERMUX2 } },
503 { INT2PRI38, 0, 32, 8, { LPC7, 0, 0, 0 } },
504 { INT2PRI39, 0, 32, 8, { 0, 0, 0, WDT4B } },
505 { INT2PRI40, 0, 32, 8, { 0, 0, 0, DMINT17 } },
506 { INT2PRI41, 0, 32, 8, { DDRECC, 0, WDT6B, WDT5B } },
507 { INT2PRI42, 0, 32, 8, { 0, 0, 0, LPC8 } },
508 { INT2PRI43, 0, 32, 8, { 0, WDT7B, PCIE_BRIDGE, WDT8B } },
509 { INT2PRI44, 0, 32, 8, { WDT2B, GETHER2, 0, 0 } },
510 { INT2PRI45, 0, 32, 8, { 0, 0, LPC5, SERMUX3 } },
511 { INT2PRI46, 0, 32, 8, { WDT0B, WDT1B, WDT3B, GETHER0 } },
512 { INT2PRI47, 0, 32, 8, { DMINT12, DMINT13, DMINT14, DMINT15 } },
513};
514
515static struct intc_sense_reg sense_registers_irq8to15[] __initdata = {
516 { 0xffd100f8, 32, 2, /* ICR2 */ { IRQ15, IRQ14, IRQ13, IRQ12,
517 IRQ11, IRQ10, IRQ9, IRQ8 } },
c01f0f1a
YS		 518};
519
520static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
c3721d5b
YS		 521 mask_registers, prio_registers,
522 sense_registers_irq8to15);
c01f0f1a
YS		 523
524/* Support for external interrupt pins in IRQ mode */
525static struct intc_vect vectors_irq0123[] __initdata = {
526 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
527 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
528};
529
530static struct intc_vect vectors_irq4567[] __initdata = {
531 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
532 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
533};
534
535static struct intc_sense_reg sense_registers[] __initdata = {
536 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
537 IRQ4, IRQ5, IRQ6, IRQ7 } },
538};
539
540static struct intc_mask_reg ack_registers[] __initdata = {
541 { 0xffd00024, 0, 32, /* INTREQ */
542 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
543};
544
545static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
546 vectors_irq0123, NULL, mask_registers,
547 prio_registers, sense_registers, ack_registers);
548
549static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
550 vectors_irq4567, NULL, mask_registers,
551 prio_registers, sense_registers, ack_registers);
552
553/* External interrupt pins in IRL mode */
554static struct intc_vect vectors_irl0123[] __initdata = {
555 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
556 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
557 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
558 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
559 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
560 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
561 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
562 INTC_VECT(IRL0_HHHL, 0x3c0),
563};
564
565static struct intc_vect vectors_irl4567[] __initdata = {
566 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
567 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
568 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
569 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
570 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
571 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
572 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
573 INTC_VECT(IRL4_HHHL, 0xcc0),
574};
575
576static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
577 NULL, mask_registers, NULL, NULL);
578
579static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
580 NULL, mask_registers, NULL, NULL);
581
582#define INTC_ICR0 0xffd00000
583#define INTC_INTMSK0 0xffd00044
584#define INTC_INTMSK1 0xffd00048
585#define INTC_INTMSK2 0xffd40080
586#define INTC_INTMSKCLR1 0xffd00068
587#define INTC_INTMSKCLR2 0xffd40084
588
589void __init plat_irq_setup(void)
590{
591 /* disable IRQ3-0 + IRQ7-4 */
9d56dd3b 592 __raw_writel(0xff000000, INTC_INTMSK0);
c01f0f1a
YS		 593
594 /* disable IRL3-0 + IRL7-4 */
9d56dd3b
PM		 595 __raw_writel(0xc0000000, INTC_INTMSK1);
596 __raw_writel(0xfffefffe, INTC_INTMSK2);
c01f0f1a
YS		 597
598 /* select IRL mode for IRL3-0 + IRL7-4 */
9d56dd3b 599 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
c01f0f1a
YS		 600
601 /* disable holding function, ie enable "SH-4 Mode" */
9d56dd3b 602 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
c01f0f1a
YS		 603
604 register_intc_controller(&intc_desc);
605}
606
607void __init plat_irq_setup_pins(int mode)
608{
609 switch (mode) {
610 case IRQ_MODE_IRQ7654:
611 /* select IRQ mode for IRL7-4 */
9d56dd3b 612 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
c01f0f1a
YS		 613 register_intc_controller(&intc_desc_irq4567);
614 break;
615 case IRQ_MODE_IRQ3210:
616 /* select IRQ mode for IRL3-0 */
9d56dd3b 617 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
c01f0f1a
YS		 618 register_intc_controller(&intc_desc_irq0123);
619 break;
620 case IRQ_MODE_IRL7654:
621 /* enable IRL7-4 but don't provide any masking */
9d56dd3b
PM		 622 __raw_writel(0x40000000, INTC_INTMSKCLR1);
623 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
c01f0f1a
YS		 624 break;
625 case IRQ_MODE_IRL3210:
626 /* enable IRL0-3 but don't provide any masking */
9d56dd3b
PM		 627 __raw_writel(0x80000000, INTC_INTMSKCLR1);
628 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
c01f0f1a
YS		 629 break;
630 case IRQ_MODE_IRL7654_MASK:
631 /* enable IRL7-4 and mask using cpu intc controller */
9d56dd3b 632 __raw_writel(0x40000000, INTC_INTMSKCLR1);
c01f0f1a
YS		 633 register_intc_controller(&intc_desc_irl4567);
634 break;
635 case IRQ_MODE_IRL3210_MASK:
636 /* enable IRL0-3 and mask using cpu intc controller */
9d56dd3b 637 __raw_writel(0x80000000, INTC_INTMSKCLR1);
c01f0f1a
YS		 638 register_intc_controller(&intc_desc_irl0123);
639 break;
640 default:
641 BUG();
642 }
643}
644
645void __init plat_mem_setup(void)
646{
647}
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