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7d740a06 YS |
1 | /* |
2 | * SH7763 Setup | |
3 | * | |
4 | * Copyright (C) 2006 Paul Mundt | |
5 | * Copyright (C) 2007 Yoshihiro Shimoda | |
6 | * | |
7 | * This file is subject to the terms and conditions of the GNU General Public | |
8 | * License. See the file "COPYING" in the main directory of this archive | |
9 | * for more details. | |
10 | */ | |
11 | #include <linux/platform_device.h> | |
12 | #include <linux/init.h> | |
13 | #include <linux/serial.h> | |
14 | #include <linux/io.h> | |
96de1a8f | 15 | #include <linux/serial_sci.h> |
7d740a06 YS |
16 | |
17 | static struct resource rtc_resources[] = { | |
18 | [0] = { | |
19 | .start = 0xffe80000, | |
20 | .end = 0xffe80000 + 0x58 - 1, | |
21 | .flags = IORESOURCE_IO, | |
22 | }, | |
23 | [1] = { | |
24 | /* Period IRQ */ | |
25 | .start = 21, | |
26 | .flags = IORESOURCE_IRQ, | |
27 | }, | |
28 | [2] = { | |
29 | /* Carry IRQ */ | |
30 | .start = 22, | |
31 | .flags = IORESOURCE_IRQ, | |
32 | }, | |
33 | [3] = { | |
34 | /* Alarm IRQ */ | |
35 | .start = 20, | |
36 | .flags = IORESOURCE_IRQ, | |
37 | }, | |
38 | }; | |
39 | ||
40 | static struct platform_device rtc_device = { | |
41 | .name = "sh-rtc", | |
42 | .id = -1, | |
43 | .num_resources = ARRAY_SIZE(rtc_resources), | |
44 | .resource = rtc_resources, | |
45 | }; | |
46 | ||
47 | static struct plat_sci_port sci_platform_data[] = { | |
48 | { | |
49 | .mapbase = 0xffe00000, | |
50 | .flags = UPF_BOOT_AUTOCONF, | |
51 | .type = PORT_SCIF, | |
52 | .irqs = { 40, 41, 43, 42 }, | |
53 | }, { | |
54 | .mapbase = 0xffe08000, | |
55 | .flags = UPF_BOOT_AUTOCONF, | |
56 | .type = PORT_SCIF, | |
57 | .irqs = { 76, 77, 79, 78 }, | |
58 | }, { | |
59 | .flags = 0, | |
60 | } | |
61 | }; | |
62 | ||
63 | static struct platform_device sci_device = { | |
64 | .name = "sh-sci", | |
65 | .id = -1, | |
66 | .dev = { | |
67 | .platform_data = sci_platform_data, | |
68 | }, | |
69 | }; | |
70 | ||
71 | static struct resource usb_ohci_resources[] = { | |
72 | [0] = { | |
73 | .start = 0xffec8000, | |
74 | .end = 0xffec80ff, | |
75 | .flags = IORESOURCE_MEM, | |
76 | }, | |
77 | [1] = { | |
78 | .start = 83, | |
79 | .end = 83, | |
80 | .flags = IORESOURCE_IRQ, | |
81 | }, | |
82 | }; | |
83 | ||
84 | static u64 usb_ohci_dma_mask = 0xffffffffUL; | |
85 | static struct platform_device usb_ohci_device = { | |
86 | .name = "sh_ohci", | |
87 | .id = -1, | |
88 | .dev = { | |
89 | .dma_mask = &usb_ohci_dma_mask, | |
90 | .coherent_dma_mask = 0xffffffff, | |
91 | }, | |
92 | .num_resources = ARRAY_SIZE(usb_ohci_resources), | |
93 | .resource = usb_ohci_resources, | |
94 | }; | |
95 | ||
96 | static struct resource usbf_resources[] = { | |
97 | [0] = { | |
98 | .start = 0xffec0000, | |
99 | .end = 0xffec00ff, | |
100 | .flags = IORESOURCE_MEM, | |
101 | }, | |
102 | [1] = { | |
103 | .start = 84, | |
104 | .end = 84, | |
105 | .flags = IORESOURCE_IRQ, | |
106 | }, | |
107 | }; | |
108 | ||
109 | static struct platform_device usbf_device = { | |
110 | .name = "sh_udc", | |
111 | .id = -1, | |
112 | .dev = { | |
113 | .dma_mask = NULL, | |
114 | .coherent_dma_mask = 0xffffffff, | |
115 | }, | |
116 | .num_resources = ARRAY_SIZE(usbf_resources), | |
117 | .resource = usbf_resources, | |
118 | }; | |
119 | ||
120 | static struct platform_device *sh7763_devices[] __initdata = { | |
121 | &rtc_device, | |
122 | &sci_device, | |
123 | &usb_ohci_device, | |
124 | &usbf_device, | |
125 | }; | |
126 | ||
127 | static int __init sh7763_devices_setup(void) | |
128 | { | |
129 | return platform_add_devices(sh7763_devices, | |
130 | ARRAY_SIZE(sh7763_devices)); | |
131 | } | |
132 | __initcall(sh7763_devices_setup); | |
133 | ||
134 | enum { | |
135 | UNUSED = 0, | |
136 | ||
137 | /* interrupt sources */ | |
138 | ||
139 | IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, | |
140 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, | |
141 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, | |
142 | IRL_HHLL, IRL_HHLH, IRL_HHHL, | |
143 | ||
144 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, | |
145 | RTC_ATI, RTC_PRI, RTC_CUI, | |
146 | WDT, TMU0, TMU1, TMU2, TMU2_TICPI, | |
147 | HUDI, LCDC, | |
148 | DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, DMAC0_DMINT3, DMAC0_DMAE, | |
149 | SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI, | |
150 | DMAC0_DMINT4, DMAC0_DMINT5, | |
151 | IIC0, IIC1, | |
152 | CMT, | |
153 | GEINT0, GEINT1, GEINT2, | |
154 | HAC, | |
155 | PCISERR, PCIINTA, PCIINTB, PCIINTC, PCIINTD, | |
156 | PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0, | |
157 | STIF0, STIF1, | |
158 | SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI, | |
159 | SIOF0, SIOF1, SIOF2, | |
160 | USBH, USBFI0, USBFI1, | |
161 | TPU, PCC, | |
162 | MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY, | |
163 | SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND, | |
164 | TMU3, TMU4, TMU5, ADC, SSI0, SSI1, SSI2, SSI3, | |
165 | SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI, | |
166 | GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3, | |
167 | ||
168 | /* interrupt groups */ | |
169 | ||
170 | TMU012, TMU345, RTC, DMAC, SCIF0, GETHER, PCIC5, | |
171 | SCIF1, USBF, MMCIF, SIM, SCIF2, GPIO, | |
172 | }; | |
173 | ||
174 | static struct intc_vect vectors[] __initdata = { | |
175 | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), | |
176 | INTC_VECT(RTC_CUI, 0x4c0), | |
177 | INTC_VECT(WDT, 0x560), INTC_VECT(TMU0, 0x580), | |
178 | INTC_VECT(TMU1, 0x5a0), INTC_VECT(TMU2, 0x5c0), | |
179 | INTC_VECT(TMU2_TICPI, 0x5e0), INTC_VECT(HUDI, 0x600), | |
180 | INTC_VECT(LCDC, 0x620), | |
181 | INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), | |
182 | INTC_VECT(DMAC0_DMINT2, 0x680), INTC_VECT(DMAC0_DMINT3, 0x6a0), | |
183 | INTC_VECT(DMAC0_DMAE, 0x6c0), | |
184 | INTC_VECT(SCIF0_ERI, 0x700), INTC_VECT(SCIF0_RXI, 0x720), | |
185 | INTC_VECT(SCIF0_BRI, 0x740), INTC_VECT(SCIF0_TXI, 0x760), | |
186 | INTC_VECT(DMAC0_DMINT4, 0x780), INTC_VECT(DMAC0_DMINT5, 0x7a0), | |
187 | INTC_VECT(IIC0, 0x8A0), INTC_VECT(IIC1, 0x8C0), | |
188 | INTC_VECT(CMT, 0x900), INTC_VECT(GEINT0, 0x920), | |
189 | INTC_VECT(GEINT1, 0x940), INTC_VECT(GEINT2, 0x960), | |
190 | INTC_VECT(HAC, 0x980), | |
191 | INTC_VECT(PCISERR, 0xa00), INTC_VECT(PCIINTA, 0xa20), | |
192 | INTC_VECT(PCIINTB, 0xa40), INTC_VECT(PCIINTC, 0xa60), | |
193 | INTC_VECT(PCIINTD, 0xa80), INTC_VECT(PCIERR, 0xaa0), | |
194 | INTC_VECT(PCIPWD3, 0xac0), INTC_VECT(PCIPWD2, 0xae0), | |
195 | INTC_VECT(PCIPWD1, 0xb00), INTC_VECT(PCIPWD0, 0xb20), | |
196 | INTC_VECT(STIF0, 0xb40), INTC_VECT(STIF1, 0xb60), | |
197 | INTC_VECT(SCIF1_ERI, 0xb80), INTC_VECT(SCIF1_RXI, 0xba0), | |
198 | INTC_VECT(SCIF1_BRI, 0xbc0), INTC_VECT(SCIF1_TXI, 0xbe0), | |
199 | INTC_VECT(SIOF0, 0xc00), INTC_VECT(SIOF1, 0xc20), | |
200 | INTC_VECT(USBH, 0xc60), INTC_VECT(USBFI0, 0xc80), | |
201 | INTC_VECT(USBFI1, 0xca0), | |
202 | INTC_VECT(TPU, 0xcc0), INTC_VECT(PCC, 0xce0), | |
203 | INTC_VECT(MMCIF_FSTAT, 0xd00), INTC_VECT(MMCIF_TRAN, 0xd20), | |
204 | INTC_VECT(MMCIF_ERR, 0xd40), INTC_VECT(MMCIF_FRDY, 0xd60), | |
205 | INTC_VECT(SIM_ERI, 0xd80), INTC_VECT(SIM_RXI, 0xda0), | |
206 | INTC_VECT(SIM_TXI, 0xdc0), INTC_VECT(SIM_TEND, 0xde0), | |
207 | INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20), | |
208 | INTC_VECT(TMU5, 0xe40), INTC_VECT(ADC, 0xe60), | |
209 | INTC_VECT(SSI0, 0xe80), INTC_VECT(SSI1, 0xea0), | |
210 | INTC_VECT(SSI2, 0xec0), INTC_VECT(SSI3, 0xee0), | |
211 | INTC_VECT(SCIF1_ERI, 0xf00), INTC_VECT(SCIF1_RXI, 0xf20), | |
212 | INTC_VECT(SCIF1_BRI, 0xf40), INTC_VECT(SCIF1_TXI, 0xf60), | |
213 | INTC_VECT(GPIO_CH0, 0xf80), INTC_VECT(GPIO_CH1, 0xfa0), | |
214 | INTC_VECT(GPIO_CH2, 0xfc0), INTC_VECT(GPIO_CH3, 0xfe0), | |
215 | }; | |
216 | ||
217 | static struct intc_group groups[] __initdata = { | |
218 | INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI), | |
219 | INTC_GROUP(TMU345, TMU3, TMU4, TMU5), | |
220 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | |
221 | INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, | |
222 | DMAC0_DMINT3, DMAC0_DMINT4, DMAC0_DMINT5, DMAC0_DMAE), | |
223 | INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI), | |
224 | INTC_GROUP(GETHER, GEINT0, GEINT1, GEINT2), | |
225 | INTC_GROUP(PCIC5, PCIERR, PCIPWD3, PCIPWD2, PCIPWD1, PCIPWD0), | |
226 | INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI), | |
227 | INTC_GROUP(USBF, USBFI0, USBFI1), | |
228 | INTC_GROUP(MMCIF, MMCIF_FSTAT, MMCIF_TRAN, MMCIF_ERR, MMCIF_FRDY), | |
229 | INTC_GROUP(SIM, SIM_ERI, SIM_RXI, SIM_TXI, SIM_TEND), | |
230 | INTC_GROUP(SCIF2, SCIF2_ERI, SCIF2_RXI, SCIF2_BRI, SCIF2_TXI), | |
231 | INTC_GROUP(GPIO, GPIO_CH0, GPIO_CH1, GPIO_CH2, GPIO_CH3), | |
232 | }; | |
233 | ||
7d740a06 YS |
234 | static struct intc_mask_reg mask_registers[] __initdata = { |
235 | { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */ | |
236 | { 0, 0, 0, 0, 0, 0, GPIO, 0, | |
237 | SSI0, MMCIF, 0, SIOF0, PCIC5, PCIINTD, PCIINTC, PCIINTB, | |
238 | PCIINTA, PCISERR, HAC, CMT, 0, 0, 0, DMAC, | |
239 | HUDI, 0, WDT, SCIF1, SCIF0, RTC, TMU345, TMU012 } }, | |
240 | { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */ | |
241 | { 0, 0, 0, 0, 0, 0, SCIF2, USBF, | |
242 | 0, 0, STIF1, STIF0, 0, 0, USBH, GETHER, | |
243 | PCC, 0, 0, ADC, TPU, SIM, SIOF2, SIOF1, | |
244 | LCDC, 0, IIC1, IIC0, SSI3, SSI2, SSI1, 0 } }, | |
245 | }; | |
246 | ||
247 | static struct intc_prio_reg prio_registers[] __initdata = { | |
248 | { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0, TMU1, | |
249 | TMU2, TMU2_TICPI } }, | |
250 | { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3, TMU4, TMU5, RTC } }, | |
251 | { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0, SCIF1, WDT } }, | |
252 | { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI, DMAC, ADC } }, | |
253 | { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT, HAC, | |
254 | PCISERR, PCIINTA } }, | |
255 | { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB, PCIINTC, | |
256 | PCIINTD, PCIC5 } }, | |
257 | { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF0, USBF, MMCIF, SSI0 } }, | |
258 | { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { SCIF2, GPIO } }, | |
259 | { 0xffd400a0, 0, 32, 8, /* INT2PRI8 */ { SSI3, SSI2, SSI1, 0 } }, | |
260 | { 0xffd400a4, 0, 32, 8, /* INT2PRI9 */ { LCDC, 0, IIC1, IIC0 } }, | |
261 | { 0xffd400a8, 0, 32, 8, /* INT2PRI10 */ { TPU, SIM, SIOF2, SIOF1 } }, | |
262 | { 0xffd400ac, 0, 32, 8, /* INT2PRI11 */ { PCC } }, | |
263 | { 0xffd400b0, 0, 32, 8, /* INT2PRI12 */ { 0, 0, USBH, GETHER } }, | |
264 | { 0xffd400b4, 0, 32, 8, /* INT2PRI13 */ { 0, 0, STIF1, STIF0 } }, | |
265 | }; | |
266 | ||
47aa8f49 | 267 | static DECLARE_INTC_DESC(intc_desc, "sh7763", vectors, groups, |
7d740a06 YS |
268 | mask_registers, prio_registers, NULL); |
269 | ||
270 | /* Support for external interrupt pins in IRQ mode */ | |
7d740a06 YS |
271 | static struct intc_vect irq_vectors[] __initdata = { |
272 | INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), | |
273 | INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), | |
274 | INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), | |
275 | INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200), | |
276 | }; | |
277 | ||
278 | static struct intc_mask_reg irq_mask_registers[] __initdata = { | |
279 | { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ | |
280 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
281 | }; | |
282 | ||
283 | static struct intc_prio_reg irq_prio_registers[] __initdata = { | |
284 | { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, | |
285 | IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
286 | }; | |
287 | ||
288 | static struct intc_sense_reg irq_sense_registers[] __initdata = { | |
289 | { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, | |
290 | IRQ4, IRQ5, IRQ6, IRQ7 } }, | |
291 | }; | |
292 | ||
293 | static DECLARE_INTC_DESC(intc_irq_desc, "sh7763-irq", irq_vectors, | |
5bde47bc NI |
294 | NULL, irq_mask_registers, irq_prio_registers, |
295 | irq_sense_registers); | |
296 | ||
7d740a06 YS |
297 | |
298 | /* External interrupt pins in IRL mode */ | |
7d740a06 YS |
299 | static struct intc_vect irl_vectors[] __initdata = { |
300 | INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), | |
301 | INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), | |
302 | INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), | |
303 | INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), | |
304 | INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), | |
305 | INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), | |
306 | INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), | |
307 | INTC_VECT(IRL_HHHL, 0x3c0), | |
308 | }; | |
309 | ||
310 | static struct intc_mask_reg irl3210_mask_registers[] __initdata = { | |
311 | { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ | |
312 | { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, | |
313 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, | |
314 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, | |
315 | IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, | |
316 | }; | |
317 | ||
318 | static struct intc_mask_reg irl7654_mask_registers[] __initdata = { | |
319 | { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ | |
320 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
321 | IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, | |
322 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, | |
323 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, | |
324 | IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, | |
325 | }; | |
326 | ||
327 | static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7763-irl7654", irl_vectors, | |
5bde47bc | 328 | NULL, irl7654_mask_registers, NULL, NULL); |
7d740a06 YS |
329 | |
330 | static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors, | |
5bde47bc | 331 | NULL, irl3210_mask_registers, NULL, NULL); |
7d740a06 YS |
332 | |
333 | #define INTC_ICR0 0xffd00000 | |
334 | #define INTC_INTMSK0 0xffd00044 | |
335 | #define INTC_INTMSK1 0xffd00048 | |
336 | #define INTC_INTMSK2 0xffd40080 | |
337 | #define INTC_INTMSKCLR1 0xffd00068 | |
338 | #define INTC_INTMSKCLR2 0xffd40084 | |
339 | ||
340 | void __init plat_irq_setup(void) | |
341 | { | |
342 | /* disable IRQ7-0 */ | |
343 | ctrl_outl(0xff000000, INTC_INTMSK0); | |
344 | ||
345 | /* disable IRL3-0 + IRL7-4 */ | |
346 | ctrl_outl(0xc0000000, INTC_INTMSK1); | |
347 | ctrl_outl(0xfffefffe, INTC_INTMSK2); | |
348 | ||
349 | register_intc_controller(&intc_desc); | |
350 | } | |
351 | ||
352 | void __init plat_irq_setup_pins(int mode) | |
353 | { | |
354 | switch (mode) { | |
355 | case IRQ_MODE_IRQ: | |
356 | /* select IRQ mode for IRL3-0 + IRL7-4 */ | |
357 | ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); | |
358 | register_intc_controller(&intc_irq_desc); | |
359 | break; | |
360 | case IRQ_MODE_IRL7654: | |
361 | /* enable IRL7-4 but don't provide any masking */ | |
362 | ctrl_outl(0x40000000, INTC_INTMSKCLR1); | |
363 | ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); | |
364 | break; | |
365 | case IRQ_MODE_IRL3210: | |
366 | /* enable IRL0-3 but don't provide any masking */ | |
367 | ctrl_outl(0x80000000, INTC_INTMSKCLR1); | |
368 | ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); | |
369 | break; | |
370 | case IRQ_MODE_IRL7654_MASK: | |
371 | /* enable IRL7-4 and mask using cpu intc controller */ | |
372 | ctrl_outl(0x40000000, INTC_INTMSKCLR1); | |
373 | register_intc_controller(&intc_irl7654_desc); | |
374 | break; | |
375 | case IRQ_MODE_IRL3210_MASK: | |
376 | /* enable IRL0-3 and mask using cpu intc controller */ | |
377 | ctrl_outl(0x80000000, INTC_INTMSKCLR1); | |
378 | register_intc_controller(&intc_irl3210_desc); | |
379 | break; | |
380 | default: | |
381 | BUG(); | |
382 | } | |
383 | } |