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7dec62e9 PM |
1 | /* |
2 | * SH7770 Setup | |
3 | * | |
2163b4cb | 4 | * Copyright (C) 2006 - 2008 Paul Mundt |
7dec62e9 PM |
5 | * |
6 | * This file is subject to the terms and conditions of the GNU General Public | |
7 | * License. See the file "COPYING" in the main directory of this archive | |
8 | * for more details. | |
9 | */ | |
10 | #include <linux/platform_device.h> | |
11 | #include <linux/init.h> | |
12 | #include <linux/serial.h> | |
96de1a8f | 13 | #include <linux/serial_sci.h> |
f251935e | 14 | #include <linux/sh_timer.h> |
f454314c | 15 | #include <linux/sh_intc.h> |
9304d0cc | 16 | #include <linux/io.h> |
7dec62e9 | 17 | |
a9571d7b MD |
18 | static struct plat_sci_port scif0_platform_data = { |
19 | .mapbase = 0xff923000, | |
20 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
21 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
22 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 23 | .type = PORT_SCIF, |
f454314c | 24 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9a0)), |
a9571d7b MD |
25 | }; |
26 | ||
27 | static struct platform_device scif0_device = { | |
28 | .name = "sh-sci", | |
29 | .id = 0, | |
30 | .dev = { | |
31 | .platform_data = &scif0_platform_data, | |
32 | }, | |
33 | }; | |
34 | ||
35 | static struct plat_sci_port scif1_platform_data = { | |
36 | .mapbase = 0xff924000, | |
37 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
38 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
39 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 40 | .type = PORT_SCIF, |
f454314c | 41 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9c0)), |
a9571d7b MD |
42 | }; |
43 | ||
44 | static struct platform_device scif1_device = { | |
45 | .name = "sh-sci", | |
46 | .id = 1, | |
47 | .dev = { | |
48 | .platform_data = &scif1_platform_data, | |
49 | }, | |
50 | }; | |
51 | ||
52 | static struct plat_sci_port scif2_platform_data = { | |
53 | .mapbase = 0xff925000, | |
54 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
55 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
56 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 57 | .type = PORT_SCIF, |
f454314c | 58 | .irqs = SCIx_IRQ_MUXED(evt2irq(0x9e0)), |
a9571d7b MD |
59 | }; |
60 | ||
61 | static struct platform_device scif2_device = { | |
62 | .name = "sh-sci", | |
63 | .id = 2, | |
64 | .dev = { | |
65 | .platform_data = &scif2_platform_data, | |
66 | }, | |
67 | }; | |
68 | ||
69 | static struct plat_sci_port scif3_platform_data = { | |
70 | .mapbase = 0xff926000, | |
71 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
72 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
73 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 74 | .type = PORT_SCIF, |
f454314c | 75 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa00)), |
a9571d7b MD |
76 | }; |
77 | ||
78 | static struct platform_device scif3_device = { | |
79 | .name = "sh-sci", | |
80 | .id = 3, | |
81 | .dev = { | |
82 | .platform_data = &scif3_platform_data, | |
83 | }, | |
84 | }; | |
85 | ||
86 | static struct plat_sci_port scif4_platform_data = { | |
87 | .mapbase = 0xff927000, | |
88 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
89 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
90 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 91 | .type = PORT_SCIF, |
f454314c | 92 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa20)), |
a9571d7b MD |
93 | }; |
94 | ||
95 | static struct platform_device scif4_device = { | |
96 | .name = "sh-sci", | |
97 | .id = 4, | |
98 | .dev = { | |
99 | .platform_data = &scif4_platform_data, | |
100 | }, | |
101 | }; | |
102 | ||
103 | static struct plat_sci_port scif5_platform_data = { | |
104 | .mapbase = 0xff928000, | |
105 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
106 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
107 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 108 | .type = PORT_SCIF, |
f454314c | 109 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa40)), |
a9571d7b MD |
110 | }; |
111 | ||
112 | static struct platform_device scif5_device = { | |
113 | .name = "sh-sci", | |
114 | .id = 5, | |
115 | .dev = { | |
116 | .platform_data = &scif5_platform_data, | |
117 | }, | |
118 | }; | |
119 | ||
120 | static struct plat_sci_port scif6_platform_data = { | |
121 | .mapbase = 0xff929000, | |
122 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
123 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
124 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 125 | .type = PORT_SCIF, |
f454314c | 126 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa60)), |
a9571d7b MD |
127 | }; |
128 | ||
129 | static struct platform_device scif6_device = { | |
130 | .name = "sh-sci", | |
131 | .id = 6, | |
132 | .dev = { | |
133 | .platform_data = &scif6_platform_data, | |
134 | }, | |
135 | }; | |
136 | ||
137 | static struct plat_sci_port scif7_platform_data = { | |
138 | .mapbase = 0xff92a000, | |
139 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
140 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
141 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 142 | .type = PORT_SCIF, |
f454314c | 143 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xa80)), |
a9571d7b MD |
144 | }; |
145 | ||
146 | static struct platform_device scif7_device = { | |
147 | .name = "sh-sci", | |
148 | .id = 7, | |
149 | .dev = { | |
150 | .platform_data = &scif7_platform_data, | |
151 | }, | |
152 | }; | |
153 | ||
154 | static struct plat_sci_port scif8_platform_data = { | |
155 | .mapbase = 0xff92b000, | |
156 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
157 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
158 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 159 | .type = PORT_SCIF, |
f454314c | 160 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xaa0)), |
a9571d7b MD |
161 | }; |
162 | ||
163 | static struct platform_device scif8_device = { | |
164 | .name = "sh-sci", | |
165 | .id = 8, | |
166 | .dev = { | |
167 | .platform_data = &scif8_platform_data, | |
168 | }, | |
169 | }; | |
170 | ||
171 | static struct plat_sci_port scif9_platform_data = { | |
172 | .mapbase = 0xff92c000, | |
173 | .flags = UPF_BOOT_AUTOCONF, | |
f43dc23d PM |
174 | .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE, |
175 | .scbrr_algo_id = SCBRR_ALGO_2, | |
a9571d7b | 176 | .type = PORT_SCIF, |
f454314c | 177 | .irqs = SCIx_IRQ_MUXED(evt2irq(0xac0)), |
7dec62e9 PM |
178 | }; |
179 | ||
a9571d7b | 180 | static struct platform_device scif9_device = { |
7dec62e9 | 181 | .name = "sh-sci", |
a9571d7b | 182 | .id = 9, |
7dec62e9 | 183 | .dev = { |
a9571d7b | 184 | .platform_data = &scif9_platform_data, |
7dec62e9 PM |
185 | }, |
186 | }; | |
187 | ||
f251935e | 188 | static struct sh_timer_config tmu0_platform_data = { |
f251935e MD |
189 | .channel_offset = 0x04, |
190 | .timer_bit = 0, | |
f251935e MD |
191 | .clockevent_rating = 200, |
192 | }; | |
193 | ||
194 | static struct resource tmu0_resources[] = { | |
195 | [0] = { | |
f251935e MD |
196 | .start = 0xffd80008, |
197 | .end = 0xffd80013, | |
198 | .flags = IORESOURCE_MEM, | |
199 | }, | |
200 | [1] = { | |
f454314c | 201 | .start = evt2irq(0x400), |
f251935e MD |
202 | .flags = IORESOURCE_IRQ, |
203 | }, | |
204 | }; | |
205 | ||
206 | static struct platform_device tmu0_device = { | |
207 | .name = "sh_tmu", | |
208 | .id = 0, | |
209 | .dev = { | |
210 | .platform_data = &tmu0_platform_data, | |
211 | }, | |
212 | .resource = tmu0_resources, | |
213 | .num_resources = ARRAY_SIZE(tmu0_resources), | |
214 | }; | |
215 | ||
216 | static struct sh_timer_config tmu1_platform_data = { | |
f251935e MD |
217 | .channel_offset = 0x10, |
218 | .timer_bit = 1, | |
f251935e MD |
219 | .clocksource_rating = 200, |
220 | }; | |
221 | ||
222 | static struct resource tmu1_resources[] = { | |
223 | [0] = { | |
f251935e MD |
224 | .start = 0xffd80014, |
225 | .end = 0xffd8001f, | |
226 | .flags = IORESOURCE_MEM, | |
227 | }, | |
228 | [1] = { | |
f454314c | 229 | .start = evt2irq(0x420), |
f251935e MD |
230 | .flags = IORESOURCE_IRQ, |
231 | }, | |
232 | }; | |
233 | ||
234 | static struct platform_device tmu1_device = { | |
235 | .name = "sh_tmu", | |
236 | .id = 1, | |
237 | .dev = { | |
238 | .platform_data = &tmu1_platform_data, | |
239 | }, | |
240 | .resource = tmu1_resources, | |
241 | .num_resources = ARRAY_SIZE(tmu1_resources), | |
242 | }; | |
243 | ||
244 | static struct sh_timer_config tmu2_platform_data = { | |
f251935e MD |
245 | .channel_offset = 0x1c, |
246 | .timer_bit = 2, | |
f251935e MD |
247 | }; |
248 | ||
249 | static struct resource tmu2_resources[] = { | |
250 | [0] = { | |
f251935e MD |
251 | .start = 0xffd80020, |
252 | .end = 0xffd8002f, | |
253 | .flags = IORESOURCE_MEM, | |
254 | }, | |
255 | [1] = { | |
f454314c | 256 | .start = evt2irq(0x440), |
f251935e MD |
257 | .flags = IORESOURCE_IRQ, |
258 | }, | |
259 | }; | |
260 | ||
261 | static struct platform_device tmu2_device = { | |
262 | .name = "sh_tmu", | |
263 | .id = 2, | |
264 | .dev = { | |
265 | .platform_data = &tmu2_platform_data, | |
266 | }, | |
267 | .resource = tmu2_resources, | |
268 | .num_resources = ARRAY_SIZE(tmu2_resources), | |
269 | }; | |
270 | ||
271 | static struct sh_timer_config tmu3_platform_data = { | |
f251935e MD |
272 | .channel_offset = 0x04, |
273 | .timer_bit = 0, | |
f251935e MD |
274 | }; |
275 | ||
276 | static struct resource tmu3_resources[] = { | |
277 | [0] = { | |
f251935e MD |
278 | .start = 0xffd81008, |
279 | .end = 0xffd81013, | |
280 | .flags = IORESOURCE_MEM, | |
281 | }, | |
282 | [1] = { | |
f454314c | 283 | .start = evt2irq(0x460), |
f251935e MD |
284 | .flags = IORESOURCE_IRQ, |
285 | }, | |
286 | }; | |
287 | ||
288 | static struct platform_device tmu3_device = { | |
289 | .name = "sh_tmu", | |
290 | .id = 3, | |
291 | .dev = { | |
292 | .platform_data = &tmu3_platform_data, | |
293 | }, | |
294 | .resource = tmu3_resources, | |
295 | .num_resources = ARRAY_SIZE(tmu3_resources), | |
296 | }; | |
297 | ||
298 | static struct sh_timer_config tmu4_platform_data = { | |
f251935e MD |
299 | .channel_offset = 0x10, |
300 | .timer_bit = 1, | |
f251935e MD |
301 | }; |
302 | ||
303 | static struct resource tmu4_resources[] = { | |
304 | [0] = { | |
f251935e MD |
305 | .start = 0xffd81014, |
306 | .end = 0xffd8101f, | |
307 | .flags = IORESOURCE_MEM, | |
308 | }, | |
309 | [1] = { | |
f454314c | 310 | .start = evt2irq(0x480), |
f251935e MD |
311 | .flags = IORESOURCE_IRQ, |
312 | }, | |
313 | }; | |
314 | ||
315 | static struct platform_device tmu4_device = { | |
316 | .name = "sh_tmu", | |
317 | .id = 4, | |
318 | .dev = { | |
319 | .platform_data = &tmu4_platform_data, | |
320 | }, | |
321 | .resource = tmu4_resources, | |
322 | .num_resources = ARRAY_SIZE(tmu4_resources), | |
323 | }; | |
324 | ||
325 | static struct sh_timer_config tmu5_platform_data = { | |
f251935e MD |
326 | .channel_offset = 0x1c, |
327 | .timer_bit = 2, | |
f251935e MD |
328 | }; |
329 | ||
330 | static struct resource tmu5_resources[] = { | |
331 | [0] = { | |
f251935e MD |
332 | .start = 0xffd81020, |
333 | .end = 0xffd8102f, | |
334 | .flags = IORESOURCE_MEM, | |
335 | }, | |
336 | [1] = { | |
f454314c | 337 | .start = evt2irq(0x4a0), |
f251935e MD |
338 | .flags = IORESOURCE_IRQ, |
339 | }, | |
340 | }; | |
341 | ||
342 | static struct platform_device tmu5_device = { | |
343 | .name = "sh_tmu", | |
344 | .id = 5, | |
345 | .dev = { | |
346 | .platform_data = &tmu5_platform_data, | |
347 | }, | |
348 | .resource = tmu5_resources, | |
349 | .num_resources = ARRAY_SIZE(tmu5_resources), | |
350 | }; | |
351 | ||
352 | static struct sh_timer_config tmu6_platform_data = { | |
f251935e MD |
353 | .channel_offset = 0x04, |
354 | .timer_bit = 0, | |
f251935e MD |
355 | }; |
356 | ||
357 | static struct resource tmu6_resources[] = { | |
358 | [0] = { | |
f251935e MD |
359 | .start = 0xffd82008, |
360 | .end = 0xffd82013, | |
361 | .flags = IORESOURCE_MEM, | |
362 | }, | |
363 | [1] = { | |
f454314c | 364 | .start = evt2irq(0x4c0), |
f251935e MD |
365 | .flags = IORESOURCE_IRQ, |
366 | }, | |
367 | }; | |
368 | ||
369 | static struct platform_device tmu6_device = { | |
370 | .name = "sh_tmu", | |
371 | .id = 6, | |
372 | .dev = { | |
373 | .platform_data = &tmu6_platform_data, | |
374 | }, | |
375 | .resource = tmu6_resources, | |
376 | .num_resources = ARRAY_SIZE(tmu6_resources), | |
377 | }; | |
378 | ||
379 | static struct sh_timer_config tmu7_platform_data = { | |
f251935e MD |
380 | .channel_offset = 0x10, |
381 | .timer_bit = 1, | |
f251935e MD |
382 | }; |
383 | ||
384 | static struct resource tmu7_resources[] = { | |
385 | [0] = { | |
f251935e MD |
386 | .start = 0xffd82014, |
387 | .end = 0xffd8201f, | |
388 | .flags = IORESOURCE_MEM, | |
389 | }, | |
390 | [1] = { | |
f454314c | 391 | .start = evt2irq(0x4e0), |
f251935e MD |
392 | .flags = IORESOURCE_IRQ, |
393 | }, | |
394 | }; | |
395 | ||
396 | static struct platform_device tmu7_device = { | |
397 | .name = "sh_tmu", | |
398 | .id = 7, | |
399 | .dev = { | |
400 | .platform_data = &tmu7_platform_data, | |
401 | }, | |
402 | .resource = tmu7_resources, | |
403 | .num_resources = ARRAY_SIZE(tmu7_resources), | |
404 | }; | |
405 | ||
406 | static struct sh_timer_config tmu8_platform_data = { | |
f251935e MD |
407 | .channel_offset = 0x1c, |
408 | .timer_bit = 2, | |
f251935e MD |
409 | }; |
410 | ||
411 | static struct resource tmu8_resources[] = { | |
412 | [0] = { | |
f251935e MD |
413 | .start = 0xffd82020, |
414 | .end = 0xffd8202b, | |
415 | .flags = IORESOURCE_MEM, | |
416 | }, | |
417 | [1] = { | |
f454314c | 418 | .start = evt2irq(0x500), |
f251935e MD |
419 | .flags = IORESOURCE_IRQ, |
420 | }, | |
421 | }; | |
422 | ||
423 | static struct platform_device tmu8_device = { | |
424 | .name = "sh_tmu", | |
425 | .id = 8, | |
426 | .dev = { | |
427 | .platform_data = &tmu8_platform_data, | |
428 | }, | |
429 | .resource = tmu8_resources, | |
430 | .num_resources = ARRAY_SIZE(tmu8_resources), | |
431 | }; | |
432 | ||
7dec62e9 | 433 | static struct platform_device *sh7770_devices[] __initdata = { |
a9571d7b MD |
434 | &scif0_device, |
435 | &scif1_device, | |
436 | &scif2_device, | |
437 | &scif3_device, | |
438 | &scif4_device, | |
439 | &scif5_device, | |
440 | &scif6_device, | |
441 | &scif7_device, | |
442 | &scif8_device, | |
443 | &scif9_device, | |
f251935e MD |
444 | &tmu0_device, |
445 | &tmu1_device, | |
446 | &tmu2_device, | |
447 | &tmu3_device, | |
448 | &tmu4_device, | |
449 | &tmu5_device, | |
450 | &tmu6_device, | |
451 | &tmu7_device, | |
452 | &tmu8_device, | |
7dec62e9 PM |
453 | }; |
454 | ||
455 | static int __init sh7770_devices_setup(void) | |
456 | { | |
457 | return platform_add_devices(sh7770_devices, | |
458 | ARRAY_SIZE(sh7770_devices)); | |
459 | } | |
ba9a6337 | 460 | arch_initcall(sh7770_devices_setup); |
35f3abe9 | 461 | |
f251935e | 462 | static struct platform_device *sh7770_early_devices[] __initdata = { |
a9571d7b MD |
463 | &scif0_device, |
464 | &scif1_device, | |
465 | &scif2_device, | |
466 | &scif3_device, | |
467 | &scif4_device, | |
468 | &scif5_device, | |
469 | &scif6_device, | |
470 | &scif7_device, | |
471 | &scif8_device, | |
472 | &scif9_device, | |
f251935e MD |
473 | &tmu0_device, |
474 | &tmu1_device, | |
475 | &tmu2_device, | |
476 | &tmu3_device, | |
477 | &tmu4_device, | |
478 | &tmu5_device, | |
479 | &tmu6_device, | |
480 | &tmu7_device, | |
481 | &tmu8_device, | |
482 | }; | |
483 | ||
484 | void __init plat_early_device_setup(void) | |
485 | { | |
486 | early_platform_add_devices(sh7770_early_devices, | |
487 | ARRAY_SIZE(sh7770_early_devices)); | |
488 | } | |
489 | ||
9304d0cc MD |
490 | enum { |
491 | UNUSED = 0, | |
492 | ||
493 | /* interrupt sources */ | |
494 | IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, | |
495 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, | |
496 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, | |
497 | IRL_HHLL, IRL_HHLH, IRL_HHHL, | |
498 | ||
499 | IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, | |
500 | ||
501 | GPIO, | |
502 | TMU0, TMU1, TMU2, TMU2_TICPI, | |
503 | TMU3, TMU4, TMU5, TMU5_TICPI, | |
504 | TMU6, TMU7, TMU8, | |
505 | HAC, IPI, SPDIF, HUDI, I2C, | |
506 | DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2, | |
507 | I2S0, I2S1, I2S2, I2S3, | |
508 | SRC_RX, SRC_TX, SRC_SPDIF, | |
509 | DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D, | |
510 | GFX3D_MBX, GFX3D_DMAC, | |
511 | EXBUS_ATA, | |
512 | SPI0, SPI1, | |
513 | SCIF089, SCIF1234, SCIF567, | |
514 | ADC, | |
515 | BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, | |
516 | BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, | |
517 | BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31, | |
518 | ||
519 | /* interrupt groups */ | |
520 | TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC, | |
521 | }; | |
522 | ||
523 | static struct intc_vect vectors[] __initdata = { | |
524 | INTC_VECT(GPIO, 0x3e0), | |
525 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | |
526 | INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460), | |
527 | INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0), | |
528 | INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0), | |
529 | INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520), | |
530 | INTC_VECT(TMU8, 0x540), | |
531 | INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0), | |
532 | INTC_VECT(SPDIF, 0x5e0), | |
533 | INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620), | |
534 | INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660), | |
535 | INTC_VECT(DMAC0_DMINT2, 0x680), | |
536 | INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0), | |
537 | INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700), | |
538 | INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740), | |
539 | INTC_VECT(SRC_SPDIF, 0x760), | |
540 | INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0), | |
541 | INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0), | |
542 | INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860), | |
543 | INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0), | |
544 | INTC_VECT(GFX2D, 0x8c0), | |
545 | INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920), | |
546 | INTC_VECT(EXBUS_ATA, 0x940), | |
547 | INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980), | |
548 | INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0), | |
549 | INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00), | |
550 | INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40), | |
551 | INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80), | |
552 | INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0), | |
553 | INTC_VECT(ADC, 0xb20), | |
554 | INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0), | |
555 | INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00), | |
556 | INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40), | |
557 | INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80), | |
558 | INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0), | |
559 | INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00), | |
560 | INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40), | |
561 | INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80), | |
562 | INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0), | |
563 | INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00), | |
564 | INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40), | |
565 | INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80), | |
566 | INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0), | |
567 | INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00), | |
568 | INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40), | |
569 | INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80), | |
570 | }; | |
571 | ||
572 | static struct intc_group groups[] __initdata = { | |
573 | INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5, | |
574 | TMU5_TICPI, TMU6, TMU7, TMU8), | |
575 | INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2), | |
576 | INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3), | |
577 | INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF), | |
578 | INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC), | |
579 | INTC_GROUP(SPI, SPI0, SPI1), | |
580 | INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567), | |
581 | INTC_GROUP(BBDMAC, | |
582 | BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, | |
583 | BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, | |
584 | BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31), | |
585 | }; | |
586 | ||
587 | static struct intc_mask_reg mask_registers[] __initdata = { | |
588 | { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */ | |
589 | { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D, | |
590 | GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S, | |
591 | DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } }, | |
592 | }; | |
593 | ||
594 | static struct intc_prio_reg prio_registers[] __initdata = { | |
595 | { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } }, | |
596 | { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } }, | |
597 | { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } }, | |
598 | { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } }, | |
599 | { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } }, | |
600 | { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } }, | |
601 | { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } }, | |
602 | { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } }, | |
603 | { 0xffe00020, 0, 32, 8, /* INT2PRI8 */ | |
604 | { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } }, | |
605 | { 0xffe00024, 0, 32, 8, /* INT2PRI9 */ | |
606 | { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } }, | |
607 | { 0xffe00028, 0, 32, 8, /* INT2PRI10 */ | |
608 | { BBDMAC_29, BBDMAC_30, BBDMAC_31 } }, | |
609 | { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */ | |
610 | { TMU1, TMU2, TMU2_TICPI, TMU3 } }, | |
611 | { 0xffe00030, 0, 32, 8, /* INT2PRI12 */ | |
612 | { TMU4, TMU5, TMU5_TICPI, TMU6 } }, | |
613 | { 0xffe00034, 0, 32, 8, /* INT2PRI13 */ | |
614 | { TMU7, TMU8 } }, | |
615 | }; | |
616 | ||
617 | static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups, | |
618 | mask_registers, prio_registers, NULL); | |
619 | ||
620 | /* Support for external interrupt pins in IRQ mode */ | |
621 | static struct intc_vect irq_vectors[] __initdata = { | |
622 | INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280), | |
623 | INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300), | |
624 | INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380), | |
625 | }; | |
626 | ||
627 | static struct intc_mask_reg irq_mask_registers[] __initdata = { | |
628 | { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */ | |
629 | { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } }, | |
630 | }; | |
631 | ||
632 | static struct intc_prio_reg irq_prio_registers[] __initdata = { | |
633 | { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3, | |
634 | IRQ4, IRQ5, } }, | |
635 | }; | |
636 | ||
637 | static struct intc_sense_reg irq_sense_registers[] __initdata = { | |
638 | { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3, | |
639 | IRQ4, IRQ5, } }, | |
640 | }; | |
641 | ||
642 | static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors, | |
643 | NULL, irq_mask_registers, irq_prio_registers, | |
644 | irq_sense_registers); | |
645 | ||
646 | /* External interrupt pins in IRL mode */ | |
647 | static struct intc_vect irl_vectors[] __initdata = { | |
648 | INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220), | |
649 | INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260), | |
650 | INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0), | |
651 | INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0), | |
652 | INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320), | |
653 | INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360), | |
654 | INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0), | |
655 | INTC_VECT(IRL_HHHL, 0x3c0), | |
656 | }; | |
657 | ||
658 | static struct intc_mask_reg irl3210_mask_registers[] __initdata = { | |
659 | { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ | |
660 | { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, | |
661 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, | |
662 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, | |
663 | IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, | |
664 | }; | |
665 | ||
666 | static struct intc_mask_reg irl7654_mask_registers[] __initdata = { | |
667 | { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */ | |
668 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
669 | IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH, | |
670 | IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH, | |
671 | IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH, | |
672 | IRL_HHLL, IRL_HHLH, IRL_HHHL, } }, | |
673 | }; | |
674 | ||
675 | static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors, | |
676 | NULL, irl7654_mask_registers, NULL, NULL); | |
677 | ||
678 | static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors, | |
679 | NULL, irl3210_mask_registers, NULL, NULL); | |
680 | ||
681 | #define INTC_ICR0 0xffd00000 | |
682 | #define INTC_INTMSK0 0xffd00044 | |
683 | #define INTC_INTMSK1 0xffd00048 | |
684 | #define INTC_INTMSK2 0xffd40080 | |
685 | #define INTC_INTMSKCLR1 0xffd00068 | |
686 | #define INTC_INTMSKCLR2 0xffd40084 | |
687 | ||
35f3abe9 PM |
688 | void __init plat_irq_setup(void) |
689 | { | |
9304d0cc | 690 | /* disable IRQ7-0 */ |
9d56dd3b | 691 | __raw_writel(0xff000000, INTC_INTMSK0); |
9304d0cc MD |
692 | |
693 | /* disable IRL3-0 + IRL7-4 */ | |
9d56dd3b PM |
694 | __raw_writel(0xc0000000, INTC_INTMSK1); |
695 | __raw_writel(0xfffefffe, INTC_INTMSK2); | |
9304d0cc MD |
696 | |
697 | /* select IRL mode for IRL3-0 + IRL7-4 */ | |
9d56dd3b | 698 | __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); |
9304d0cc MD |
699 | |
700 | /* disable holding function, ie enable "SH-4 Mode" */ | |
9d56dd3b | 701 | __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0); |
9304d0cc MD |
702 | |
703 | register_intc_controller(&intc_desc); | |
704 | } | |
705 | ||
706 | void __init plat_irq_setup_pins(int mode) | |
707 | { | |
708 | switch (mode) { | |
709 | case IRQ_MODE_IRQ: | |
710 | /* select IRQ mode for IRL3-0 + IRL7-4 */ | |
9d56dd3b | 711 | __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0); |
9304d0cc MD |
712 | register_intc_controller(&intc_irq_desc); |
713 | break; | |
714 | case IRQ_MODE_IRL7654: | |
715 | /* enable IRL7-4 but don't provide any masking */ | |
9d56dd3b PM |
716 | __raw_writel(0x40000000, INTC_INTMSKCLR1); |
717 | __raw_writel(0x0000fffe, INTC_INTMSKCLR2); | |
9304d0cc MD |
718 | break; |
719 | case IRQ_MODE_IRL3210: | |
720 | /* enable IRL0-3 but don't provide any masking */ | |
9d56dd3b PM |
721 | __raw_writel(0x80000000, INTC_INTMSKCLR1); |
722 | __raw_writel(0xfffe0000, INTC_INTMSKCLR2); | |
9304d0cc MD |
723 | break; |
724 | case IRQ_MODE_IRL7654_MASK: | |
725 | /* enable IRL7-4 and mask using cpu intc controller */ | |
9d56dd3b | 726 | __raw_writel(0x40000000, INTC_INTMSKCLR1); |
9304d0cc MD |
727 | register_intc_controller(&intc_irl7654_desc); |
728 | break; | |
729 | case IRQ_MODE_IRL3210_MASK: | |
730 | /* enable IRL0-3 and mask using cpu intc controller */ | |
9d56dd3b | 731 | __raw_writel(0x80000000, INTC_INTMSKCLR1); |
9304d0cc MD |
732 | register_intc_controller(&intc_irl3210_desc); |
733 | break; | |
734 | default: | |
735 | BUG(); | |
736 | } | |
35f3abe9 | 737 | } |