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5933f6d2 | 1 | // SPDX-License-Identifier: GPL-2.0 |
6b002230 PM |
2 | /* |
3 | * 'traps.c' handles hardware traps and faults after we have saved some | |
4 | * state in 'entry.S'. | |
1da177e4 LT |
5 | * |
6 | * SuperH version: Copyright (C) 1999 Niibe Yutaka | |
7 | * Copyright (C) 2000 Philipp Rumpf | |
8 | * Copyright (C) 2000 David Howells | |
ace2dc7d | 9 | * Copyright (C) 2002 - 2010 Paul Mundt |
1da177e4 | 10 | */ |
1da177e4 | 11 | #include <linux/kernel.h> |
1da177e4 | 12 | #include <linux/ptrace.h> |
ba84be23 | 13 | #include <linux/hardirq.h> |
1da177e4 | 14 | #include <linux/init.h> |
1da177e4 | 15 | #include <linux/spinlock.h> |
1da177e4 | 16 | #include <linux/kallsyms.h> |
1f666587 | 17 | #include <linux/io.h> |
fa691511 | 18 | #include <linux/bug.h> |
9b8c90eb | 19 | #include <linux/debug_locks.h> |
b118ca57 | 20 | #include <linux/kdebug.h> |
dc34d312 | 21 | #include <linux/limits.h> |
af67c3a9 | 22 | #include <linux/sysfs.h> |
a99eae54 | 23 | #include <linux/uaccess.h> |
ace2dc7d | 24 | #include <linux/perf_event.h> |
68db0cf1 IM |
25 | #include <linux/sched/task_stack.h> |
26 | ||
a99eae54 | 27 | #include <asm/alignment.h> |
fad0f901 | 28 | #include <asm/fpu.h> |
d39f5450 | 29 | #include <asm/kprobes.h> |
e839ca52 DH |
30 | #include <asm/traps.h> |
31 | #include <asm/bl_bit.h> | |
1da177e4 | 32 | |
1da177e4 | 33 | #ifdef CONFIG_CPU_SH2 |
0983b318 YS |
34 | # define TRAP_RESERVED_INST 4 |
35 | # define TRAP_ILLEGAL_SLOT_INST 6 | |
36 | # define TRAP_ADDRESS_ERROR 9 | |
37 | # ifdef CONFIG_CPU_SH2A | |
cd89436e | 38 | # define TRAP_UBC 12 |
6e80f5e8 | 39 | # define TRAP_FPU_ERROR 13 |
0983b318 YS |
40 | # define TRAP_DIVZERO_ERROR 17 |
41 | # define TRAP_DIVOVF_ERROR 18 | |
42 | # endif | |
1da177e4 LT |
43 | #else |
44 | #define TRAP_RESERVED_INST 12 | |
45 | #define TRAP_ILLEGAL_SLOT_INST 13 | |
46 | #endif | |
47 | ||
86c0179c MD |
48 | static inline void sign_extend(unsigned int count, unsigned char *dst) |
49 | { | |
50 | #ifdef __LITTLE_ENDIAN__ | |
4252c659 MD |
51 | if ((count == 1) && dst[0] & 0x80) { |
52 | dst[1] = 0xff; | |
53 | dst[2] = 0xff; | |
54 | dst[3] = 0xff; | |
55 | } | |
86c0179c MD |
56 | if ((count == 2) && dst[1] & 0x80) { |
57 | dst[2] = 0xff; | |
58 | dst[3] = 0xff; | |
59 | } | |
60 | #else | |
4252c659 MD |
61 | if ((count == 1) && dst[3] & 0x80) { |
62 | dst[2] = 0xff; | |
63 | dst[1] = 0xff; | |
86c0179c | 64 | dst[0] = 0xff; |
4252c659 MD |
65 | } |
66 | if ((count == 2) && dst[2] & 0x80) { | |
86c0179c | 67 | dst[1] = 0xff; |
4252c659 | 68 | dst[0] = 0xff; |
86c0179c MD |
69 | } |
70 | #endif | |
71 | } | |
72 | ||
e7cc9a73 MD |
73 | static struct mem_access user_mem_access = { |
74 | copy_from_user, | |
75 | copy_to_user, | |
76 | }; | |
77 | ||
1da177e4 LT |
78 | /* |
79 | * handle an instruction that does an unaligned memory access by emulating the | |
80 | * desired behaviour | |
81 | * - note that PC _may not_ point to the faulting instruction | |
82 | * (if that instruction is in a branch delay slot) | |
83 | * - return 0 if emulation okay, -EFAULT on existential error | |
84 | */ | |
2bcfffa4 | 85 | static int handle_unaligned_ins(insn_size_t instruction, struct pt_regs *regs, |
e7cc9a73 | 86 | struct mem_access *ma) |
1da177e4 LT |
87 | { |
88 | int ret, index, count; | |
89 | unsigned long *rm, *rn; | |
90 | unsigned char *src, *dst; | |
fa43972f | 91 | unsigned char __user *srcu, *dstu; |
1da177e4 LT |
92 | |
93 | index = (instruction>>8)&15; /* 0x0F00 */ | |
94 | rn = ®s->regs[index]; | |
95 | ||
96 | index = (instruction>>4)&15; /* 0x00F0 */ | |
97 | rm = ®s->regs[index]; | |
98 | ||
99 | count = 1<<(instruction&3); | |
100 | ||
7436cde6 | 101 | switch (count) { |
a99eae54 PM |
102 | case 1: inc_unaligned_byte_access(); break; |
103 | case 2: inc_unaligned_word_access(); break; | |
104 | case 4: inc_unaligned_dword_access(); break; | |
105 | case 8: inc_unaligned_multi_access(); break; | |
7436cde6 AD |
106 | } |
107 | ||
1da177e4 LT |
108 | ret = -EFAULT; |
109 | switch (instruction>>12) { | |
110 | case 0: /* mov.[bwl] to/from memory via r0+rn */ | |
111 | if (instruction & 8) { | |
112 | /* from memory */ | |
fa43972f PM |
113 | srcu = (unsigned char __user *)*rm; |
114 | srcu += regs->regs[0]; | |
115 | dst = (unsigned char *)rn; | |
116 | *(unsigned long *)dst = 0; | |
1da177e4 | 117 | |
86c0179c | 118 | #if !defined(__LITTLE_ENDIAN__) |
1da177e4 | 119 | dst += 4-count; |
86c0179c | 120 | #endif |
fa43972f | 121 | if (ma->from(dst, srcu, count)) |
1da177e4 LT |
122 | goto fetch_fault; |
123 | ||
86c0179c | 124 | sign_extend(count, dst); |
1da177e4 LT |
125 | } else { |
126 | /* to memory */ | |
fa43972f | 127 | src = (unsigned char *)rm; |
1da177e4 LT |
128 | #if !defined(__LITTLE_ENDIAN__) |
129 | src += 4-count; | |
130 | #endif | |
fa43972f PM |
131 | dstu = (unsigned char __user *)*rn; |
132 | dstu += regs->regs[0]; | |
1da177e4 | 133 | |
fa43972f | 134 | if (ma->to(dstu, src, count)) |
1da177e4 LT |
135 | goto fetch_fault; |
136 | } | |
137 | ret = 0; | |
138 | break; | |
139 | ||
140 | case 1: /* mov.l Rm,@(disp,Rn) */ | |
141 | src = (unsigned char*) rm; | |
fa43972f PM |
142 | dstu = (unsigned char __user *)*rn; |
143 | dstu += (instruction&0x000F)<<2; | |
1da177e4 | 144 | |
fa43972f | 145 | if (ma->to(dstu, src, 4)) |
1da177e4 LT |
146 | goto fetch_fault; |
147 | ret = 0; | |
b5a1bcbe | 148 | break; |
1da177e4 LT |
149 | |
150 | case 2: /* mov.[bwl] to memory, possibly with pre-decrement */ | |
151 | if (instruction & 4) | |
152 | *rn -= count; | |
153 | src = (unsigned char*) rm; | |
fa43972f | 154 | dstu = (unsigned char __user *)*rn; |
1da177e4 LT |
155 | #if !defined(__LITTLE_ENDIAN__) |
156 | src += 4-count; | |
157 | #endif | |
fa43972f | 158 | if (ma->to(dstu, src, count)) |
1da177e4 LT |
159 | goto fetch_fault; |
160 | ret = 0; | |
161 | break; | |
162 | ||
163 | case 5: /* mov.l @(disp,Rm),Rn */ | |
fa43972f PM |
164 | srcu = (unsigned char __user *)*rm; |
165 | srcu += (instruction & 0x000F) << 2; | |
166 | dst = (unsigned char *)rn; | |
167 | *(unsigned long *)dst = 0; | |
1da177e4 | 168 | |
fa43972f | 169 | if (ma->from(dst, srcu, 4)) |
1da177e4 LT |
170 | goto fetch_fault; |
171 | ret = 0; | |
b5a1bcbe | 172 | break; |
1da177e4 LT |
173 | |
174 | case 6: /* mov.[bwl] from memory, possibly with post-increment */ | |
fa43972f | 175 | srcu = (unsigned char __user *)*rm; |
1da177e4 LT |
176 | if (instruction & 4) |
177 | *rm += count; | |
178 | dst = (unsigned char*) rn; | |
179 | *(unsigned long*)dst = 0; | |
b5a1bcbe | 180 | |
86c0179c | 181 | #if !defined(__LITTLE_ENDIAN__) |
1da177e4 | 182 | dst += 4-count; |
86c0179c | 183 | #endif |
fa43972f | 184 | if (ma->from(dst, srcu, count)) |
1da177e4 | 185 | goto fetch_fault; |
86c0179c | 186 | sign_extend(count, dst); |
1da177e4 LT |
187 | ret = 0; |
188 | break; | |
189 | ||
190 | case 8: | |
191 | switch ((instruction&0xFF00)>>8) { | |
192 | case 0x81: /* mov.w R0,@(disp,Rn) */ | |
fa43972f | 193 | src = (unsigned char *) ®s->regs[0]; |
1da177e4 LT |
194 | #if !defined(__LITTLE_ENDIAN__) |
195 | src += 2; | |
196 | #endif | |
fa43972f PM |
197 | dstu = (unsigned char __user *)*rm; /* called Rn in the spec */ |
198 | dstu += (instruction & 0x000F) << 1; | |
1da177e4 | 199 | |
fa43972f | 200 | if (ma->to(dstu, src, 2)) |
1da177e4 LT |
201 | goto fetch_fault; |
202 | ret = 0; | |
203 | break; | |
204 | ||
205 | case 0x85: /* mov.w @(disp,Rm),R0 */ | |
fa43972f PM |
206 | srcu = (unsigned char __user *)*rm; |
207 | srcu += (instruction & 0x000F) << 1; | |
208 | dst = (unsigned char *) ®s->regs[0]; | |
209 | *(unsigned long *)dst = 0; | |
1da177e4 LT |
210 | |
211 | #if !defined(__LITTLE_ENDIAN__) | |
212 | dst += 2; | |
213 | #endif | |
fa43972f | 214 | if (ma->from(dst, srcu, 2)) |
1da177e4 | 215 | goto fetch_fault; |
86c0179c | 216 | sign_extend(2, dst); |
1da177e4 LT |
217 | ret = 0; |
218 | break; | |
219 | } | |
220 | break; | |
34f7145a PE |
221 | |
222 | case 9: /* mov.w @(disp,PC),Rn */ | |
223 | srcu = (unsigned char __user *)regs->pc; | |
224 | srcu += 4; | |
225 | srcu += (instruction & 0x00FF) << 1; | |
226 | dst = (unsigned char *)rn; | |
227 | *(unsigned long *)dst = 0; | |
228 | ||
229 | #if !defined(__LITTLE_ENDIAN__) | |
230 | dst += 2; | |
231 | #endif | |
232 | ||
233 | if (ma->from(dst, srcu, 2)) | |
234 | goto fetch_fault; | |
235 | sign_extend(2, dst); | |
236 | ret = 0; | |
237 | break; | |
238 | ||
239 | case 0xd: /* mov.l @(disp,PC),Rn */ | |
240 | srcu = (unsigned char __user *)(regs->pc & ~0x3); | |
241 | srcu += 4; | |
242 | srcu += (instruction & 0x00FF) << 2; | |
243 | dst = (unsigned char *)rn; | |
244 | *(unsigned long *)dst = 0; | |
245 | ||
246 | if (ma->from(dst, srcu, 4)) | |
247 | goto fetch_fault; | |
248 | ret = 0; | |
249 | break; | |
1da177e4 LT |
250 | } |
251 | return ret; | |
252 | ||
253 | fetch_fault: | |
254 | /* Argh. Address not only misaligned but also non-existent. | |
255 | * Raise an EFAULT and see if it's trapped | |
256 | */ | |
2afb447f ST |
257 | die_if_no_fixup("Fault in unaligned fixup", regs, 0); |
258 | return -EFAULT; | |
1da177e4 LT |
259 | } |
260 | ||
261 | /* | |
262 | * emulate the instruction in the delay slot | |
263 | * - fetches the instruction from PC+2 | |
264 | */ | |
e7cc9a73 | 265 | static inline int handle_delayslot(struct pt_regs *regs, |
2bcfffa4 | 266 | insn_size_t old_instruction, |
e7cc9a73 | 267 | struct mem_access *ma) |
1da177e4 | 268 | { |
2bcfffa4 | 269 | insn_size_t instruction; |
fa43972f PM |
270 | void __user *addr = (void __user *)(regs->pc + |
271 | instruction_size(old_instruction)); | |
1da177e4 | 272 | |
4b5a9ef5 | 273 | if (copy_from_user(&instruction, addr, sizeof(instruction))) { |
1da177e4 LT |
274 | /* the instruction-fetch faulted */ |
275 | if (user_mode(regs)) | |
276 | return -EFAULT; | |
277 | ||
278 | /* kernel */ | |
b5a1bcbe SM |
279 | die("delay-slot-insn faulting in handle_unaligned_delayslot", |
280 | regs, 0); | |
1da177e4 LT |
281 | } |
282 | ||
e7cc9a73 | 283 | return handle_unaligned_ins(instruction, regs, ma); |
1da177e4 LT |
284 | } |
285 | ||
286 | /* | |
287 | * handle an instruction that does an unaligned memory access | |
288 | * - have to be careful of branch delay-slot instructions that fault | |
289 | * SH3: | |
290 | * - if the branch would be taken PC points to the branch | |
291 | * - if the branch would not be taken, PC points to delay-slot | |
292 | * SH4: | |
293 | * - PC always points to delayed branch | |
294 | * - return 0 if handled, -EFAULT if failed (may not return if in kernel) | |
295 | */ | |
296 | ||
297 | /* Macros to determine offset from current PC for branch instructions */ | |
298 | /* Explicit type coercion is used to force sign extension where needed */ | |
299 | #define SH_PC_8BIT_OFFSET(instr) ((((signed char)(instr))*2) + 4) | |
300 | #define SH_PC_12BIT_OFFSET(instr) ((((signed short)(instr<<4))>>3) + 4) | |
301 | ||
2bcfffa4 | 302 | int handle_unaligned_access(insn_size_t instruction, struct pt_regs *regs, |
ace2dc7d PM |
303 | struct mem_access *ma, int expected, |
304 | unsigned long address) | |
1da177e4 LT |
305 | { |
306 | u_int rm; | |
307 | int ret, index; | |
308 | ||
23c4c821 PM |
309 | /* |
310 | * XXX: We can't handle mixed 16/32-bit instructions yet | |
311 | */ | |
312 | if (instruction_size(instruction) != 2) | |
313 | return -EINVAL; | |
314 | ||
1da177e4 LT |
315 | index = (instruction>>8)&15; /* 0x0F00 */ |
316 | rm = regs->regs[index]; | |
317 | ||
ace2dc7d PM |
318 | /* |
319 | * Log the unexpected fixups, and then pass them on to perf. | |
320 | * | |
321 | * We intentionally don't report the expected cases to perf as | |
322 | * otherwise the trapped I/O case will skew the results too much | |
323 | * to be useful. | |
324 | */ | |
325 | if (!expected) { | |
a99eae54 | 326 | unaligned_fixups_notify(current, instruction, regs); |
a8b0ca17 | 327 | perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, |
ace2dc7d PM |
328 | regs, address); |
329 | } | |
1da177e4 LT |
330 | |
331 | ret = -EFAULT; | |
332 | switch (instruction&0xF000) { | |
333 | case 0x0000: | |
334 | if (instruction==0x000B) { | |
335 | /* rts */ | |
e7cc9a73 | 336 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
337 | if (ret==0) |
338 | regs->pc = regs->pr; | |
339 | } | |
340 | else if ((instruction&0x00FF)==0x0023) { | |
341 | /* braf @Rm */ | |
e7cc9a73 | 342 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
343 | if (ret==0) |
344 | regs->pc += rm + 4; | |
345 | } | |
346 | else if ((instruction&0x00FF)==0x0003) { | |
347 | /* bsrf @Rm */ | |
e7cc9a73 | 348 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
349 | if (ret==0) { |
350 | regs->pr = regs->pc + 4; | |
351 | regs->pc += rm + 4; | |
352 | } | |
353 | } | |
354 | else { | |
355 | /* mov.[bwl] to/from memory via r0+rn */ | |
356 | goto simple; | |
357 | } | |
358 | break; | |
359 | ||
360 | case 0x1000: /* mov.l Rm,@(disp,Rn) */ | |
361 | goto simple; | |
362 | ||
363 | case 0x2000: /* mov.[bwl] to memory, possibly with pre-decrement */ | |
364 | goto simple; | |
365 | ||
366 | case 0x4000: | |
367 | if ((instruction&0x00FF)==0x002B) { | |
368 | /* jmp @Rm */ | |
e7cc9a73 | 369 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
370 | if (ret==0) |
371 | regs->pc = rm; | |
372 | } | |
373 | else if ((instruction&0x00FF)==0x000B) { | |
374 | /* jsr @Rm */ | |
e7cc9a73 | 375 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
376 | if (ret==0) { |
377 | regs->pr = regs->pc + 4; | |
378 | regs->pc = rm; | |
379 | } | |
380 | } | |
381 | else { | |
382 | /* mov.[bwl] to/from memory via r0+rn */ | |
383 | goto simple; | |
384 | } | |
385 | break; | |
386 | ||
387 | case 0x5000: /* mov.l @(disp,Rm),Rn */ | |
388 | goto simple; | |
389 | ||
390 | case 0x6000: /* mov.[bwl] from memory, possibly with post-increment */ | |
391 | goto simple; | |
392 | ||
393 | case 0x8000: /* bf lab, bf/s lab, bt lab, bt/s lab */ | |
394 | switch (instruction&0x0F00) { | |
395 | case 0x0100: /* mov.w R0,@(disp,Rm) */ | |
396 | goto simple; | |
397 | case 0x0500: /* mov.w @(disp,Rm),R0 */ | |
398 | goto simple; | |
399 | case 0x0B00: /* bf lab - no delayslot*/ | |
0710b91c | 400 | ret = 0; |
1da177e4 LT |
401 | break; |
402 | case 0x0F00: /* bf/s lab */ | |
e7cc9a73 | 403 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
404 | if (ret==0) { |
405 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) | |
406 | if ((regs->sr & 0x00000001) != 0) | |
407 | regs->pc += 4; /* next after slot */ | |
408 | else | |
409 | #endif | |
410 | regs->pc += SH_PC_8BIT_OFFSET(instruction); | |
411 | } | |
412 | break; | |
413 | case 0x0900: /* bt lab - no delayslot */ | |
0710b91c | 414 | ret = 0; |
1da177e4 LT |
415 | break; |
416 | case 0x0D00: /* bt/s lab */ | |
e7cc9a73 | 417 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
418 | if (ret==0) { |
419 | #if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) | |
420 | if ((regs->sr & 0x00000001) == 0) | |
421 | regs->pc += 4; /* next after slot */ | |
422 | else | |
423 | #endif | |
424 | regs->pc += SH_PC_8BIT_OFFSET(instruction); | |
425 | } | |
426 | break; | |
427 | } | |
428 | break; | |
429 | ||
34f7145a PE |
430 | case 0x9000: /* mov.w @(disp,Rm),Rn */ |
431 | goto simple; | |
432 | ||
1da177e4 | 433 | case 0xA000: /* bra label */ |
e7cc9a73 | 434 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
435 | if (ret==0) |
436 | regs->pc += SH_PC_12BIT_OFFSET(instruction); | |
437 | break; | |
438 | ||
439 | case 0xB000: /* bsr label */ | |
e7cc9a73 | 440 | ret = handle_delayslot(regs, instruction, ma); |
1da177e4 LT |
441 | if (ret==0) { |
442 | regs->pr = regs->pc + 4; | |
443 | regs->pc += SH_PC_12BIT_OFFSET(instruction); | |
444 | } | |
445 | break; | |
34f7145a PE |
446 | |
447 | case 0xD000: /* mov.l @(disp,Rm),Rn */ | |
448 | goto simple; | |
1da177e4 LT |
449 | } |
450 | return ret; | |
451 | ||
452 | /* handle non-delay-slot instruction */ | |
453 | simple: | |
e7cc9a73 | 454 | ret = handle_unaligned_ins(instruction, regs, ma); |
1da177e4 | 455 | if (ret==0) |
53f983a9 | 456 | regs->pc += instruction_size(instruction); |
1da177e4 LT |
457 | return ret; |
458 | } | |
459 | ||
460 | /* | |
b5a1bcbe SM |
461 | * Handle various address error exceptions: |
462 | * - instruction address error: | |
463 | * misaligned PC | |
464 | * PC >= 0x80000000 in user mode | |
465 | * - data address error (read and write) | |
466 | * misaligned data access | |
467 | * access to >= 0x80000000 is user mode | |
468 | * Unfortuntaly we can't distinguish between instruction address error | |
e868d612 | 469 | * and data address errors caused by read accesses. |
1da177e4 | 470 | */ |
f0bc814c | 471 | asmlinkage void do_address_error(struct pt_regs *regs, |
1da177e4 LT |
472 | unsigned long writeaccess, |
473 | unsigned long address) | |
474 | { | |
0983b318 | 475 | unsigned long error_code = 0; |
1da177e4 | 476 | mm_segment_t oldfs; |
2bcfffa4 | 477 | insn_size_t instruction; |
1da177e4 LT |
478 | int tmp; |
479 | ||
0983b318 YS |
480 | /* Intentional ifdef */ |
481 | #ifdef CONFIG_CPU_HAS_SR_RB | |
4c59e294 | 482 | error_code = lookup_exception_vector(); |
0983b318 | 483 | #endif |
1da177e4 | 484 | |
1da177e4 | 485 | if (user_mode(regs)) { |
b5a1bcbe | 486 | int si_code = BUS_ADRERR; |
a99eae54 | 487 | unsigned int user_action; |
b5a1bcbe | 488 | |
1da177e4 | 489 | local_irq_enable(); |
a99eae54 | 490 | inc_unaligned_user_access(); |
7436cde6 | 491 | |
3d13f313 | 492 | oldfs = force_uaccess_begin(); |
23c4c821 PM |
493 | if (copy_from_user(&instruction, (insn_size_t *)(regs->pc & ~1), |
494 | sizeof(instruction))) { | |
3d13f313 | 495 | force_uaccess_end(oldfs); |
5a0ab35e AD |
496 | goto uspace_segv; |
497 | } | |
3d13f313 | 498 | force_uaccess_end(oldfs); |
5a0ab35e | 499 | |
7436cde6 | 500 | /* shout about userspace fixups */ |
a99eae54 | 501 | unaligned_fixups_notify(current, instruction, regs); |
7436cde6 | 502 | |
a99eae54 PM |
503 | user_action = unaligned_user_action(); |
504 | if (user_action & UM_FIXUP) | |
7436cde6 | 505 | goto fixup; |
a99eae54 | 506 | if (user_action & UM_SIGNAL) |
7436cde6 AD |
507 | goto uspace_segv; |
508 | else { | |
509 | /* ignore */ | |
5a0ab35e | 510 | regs->pc += instruction_size(instruction); |
7436cde6 AD |
511 | return; |
512 | } | |
513 | ||
514 | fixup: | |
1da177e4 | 515 | /* bad PC is not something we can fix */ |
b5a1bcbe SM |
516 | if (regs->pc & 1) { |
517 | si_code = BUS_ADRALN; | |
1da177e4 | 518 | goto uspace_segv; |
b5a1bcbe | 519 | } |
1da177e4 | 520 | |
3d13f313 | 521 | oldfs = force_uaccess_begin(); |
e7cc9a73 | 522 | tmp = handle_unaligned_access(instruction, regs, |
ace2dc7d PM |
523 | &user_mem_access, 0, |
524 | address); | |
3d13f313 | 525 | force_uaccess_end(oldfs); |
1da177e4 | 526 | |
a99eae54 | 527 | if (tmp == 0) |
1da177e4 | 528 | return; /* sorted */ |
b5a1bcbe SM |
529 | uspace_segv: |
530 | printk(KERN_NOTICE "Sending SIGBUS to \"%s\" due to unaligned " | |
531 | "access (PC %lx PR %lx)\n", current->comm, regs->pc, | |
532 | regs->pr); | |
533 | ||
2e1661d2 | 534 | force_sig_fault(SIGBUS, si_code, (void __user *)address); |
1da177e4 | 535 | } else { |
a99eae54 | 536 | inc_unaligned_kernel_access(); |
7436cde6 | 537 | |
1da177e4 LT |
538 | if (regs->pc & 1) |
539 | die("unaligned program counter", regs, error_code); | |
540 | ||
541 | set_fs(KERNEL_DS); | |
fa43972f | 542 | if (copy_from_user(&instruction, (void __user *)(regs->pc), |
4b5a9ef5 | 543 | sizeof(instruction))) { |
1da177e4 LT |
544 | /* Argh. Fault on the instruction itself. |
545 | This should never happen non-SMP | |
546 | */ | |
547 | set_fs(oldfs); | |
548 | die("insn faulting in do_address_error", regs, 0); | |
549 | } | |
550 | ||
a99eae54 | 551 | unaligned_fixups_notify(current, instruction, regs); |
40258ee9 | 552 | |
ace2dc7d PM |
553 | handle_unaligned_access(instruction, regs, &user_mem_access, |
554 | 0, address); | |
1da177e4 LT |
555 | set_fs(oldfs); |
556 | } | |
557 | } | |
558 | ||
559 | #ifdef CONFIG_SH_DSP | |
560 | /* | |
561 | * SH-DSP support gerg@snapgear.com. | |
562 | */ | |
563 | int is_dsp_inst(struct pt_regs *regs) | |
564 | { | |
882c12c4 | 565 | unsigned short inst = 0; |
1da177e4 | 566 | |
f0bc814c | 567 | /* |
1da177e4 LT |
568 | * Safe guard if DSP mode is already enabled or we're lacking |
569 | * the DSP altogether. | |
570 | */ | |
11c19656 | 571 | if (!(current_cpu_data.flags & CPU_HAS_DSP) || (regs->sr & SR_DSP)) |
1da177e4 LT |
572 | return 0; |
573 | ||
574 | get_user(inst, ((unsigned short *) regs->pc)); | |
575 | ||
576 | inst &= 0xf000; | |
577 | ||
578 | /* Check for any type of DSP or support instruction */ | |
579 | if ((inst == 0xf000) || (inst == 0x4000)) | |
580 | return 1; | |
581 | ||
582 | return 0; | |
583 | } | |
584 | #else | |
585 | #define is_dsp_inst(regs) (0) | |
586 | #endif /* CONFIG_SH_DSP */ | |
587 | ||
0983b318 | 588 | #ifdef CONFIG_CPU_SH2A |
a3c19514 | 589 | asmlinkage void do_divide_error(unsigned long r4) |
0983b318 | 590 | { |
c65626c0 | 591 | int code; |
0983b318 | 592 | |
0983b318 YS |
593 | switch (r4) { |
594 | case TRAP_DIVZERO_ERROR: | |
c65626c0 | 595 | code = FPE_INTDIV; |
0983b318 YS |
596 | break; |
597 | case TRAP_DIVOVF_ERROR: | |
c65626c0 | 598 | code = FPE_INTOVF; |
0983b318 | 599 | break; |
26da3501 EB |
600 | default: |
601 | /* Let gcc know unhandled cases don't make it past here */ | |
602 | return; | |
0983b318 | 603 | } |
2e1661d2 | 604 | force_sig_fault(SIGFPE, code, NULL); |
0983b318 YS |
605 | } |
606 | #endif | |
607 | ||
a3c19514 | 608 | asmlinkage void do_reserved_inst(void) |
4b565680 | 609 | { |
a3c19514 | 610 | struct pt_regs *regs = current_pt_regs(); |
4b565680 | 611 | unsigned long error_code; |
4b565680 TY |
612 | |
613 | #ifdef CONFIG_SH_FPU_EMU | |
0983b318 | 614 | unsigned short inst = 0; |
4b565680 TY |
615 | int err; |
616 | ||
f0bc814c | 617 | get_user(inst, (unsigned short*)regs->pc); |
4b565680 | 618 | |
f0bc814c | 619 | err = do_fpu_inst(inst, regs); |
4b565680 | 620 | if (!err) { |
53f983a9 | 621 | regs->pc += instruction_size(inst); |
4b565680 TY |
622 | return; |
623 | } | |
624 | /* not a FPU inst. */ | |
625 | #endif | |
626 | ||
627 | #ifdef CONFIG_SH_DSP | |
628 | /* Check if it's a DSP instruction */ | |
b5a1bcbe | 629 | if (is_dsp_inst(regs)) { |
4b565680 | 630 | /* Enable DSP mode, and restart instruction. */ |
f0bc814c | 631 | regs->sr |= SR_DSP; |
01ab1039 | 632 | /* Save DSP mode */ |
3cf5d076 | 633 | current->thread.dsp_status.status |= SR_DSP; |
4b565680 TY |
634 | return; |
635 | } | |
636 | #endif | |
637 | ||
4c59e294 | 638 | error_code = lookup_exception_vector(); |
0983b318 | 639 | |
4b565680 | 640 | local_irq_enable(); |
3cf5d076 | 641 | force_sig(SIGILL); |
f0bc814c | 642 | die_if_no_fixup("reserved instruction", regs, error_code); |
4b565680 TY |
643 | } |
644 | ||
645 | #ifdef CONFIG_SH_FPU_EMU | |
edfd6da0 | 646 | static int emulate_branch(unsigned short inst, struct pt_regs *regs) |
4b565680 TY |
647 | { |
648 | /* | |
649 | * bfs: 8fxx: PC+=d*2+4; | |
650 | * bts: 8dxx: PC+=d*2+4; | |
651 | * bra: axxx: PC+=D*2+4; | |
652 | * bsr: bxxx: PC+=D*2+4 after PR=PC+4; | |
653 | * braf:0x23: PC+=Rn*2+4; | |
654 | * bsrf:0x03: PC+=Rn*2+4 after PR=PC+4; | |
655 | * jmp: 4x2b: PC=Rn; | |
656 | * jsr: 4x0b: PC=Rn after PR=PC+4; | |
657 | * rts: 000b: PC=PR; | |
658 | */ | |
edfd6da0 PM |
659 | if (((inst & 0xf000) == 0xb000) || /* bsr */ |
660 | ((inst & 0xf0ff) == 0x0003) || /* bsrf */ | |
661 | ((inst & 0xf0ff) == 0x400b)) /* jsr */ | |
662 | regs->pr = regs->pc + 4; | |
663 | ||
664 | if ((inst & 0xfd00) == 0x8d00) { /* bfs, bts */ | |
4b565680 TY |
665 | regs->pc += SH_PC_8BIT_OFFSET(inst); |
666 | return 0; | |
667 | } | |
668 | ||
edfd6da0 | 669 | if ((inst & 0xe000) == 0xa000) { /* bra, bsr */ |
4b565680 TY |
670 | regs->pc += SH_PC_12BIT_OFFSET(inst); |
671 | return 0; | |
672 | } | |
673 | ||
edfd6da0 | 674 | if ((inst & 0xf0df) == 0x0003) { /* braf, bsrf */ |
4b565680 TY |
675 | regs->pc += regs->regs[(inst & 0x0f00) >> 8] + 4; |
676 | return 0; | |
677 | } | |
678 | ||
edfd6da0 | 679 | if ((inst & 0xf0df) == 0x400b) { /* jmp, jsr */ |
4b565680 TY |
680 | regs->pc = regs->regs[(inst & 0x0f00) >> 8]; |
681 | return 0; | |
682 | } | |
683 | ||
edfd6da0 | 684 | if ((inst & 0xffff) == 0x000b) { /* rts */ |
4b565680 TY |
685 | regs->pc = regs->pr; |
686 | return 0; | |
687 | } | |
688 | ||
689 | return 1; | |
690 | } | |
691 | #endif | |
692 | ||
a3c19514 | 693 | asmlinkage void do_illegal_slot_inst(void) |
4b565680 | 694 | { |
a3c19514 | 695 | struct pt_regs *regs = current_pt_regs(); |
b3d765f5 | 696 | unsigned long inst; |
d39f5450 CS |
697 | |
698 | if (kprobe_handle_illslot(regs->pc) == 0) | |
699 | return; | |
700 | ||
4b565680 | 701 | #ifdef CONFIG_SH_FPU_EMU |
f0bc814c SM |
702 | get_user(inst, (unsigned short *)regs->pc + 1); |
703 | if (!do_fpu_inst(inst, regs)) { | |
704 | get_user(inst, (unsigned short *)regs->pc); | |
705 | if (!emulate_branch(inst, regs)) | |
4b565680 TY |
706 | return; |
707 | /* fault in branch.*/ | |
708 | } | |
709 | /* not a FPU inst. */ | |
710 | #endif | |
711 | ||
4c59e294 | 712 | inst = lookup_exception_vector(); |
0983b318 | 713 | |
4b565680 | 714 | local_irq_enable(); |
3cf5d076 | 715 | force_sig(SIGILL); |
b3d765f5 | 716 | die_if_no_fixup("illegal slot instruction", regs, inst); |
4b565680 | 717 | } |
1da177e4 | 718 | |
a3c19514 | 719 | asmlinkage void do_exception_error(void) |
1da177e4 LT |
720 | { |
721 | long ex; | |
0983b318 | 722 | |
4c59e294 | 723 | ex = lookup_exception_vector(); |
a3c19514 | 724 | die_if_kernel("exception", current_pt_regs(), ex); |
1da177e4 LT |
725 | } |
726 | ||
4603f53a | 727 | void per_cpu_trap_init(void) |
1da177e4 LT |
728 | { |
729 | extern void *vbr_base; | |
730 | ||
1da177e4 LT |
731 | /* NOTE: The VBR value should be at P1 |
732 | (or P2, virtural "fixed" address space). | |
733 | It's definitely should not in physical address. */ | |
734 | ||
735 | asm volatile("ldc %0, vbr" | |
736 | : /* no output */ | |
737 | : "r" (&vbr_base) | |
738 | : "memory"); | |
68a1aed7 MD |
739 | |
740 | /* disable exception blocking now when the vbr has been setup */ | |
741 | clear_bl_bit(); | |
1da177e4 LT |
742 | } |
743 | ||
1f666587 | 744 | void *set_exception_table_vec(unsigned int vec, void *handler) |
1da177e4 LT |
745 | { |
746 | extern void *exception_handling_table[]; | |
1f666587 | 747 | void *old_handler; |
b5a1bcbe | 748 | |
1f666587 PM |
749 | old_handler = exception_handling_table[vec]; |
750 | exception_handling_table[vec] = handler; | |
751 | return old_handler; | |
752 | } | |
1da177e4 | 753 | |
1f666587 PM |
754 | void __init trap_init(void) |
755 | { | |
756 | set_exception_table_vec(TRAP_RESERVED_INST, do_reserved_inst); | |
757 | set_exception_table_vec(TRAP_ILLEGAL_SLOT_INST, do_illegal_slot_inst); | |
1da177e4 | 758 | |
4b565680 TY |
759 | #if defined(CONFIG_CPU_SH4) && !defined(CONFIG_SH_FPU) || \ |
760 | defined(CONFIG_SH_FPU_EMU) | |
761 | /* | |
762 | * For SH-4 lacking an FPU, treat floating point instructions as | |
763 | * reserved. They'll be handled in the math-emu case, or faulted on | |
764 | * otherwise. | |
765 | */ | |
1f666587 PM |
766 | set_exception_table_evt(0x800, do_reserved_inst); |
767 | set_exception_table_evt(0x820, do_illegal_slot_inst); | |
768 | #elif defined(CONFIG_SH_FPU) | |
74d99a5e PM |
769 | set_exception_table_evt(0x800, fpu_state_restore_trap_handler); |
770 | set_exception_table_evt(0x820, fpu_state_restore_trap_handler); | |
1da177e4 | 771 | #endif |
0983b318 YS |
772 | |
773 | #ifdef CONFIG_CPU_SH2 | |
5a4f7c66 | 774 | set_exception_table_vec(TRAP_ADDRESS_ERROR, address_error_trap_handler); |
0983b318 YS |
775 | #endif |
776 | #ifdef CONFIG_CPU_SH2A | |
777 | set_exception_table_vec(TRAP_DIVZERO_ERROR, do_divide_error); | |
778 | set_exception_table_vec(TRAP_DIVOVF_ERROR, do_divide_error); | |
6e80f5e8 YS |
779 | #ifdef CONFIG_SH_FPU |
780 | set_exception_table_vec(TRAP_FPU_ERROR, fpu_error_trap_handler); | |
781 | #endif | |
0983b318 | 782 | #endif |
b5a1bcbe | 783 | |
cd89436e | 784 | #ifdef TRAP_UBC |
c4761815 | 785 | set_exception_table_vec(TRAP_UBC, breakpoint_trap_handler); |
cd89436e | 786 | #endif |
1da177e4 | 787 | } |