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sh64: Use generic unaligned access control/counters.
[mirror_ubuntu-bionic-kernel.git] / arch / sh / kernel / traps_64.c
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1da177e4 1/*
a23ba435 2 * arch/sh/kernel/traps_64.c
1da177e4
LT		 3 *
4 * Copyright (C) 2000, 2001 Paolo Alberelli
5 * Copyright (C) 2003, 2004 Paul Mundt
6 * Copyright (C) 2003, 2004 Richard Curnow
7 *
a23ba435
PM		 8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
1da177e4
LT		 11 */
12#include <linux/sched.h>
13#include <linux/kernel.h>
14#include <linux/string.h>
15#include <linux/errno.h>
16#include <linux/ptrace.h>
17#include <linux/timer.h>
18#include <linux/mm.h>
19#include <linux/smp.h>
1da177e4
LT		 20#include <linux/init.h>
21#include <linux/delay.h>
22#include <linux/spinlock.h>
23#include <linux/kallsyms.h>
24#include <linux/interrupt.h>
25#include <linux/sysctl.h>
26#include <linux/module.h>
ace2dc7d 27#include <linux/perf_event.h>
1da177e4
LT		 28#include <asm/uaccess.h>
29#include <asm/io.h>
db218b3d 30#include <asm/alignment.h>
1da177e4
LT		 31#include <asm/processor.h>
32#include <asm/pgtable.h>
50387b3e 33#include <asm/fpu.h>
1da177e4
LT		 34
35#undef DEBUG_EXCEPTION
36#ifdef DEBUG_EXCEPTION
37/* implemented in ../lib/dbg.c */
38extern void show_excp_regs(char *fname, int trapnr, int signr,
39 struct pt_regs *regs);
40#else
41#define show_excp_regs(a, b, c, d)
42#endif
43
44static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
45 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk);
46
47#define DO_ERROR(trapnr, signr, str, name, tsk) \
48asmlinkage void do_##name(unsigned long error_code, struct pt_regs *regs) \
49{ \
50 do_unhandled_exception(trapnr, signr, str, __stringify(name), error_code, regs, current); \
51}
52
bde40898 53static DEFINE_SPINLOCK(die_lock);
1da177e4
LT		 54
55void die(const char * str, struct pt_regs * regs, long err)
56{
57 console_verbose();
58 spin_lock_irq(&die_lock);
59 printk("%s: %lx\n", str, (err & 0xffffff));
60 show_regs(regs);
61 spin_unlock_irq(&die_lock);
62 do_exit(SIGSEGV);
63}
64
65static inline void die_if_kernel(const char * str, struct pt_regs * regs, long err)
66{
67 if (!user_mode(regs))
68 die(str, regs, err);
69}
70
71static void die_if_no_fixup(const char * str, struct pt_regs * regs, long err)
72{
73 if (!user_mode(regs)) {
74 const struct exception_table_entry *fixup;
75 fixup = search_exception_tables(regs->pc);
76 if (fixup) {
77 regs->pc = fixup->fixup;
78 return;
79 }
80 die(str, regs, err);
81 }
82}
83
84DO_ERROR(13, SIGILL, "illegal slot instruction", illegal_slot_inst, current)
85DO_ERROR(87, SIGSEGV, "address error (exec)", address_error_exec, current)
86
87
88/* Implement misaligned load/store handling for kernel (and optionally for user
89 mode too). Limitation : only SHmedia mode code is handled - there is no
90 handling at all for misaligned accesses occurring in SHcompact code yet. */
91
92static int misaligned_fixup(struct pt_regs *regs);
93
94asmlinkage void do_address_error_load(unsigned long error_code, struct pt_regs *regs)
95{
96 if (misaligned_fixup(regs) < 0) {
97 do_unhandled_exception(7, SIGSEGV, "address error(load)",
98 "do_address_error_load",
99 error_code, regs, current);
100 }
101 return;
102}
103
104asmlinkage void do_address_error_store(unsigned long error_code, struct pt_regs *regs)
105{
106 if (misaligned_fixup(regs) < 0) {
107 do_unhandled_exception(8, SIGSEGV, "address error(store)",
108 "do_address_error_store",
109 error_code, regs, current);
110 }
111 return;
112}
113
114#if defined(CONFIG_SH64_ID2815_WORKAROUND)
115
116#define OPCODE_INVALID 0
117#define OPCODE_USER_VALID 1
118#define OPCODE_PRIV_VALID 2
119
120/* getcon/putcon - requires checking which control register is referenced. */
121#define OPCODE_CTRL_REG 3
122
123/* Table of valid opcodes for SHmedia mode.
124 Form a 10-bit value by concatenating the major/minor opcodes i.e.
125 opcode[31:26,20:16]. The 6 MSBs of this value index into the following
126 array. The 4 LSBs select the bit-pair in the entry (bits 1:0 correspond to
127 LSBs==4'b0000 etc). */
128static unsigned long shmedia_opcode_table[64] = {
129 0x55554044,0x54445055,0x15141514,0x14541414,0x00000000,0x10001000,0x01110055,0x04050015,
130 0x00000444,0xc0000000,0x44545515,0x40405555,0x55550015,0x10005555,0x55555505,0x04050000,
131 0x00000555,0x00000404,0x00040445,0x15151414,0x00000000,0x00000000,0x00000000,0x00000000,
132 0x00000055,0x40404444,0x00000404,0xc0009495,0x00000000,0x00000000,0x00000000,0x00000000,
133 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
134 0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
135 0x80005050,0x04005055,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,0x55555555,
136 0x81055554,0x00000404,0x55555555,0x55555555,0x00000000,0x00000000,0x00000000,0x00000000
137};
138
139void do_reserved_inst(unsigned long error_code, struct pt_regs *regs)
140{
141 /* Workaround SH5-101 cut2 silicon defect #2815 :
142 in some situations, inter-mode branches from SHcompact -> SHmedia
143 which should take ITLBMISS or EXECPROT exceptions at the target
144 falsely take RESINST at the target instead. */
145
146 unsigned long opcode = 0x6ff4fff0; /* guaranteed reserved opcode */
147 unsigned long pc, aligned_pc;
148 int get_user_error;
149 int trapnr = 12;
150 int signr = SIGILL;
151 char *exception_name = "reserved_instruction";
152
153 pc = regs->pc;
154 if ((pc & 3) == 1) {
155 /* SHmedia : check for defect. This requires executable vmas
156 to be readable too. */
157 aligned_pc = pc & ~3;
158 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(unsigned long))) {
159 get_user_error = -EFAULT;
160 } else {
161 get_user_error = __get_user(opcode, (unsigned long *)aligned_pc);
162 }
163 if (get_user_error >= 0) {
164 unsigned long index, shift;
165 unsigned long major, minor, combined;
166 unsigned long reserved_field;
167 reserved_field = opcode & 0xf; /* These bits are currently reserved as zero in all valid opcodes */
168 major = (opcode >> 26) & 0x3f;
169 minor = (opcode >> 16) & 0xf;
170 combined = (major << 4) | minor;
171 index = major;
172 shift = minor << 1;
173 if (reserved_field == 0) {
174 int opcode_state = (shmedia_opcode_table[index] >> shift) & 0x3;
175 switch (opcode_state) {
176 case OPCODE_INVALID:
177 /* Trap. */
178 break;
179 case OPCODE_USER_VALID:
180 /* Restart the instruction : the branch to the instruction will now be from an RTE
181 not from SHcompact so the silicon defect won't be triggered. */
182 return;
183 case OPCODE_PRIV_VALID:
184 if (!user_mode(regs)) {
185 /* Should only ever get here if a module has
186 SHcompact code inside it. If so, the same fix up is needed. */
187 return; /* same reason */
188 }
189 /* Otherwise, user mode trying to execute a privileged instruction -
190 fall through to trap. */
191 break;
192 case OPCODE_CTRL_REG:
193 /* If in privileged mode, return as above. */
194 if (!user_mode(regs)) return;
195 /* In user mode ... */
196 if (combined == 0x9f) { /* GETCON */
197 unsigned long regno = (opcode >> 20) & 0x3f;
198 if (regno >= 62) {
199 return;
200 }
201 /* Otherwise, reserved or privileged control register, => trap */
202 } else if (combined == 0x1bf) { /* PUTCON */
203 unsigned long regno = (opcode >> 4) & 0x3f;
204 if (regno >= 62) {
205 return;
206 }
207 /* Otherwise, reserved or privileged control register, => trap */
208 } else {
209 /* Trap */
210 }
211 break;
212 default:
213 /* Fall through to trap. */
214 break;
215 }
216 }
217 /* fall through to normal resinst processing */
218 } else {
219 /* Error trying to read opcode. This typically means a
220 real fault, not a RESINST any more. So change the
221 codes. */
222 trapnr = 87;
223 exception_name = "address error (exec)";
224 signr = SIGSEGV;
225 }
226 }
227
228 do_unhandled_exception(trapnr, signr, exception_name, "do_reserved_inst", error_code, regs, current);
229}
230
231#else /* CONFIG_SH64_ID2815_WORKAROUND */
232
233/* If the workaround isn't needed, this is just a straightforward reserved
234 instruction */
235DO_ERROR(12, SIGILL, "reserved instruction", reserved_inst, current)
236
237#endif /* CONFIG_SH64_ID2815_WORKAROUND */
238
1da177e4
LT		 239/* Called with interrupts disabled */
240asmlinkage void do_exception_error(unsigned long ex, struct pt_regs *regs)
241{
866e6b9e 242 show_excp_regs(__func__, -1, -1, regs);
1da177e4
LT		 243 die_if_kernel("exception", regs, ex);
244}
245
246int do_unknown_trapa(unsigned long scId, struct pt_regs *regs)
247{
248 /* Syscall debug */
249 printk("System call ID error: [0x1#args:8 #syscall:16 0x%lx]\n", scId);
250
251 die_if_kernel("unknown trapa", regs, scId);
252
253 return -ENOSYS;
254}
255
1da177e4
LT		 256static void do_unhandled_exception(int trapnr, int signr, char *str, char *fn_name,
257 unsigned long error_code, struct pt_regs *regs, struct task_struct *tsk)
258{
259 show_excp_regs(fn_name, trapnr, signr, regs);
1da177e4
LT		 260
261 if (user_mode(regs))
262 force_sig(signr, tsk);
263
264 die_if_no_fixup(str, regs, error_code);
265}
266
db218b3d 267static int read_opcode(reg_size_t pc, insn_size_t *result_opcode, int from_user_mode)
1da177e4
LT		 268{
269 int get_user_error;
270 unsigned long aligned_pc;
db218b3d 271 insn_size_t opcode;
1da177e4
LT		 272
273 if ((pc & 3) == 1) {
274 /* SHmedia */
275 aligned_pc = pc & ~3;
276 if (from_user_mode) {
db218b3d 277 if (!access_ok(VERIFY_READ, aligned_pc, sizeof(insn_size_t))) {
1da177e4
LT		 278 get_user_error = -EFAULT;
279 } else {
db218b3d 280 get_user_error = __get_user(opcode, (insn_size_t *)aligned_pc);
1da177e4
LT		 281 *result_opcode = opcode;
282 }
283 return get_user_error;
284 } else {
285 /* If the fault was in the kernel, we can either read
286 * this directly, or if not, we fault.
287 */
db218b3d 288 *result_opcode = *(insn_size_t *)aligned_pc;
1da177e4
LT		 289 return 0;
290 }
291 } else if ((pc & 1) == 0) {
292 /* SHcompact */
293 /* TODO : provide handling for this. We don't really support
294 user-mode SHcompact yet, and for a kernel fault, this would
295 have to come from a module built for SHcompact. */
296 return -EFAULT;
297 } else {
298 /* misaligned */
299 return -EFAULT;
300 }
301}
302
303static int address_is_sign_extended(__u64 a)
304{
305 __u64 b;
306#if (NEFF == 32)
307 b = (__u64)(__s64)(__s32)(a & 0xffffffffUL);
308 return (b == a) ? 1 : 0;
309#else
310#error "Sign extend check only works for NEFF==32"
311#endif
312}
313
db218b3d 314/* return -1 for fault, 0 for OK */
1da177e4 315static int generate_and_check_address(struct pt_regs *regs,
db218b3d 316 insn_size_t opcode,
1da177e4
LT		 317 int displacement_not_indexed,
318 int width_shift,
319 __u64 *address)
320{
1da177e4
LT		 321 __u64 base_address, addr;
322 int basereg;
323
db218b3d
PM		 324 switch (1 << width_shift) {
325 case 1: inc_unaligned_byte_access(); break;
326 case 2: inc_unaligned_word_access(); break;
327 case 4: inc_unaligned_dword_access(); break;
328 case 8: inc_unaligned_multi_access(); break;
329 }
330
1da177e4
LT		 331 basereg = (opcode >> 20) & 0x3f;
332 base_address = regs->regs[basereg];
333 if (displacement_not_indexed) {
334 __s64 displacement;
335 displacement = (opcode >> 10) & 0x3ff;
336 displacement = ((displacement << 54) >> 54); /* sign extend */
337 addr = (__u64)((__s64)base_address + (displacement << width_shift));
338 } else {
339 __u64 offset;
340 int offsetreg;
341 offsetreg = (opcode >> 10) & 0x3f;
342 offset = regs->regs[offsetreg];
343 addr = base_address + offset;
344 }
345
346 /* Check sign extended */
db218b3d 347 if (!address_is_sign_extended(addr))
1da177e4 348 return -1;
1da177e4 349
1da177e4
LT		 350 /* Check accessible. For misaligned access in the kernel, assume the
351 address is always accessible (and if not, just fault when the
352 load/store gets done.) */
353 if (user_mode(regs)) {
db218b3d
PM		 354 inc_unaligned_user_access();
355
356 if (addr >= TASK_SIZE)
1da177e4 357 return -1;
db218b3d
PM		 358 } else
359 inc_unaligned_kernel_access();
1da177e4
LT		 360
361 *address = addr;
db218b3d
PM		 362
363 perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, addr);
364 unaligned_fixups_notify(current, opcode, regs);
365
1da177e4
LT		 366 return 0;
367}
368
1da177e4
LT		 369static void misaligned_kernel_word_load(__u64 address, int do_sign_extend, __u64 *result)
370{
371 unsigned short x;
372 unsigned char *p, *q;
373 p = (unsigned char *) (int) address;
374 q = (unsigned char *) &x;
375 q[0] = p[0];
376 q[1] = p[1];
377
378 if (do_sign_extend) {
379 *result = (__u64)(__s64) *(short *) &x;
380 } else {
381 *result = (__u64) x;
382 }
383}
384
385static void misaligned_kernel_word_store(__u64 address, __u64 value)
386{
387 unsigned short x;
388 unsigned char *p, *q;
389 p = (unsigned char *) (int) address;
390 q = (unsigned char *) &x;
391
392 x = (__u16) value;
393 p[0] = q[0];
394 p[1] = q[1];
395}
396
397static int misaligned_load(struct pt_regs *regs,
db218b3d 398 insn_size_t opcode,
1da177e4
LT		 399 int displacement_not_indexed,
400 int width_shift,
401 int do_sign_extend)
402{
403 /* Return -1 for a fault, 0 for OK */
404 int error;
405 int destreg;
406 __u64 address;
407
408 error = generate_and_check_address(regs, opcode,
409 displacement_not_indexed, width_shift, &address);
db218b3d 410 if (error < 0)
1da177e4 411 return error;
ace2dc7d 412
1da177e4 413 destreg = (opcode >> 4) & 0x3f;
1da177e4
LT		 414 if (user_mode(regs)) {
415 __u64 buffer;
416
417 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
418 return -1;
419 }
420
421 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
422 return -1; /* fault */
423 }
424 switch (width_shift) {
425 case 1:
426 if (do_sign_extend) {
427 regs->regs[destreg] = (__u64)(__s64) *(__s16 *) &buffer;
428 } else {
429 regs->regs[destreg] = (__u64) *(__u16 *) &buffer;
430 }
431 break;
432 case 2:
433 regs->regs[destreg] = (__u64)(__s64) *(__s32 *) &buffer;
434 break;
435 case 3:
436 regs->regs[destreg] = buffer;
437 break;
438 default:
439 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
440 width_shift, (unsigned long) regs->pc);
441 break;
442 }
c29418c2 443 } else {
1da177e4
LT		 444 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
445 __u64 lo, hi;
446
447 switch (width_shift) {
448 case 1:
449 misaligned_kernel_word_load(address, do_sign_extend, &regs->regs[destreg]);
450 break;
451 case 2:
452 asm ("ldlo.l %1, 0, %0" : "=r" (lo) : "r" (address));
453 asm ("ldhi.l %1, 3, %0" : "=r" (hi) : "r" (address));
454 regs->regs[destreg] = lo | hi;
455 break;
456 case 3:
457 asm ("ldlo.q %1, 0, %0" : "=r" (lo) : "r" (address));
458 asm ("ldhi.q %1, 7, %0" : "=r" (hi) : "r" (address));
459 regs->regs[destreg] = lo | hi;
460 break;
461
462 default:
463 printk("Unexpected width_shift %d in misaligned_load, PC=%08lx\n",
464 width_shift, (unsigned long) regs->pc);
465 break;
466 }
467 }
468
469 return 0;
1da177e4
LT		 470}
471
472static int misaligned_store(struct pt_regs *regs,
db218b3d 473 insn_size_t opcode,
1da177e4
LT		 474 int displacement_not_indexed,
475 int width_shift)
476{
477 /* Return -1 for a fault, 0 for OK */
478 int error;
479 int srcreg;
480 __u64 address;
481
482 error = generate_and_check_address(regs, opcode,
483 displacement_not_indexed, width_shift, &address);
db218b3d 484 if (error < 0)
1da177e4 485 return error;
ace2dc7d 486
1da177e4 487 srcreg = (opcode >> 4) & 0x3f;
1da177e4
LT		 488 if (user_mode(regs)) {
489 __u64 buffer;
490
491 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
492 return -1;
493 }
494
495 switch (width_shift) {
496 case 1:
497 *(__u16 *) &buffer = (__u16) regs->regs[srcreg];
498 break;
499 case 2:
500 *(__u32 *) &buffer = (__u32) regs->regs[srcreg];
501 break;
502 case 3:
503 buffer = regs->regs[srcreg];
504 break;
505 default:
506 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
507 width_shift, (unsigned long) regs->pc);
508 break;
509 }
510
511 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
512 return -1; /* fault */
513 }
c29418c2 514 } else {
1da177e4
LT		 515 /* kernel mode - we can take short cuts since if we fault, it's a genuine bug */
516 __u64 val = regs->regs[srcreg];
517
518 switch (width_shift) {
519 case 1:
520 misaligned_kernel_word_store(address, val);
521 break;
522 case 2:
523 asm ("stlo.l %1, 0, %0" : : "r" (val), "r" (address));
524 asm ("sthi.l %1, 3, %0" : : "r" (val), "r" (address));
525 break;
526 case 3:
527 asm ("stlo.q %1, 0, %0" : : "r" (val), "r" (address));
528 asm ("sthi.q %1, 7, %0" : : "r" (val), "r" (address));
529 break;
530
531 default:
532 printk("Unexpected width_shift %d in misaligned_store, PC=%08lx\n",
533 width_shift, (unsigned long) regs->pc);
534 break;
535 }
536 }
537
538 return 0;
1da177e4
LT		 539}
540
1da177e4
LT		 541/* Never need to fix up misaligned FPU accesses within the kernel since that's a real
542 error. */
543static int misaligned_fpu_load(struct pt_regs *regs,
db218b3d 544 insn_size_t opcode,
1da177e4
LT		 545 int displacement_not_indexed,
546 int width_shift,
547 int do_paired_load)
548{
549 /* Return -1 for a fault, 0 for OK */
550 int error;
551 int destreg;
552 __u64 address;
553
554 error = generate_and_check_address(regs, opcode,
555 displacement_not_indexed, width_shift, &address);
db218b3d 556 if (error < 0)
1da177e4 557 return error;
ace2dc7d 558
1da177e4
LT		 559 destreg = (opcode >> 4) & 0x3f;
560 if (user_mode(regs)) {
561 __u64 buffer;
562 __u32 buflo, bufhi;
563
564 if (!access_ok(VERIFY_READ, (unsigned long) address, 1UL<<width_shift)) {
565 return -1;
566 }
567
568 if (__copy_user(&buffer, (const void *)(int)address, (1 << width_shift)) > 0) {
569 return -1; /* fault */
570 }
571 /* 'current' may be the current owner of the FPU state, so
572 context switch the registers into memory so they can be
573 indexed by register number. */
574 if (last_task_used_math == current) {
256b22ca 575 enable_fpu();
61cc7b0a 576 save_fpu(current);
256b22ca 577 disable_fpu();
1da177e4
LT		 578 last_task_used_math = NULL;
579 regs->sr |= SR_FD;
580 }
581
582 buflo = *(__u32*) &buffer;
583 bufhi = *(1 + (__u32*) &buffer);
584
585 switch (width_shift) {
586 case 2:
3ef2932b 587 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
1da177e4
LT		 588 break;
589 case 3:
590 if (do_paired_load) {
3ef2932b
PM		 591 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
592 current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
1da177e4 593 } else {
f99cb7a4 594#if defined(CONFIG_CPU_LITTLE_ENDIAN)
3ef2932b
PM		 595 current->thread.xstate->hardfpu.fp_regs[destreg] = bufhi;
596 current->thread.xstate->hardfpu.fp_regs[destreg+1] = buflo;
1da177e4 597#else
3ef2932b
PM		 598 current->thread.xstate->hardfpu.fp_regs[destreg] = buflo;
599 current->thread.xstate->hardfpu.fp_regs[destreg+1] = bufhi;
1da177e4
LT		 600#endif
601 }
602 break;
603 default:
604 printk("Unexpected width_shift %d in misaligned_fpu_load, PC=%08lx\n",
605 width_shift, (unsigned long) regs->pc);
606 break;
607 }
608 return 0;
609 } else {
610 die ("Misaligned FPU load inside kernel", regs, 0);
611 return -1;
612 }
1da177e4
LT		 613}
614
615static int misaligned_fpu_store(struct pt_regs *regs,
db218b3d 616 insn_size_t opcode,
1da177e4
LT		 617 int displacement_not_indexed,
618 int width_shift,
619 int do_paired_load)
620{
621 /* Return -1 for a fault, 0 for OK */
622 int error;
623 int srcreg;
624 __u64 address;
625
626 error = generate_and_check_address(regs, opcode,
627 displacement_not_indexed, width_shift, &address);
db218b3d 628 if (error < 0)
1da177e4 629 return error;
ace2dc7d 630
1da177e4
LT		 631 srcreg = (opcode >> 4) & 0x3f;
632 if (user_mode(regs)) {
633 __u64 buffer;
634 /* Initialise these to NaNs. */
635 __u32 buflo=0xffffffffUL, bufhi=0xffffffffUL;
636
637 if (!access_ok(VERIFY_WRITE, (unsigned long) address, 1UL<<width_shift)) {
638 return -1;
639 }
640
641 /* 'current' may be the current owner of the FPU state, so
642 context switch the registers into memory so they can be
643 indexed by register number. */
644 if (last_task_used_math == current) {
256b22ca 645 enable_fpu();
61cc7b0a 646 save_fpu(current);
256b22ca 647 disable_fpu();
1da177e4
LT		 648 last_task_used_math = NULL;
649 regs->sr |= SR_FD;
650 }
651
652 switch (width_shift) {
653 case 2:
3ef2932b 654 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
1da177e4
LT		 655 break;
656 case 3:
657 if (do_paired_load) {
3ef2932b
PM		 658 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
659 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
1da177e4 660 } else {
f99cb7a4 661#if defined(CONFIG_CPU_LITTLE_ENDIAN)
3ef2932b
PM		 662 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg];
663 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
1da177e4 664#else
3ef2932b
PM		 665 buflo = current->thread.xstate->hardfpu.fp_regs[srcreg];
666 bufhi = current->thread.xstate->hardfpu.fp_regs[srcreg+1];
1da177e4
LT		 667#endif
668 }
669 break;
670 default:
671 printk("Unexpected width_shift %d in misaligned_fpu_store, PC=%08lx\n",
672 width_shift, (unsigned long) regs->pc);
673 break;
674 }
675
676 *(__u32*) &buffer = buflo;
677 *(1 + (__u32*) &buffer) = bufhi;
678 if (__copy_user((void *)(int)address, &buffer, (1 << width_shift)) > 0) {
679 return -1; /* fault */
680 }
681 return 0;
682 } else {
683 die ("Misaligned FPU load inside kernel", regs, 0);
684 return -1;
685 }
686}
1da177e4
LT		 687
688static int misaligned_fixup(struct pt_regs *regs)
689{
db218b3d 690 insn_size_t opcode;
1da177e4
LT		 691 int error;
692 int major, minor;
db218b3d 693 unsigned int user_action;
1da177e4 694
db218b3d
PM		 695 user_action = unaligned_user_action();
696 if (!(user_action & UM_FIXUP))
c29418c2 697 return -1;
1da177e4
LT		 698
699 error = read_opcode(regs->pc, &opcode, user_mode(regs));
700 if (error < 0) {
701 return error;
702 }
703 major = (opcode >> 26) & 0x3f;
704 minor = (opcode >> 16) & 0xf;
705
1da177e4
LT		 706 switch (major) {
707 case (0x84>>2): /* LD.W */
708 error = misaligned_load(regs, opcode, 1, 1, 1);
709 break;
710 case (0xb0>>2): /* LD.UW */
711 error = misaligned_load(regs, opcode, 1, 1, 0);
712 break;
713 case (0x88>>2): /* LD.L */
714 error = misaligned_load(regs, opcode, 1, 2, 1);
715 break;
716 case (0x8c>>2): /* LD.Q */
717 error = misaligned_load(regs, opcode, 1, 3, 0);
718 break;
719
720 case (0xa4>>2): /* ST.W */
721 error = misaligned_store(regs, opcode, 1, 1);
722 break;
723 case (0xa8>>2): /* ST.L */
724 error = misaligned_store(regs, opcode, 1, 2);
725 break;
726 case (0xac>>2): /* ST.Q */
727 error = misaligned_store(regs, opcode, 1, 3);
728 break;
729
730 case (0x40>>2): /* indexed loads */
731 switch (minor) {
732 case 0x1: /* LDX.W */
733 error = misaligned_load(regs, opcode, 0, 1, 1);
734 break;
735 case 0x5: /* LDX.UW */
736 error = misaligned_load(regs, opcode, 0, 1, 0);
737 break;
738 case 0x2: /* LDX.L */
739 error = misaligned_load(regs, opcode, 0, 2, 1);
740 break;
741 case 0x3: /* LDX.Q */
742 error = misaligned_load(regs, opcode, 0, 3, 0);
743 break;
744 default:
745 error = -1;
746 break;
747 }
748 break;
749
750 case (0x60>>2): /* indexed stores */
751 switch (minor) {
752 case 0x1: /* STX.W */
753 error = misaligned_store(regs, opcode, 0, 1);
754 break;
755 case 0x2: /* STX.L */
756 error = misaligned_store(regs, opcode, 0, 2);
757 break;
758 case 0x3: /* STX.Q */
759 error = misaligned_store(regs, opcode, 0, 3);
760 break;
761 default:
762 error = -1;
763 break;
764 }
765 break;
766
1da177e4
LT		 767 case (0x94>>2): /* FLD.S */
768 error = misaligned_fpu_load(regs, opcode, 1, 2, 0);
769 break;
770 case (0x98>>2): /* FLD.P */
771 error = misaligned_fpu_load(regs, opcode, 1, 3, 1);
772 break;
773 case (0x9c>>2): /* FLD.D */
774 error = misaligned_fpu_load(regs, opcode, 1, 3, 0);
775 break;
776 case (0x1c>>2): /* floating indexed loads */
777 switch (minor) {
778 case 0x8: /* FLDX.S */
779 error = misaligned_fpu_load(regs, opcode, 0, 2, 0);
780 break;
781 case 0xd: /* FLDX.P */
782 error = misaligned_fpu_load(regs, opcode, 0, 3, 1);
783 break;
784 case 0x9: /* FLDX.D */
785 error = misaligned_fpu_load(regs, opcode, 0, 3, 0);
786 break;
787 default:
788 error = -1;
789 break;
790 }
791 break;
792 case (0xb4>>2): /* FLD.S */
793 error = misaligned_fpu_store(regs, opcode, 1, 2, 0);
794 break;
795 case (0xb8>>2): /* FLD.P */
796 error = misaligned_fpu_store(regs, opcode, 1, 3, 1);
797 break;
798 case (0xbc>>2): /* FLD.D */
799 error = misaligned_fpu_store(regs, opcode, 1, 3, 0);
800 break;
801 case (0x3c>>2): /* floating indexed stores */
802 switch (minor) {
803 case 0x8: /* FSTX.S */
804 error = misaligned_fpu_store(regs, opcode, 0, 2, 0);
805 break;
806 case 0xd: /* FSTX.P */
807 error = misaligned_fpu_store(regs, opcode, 0, 3, 1);
808 break;
809 case 0x9: /* FSTX.D */
810 error = misaligned_fpu_store(regs, opcode, 0, 3, 0);
811 break;
812 default:
813 error = -1;
814 break;
815 }
816 break;
1da177e4
LT		 817
818 default:
819 /* Fault */
820 error = -1;
821 break;
822 }
823
824 if (error < 0) {
825 return error;
826 } else {
827 regs->pc += 4; /* Skip the instruction that's just been emulated */
828 return 0;
829 }
830
831}
832
1da177e4
LT		 833asmlinkage void do_debug_interrupt(unsigned long code, struct pt_regs *regs)
834{
835 u64 peek_real_address_q(u64 addr);
836 u64 poke_real_address_q(u64 addr, u64 val);
837 unsigned long long DM_EXP_CAUSE_PHY = 0x0c100010;
838 unsigned long long exp_cause;
839 /* It's not worth ioremapping the debug module registers for the amount
840 of access we make to them - just go direct to their physical
841 addresses. */
842 exp_cause = peek_real_address_q(DM_EXP_CAUSE_PHY);
843 if (exp_cause & ~4) {
844 printk("DM.EXP_CAUSE had unexpected bits set (=%08lx)\n",
845 (unsigned long)(exp_cause & 0xffffffff));
846 }
847 show_state();
848 /* Clear all DEBUGINT causes */
849 poke_real_address_q(DM_EXP_CAUSE_PHY, 0x0);
850}
dd2fdd26
PM		 851
852void __cpuinit per_cpu_trap_init(void)
853{
854 /* Nothing to do for now, VBR initialization later. */
855}
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