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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
f5e706ad SR |
2 | #ifndef __SPARC64_IO_H |
3 | #define __SPARC64_IO_H | |
4 | ||
5 | #include <linux/kernel.h> | |
6 | #include <linux/compiler.h> | |
7 | #include <linux/types.h> | |
8 | ||
9 | #include <asm/page.h> /* IO address mapping routines need this */ | |
f5e706ad | 10 | #include <asm/asi.h> |
a21a2fd4 | 11 | #include <asm-generic/pci_iomap.h> |
f5e706ad | 12 | |
f5e706ad SR |
13 | /* BIO layer definitions. */ |
14 | extern unsigned long kern_base, kern_size; | |
f5e706ad | 15 | |
add79d68 SR |
16 | /* __raw_{read,write}{b,w,l,q} uses direct access. |
17 | * Access the memory as big endian bypassing the cache | |
18 | * by using ASI_PHYS_BYPASS_EC_E | |
19 | */ | |
20 | #define __raw_readb __raw_readb | |
21 | static inline u8 __raw_readb(const volatile void __iomem *addr) | |
f5e706ad SR |
22 | { |
23 | u8 ret; | |
24 | ||
add79d68 | 25 | __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_raw_readb */" |
f5e706ad | 26 | : "=r" (ret) |
add79d68 | 27 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); |
f5e706ad SR |
28 | |
29 | return ret; | |
30 | } | |
31 | ||
add79d68 SR |
32 | #define __raw_readw __raw_readw |
33 | static inline u16 __raw_readw(const volatile void __iomem *addr) | |
f5e706ad SR |
34 | { |
35 | u16 ret; | |
36 | ||
add79d68 | 37 | __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_raw_readw */" |
f5e706ad | 38 | : "=r" (ret) |
add79d68 | 39 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); |
f5e706ad SR |
40 | |
41 | return ret; | |
42 | } | |
43 | ||
add79d68 SR |
44 | #define __raw_readl __raw_readl |
45 | static inline u32 __raw_readl(const volatile void __iomem *addr) | |
f5e706ad SR |
46 | { |
47 | u32 ret; | |
48 | ||
add79d68 | 49 | __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_raw_readl */" |
f5e706ad | 50 | : "=r" (ret) |
add79d68 | 51 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); |
f5e706ad SR |
52 | |
53 | return ret; | |
54 | } | |
55 | ||
add79d68 SR |
56 | #define __raw_readq __raw_readq |
57 | static inline u64 __raw_readq(const volatile void __iomem *addr) | |
f5e706ad | 58 | { |
add79d68 | 59 | u64 ret; |
f5e706ad | 60 | |
add79d68 SR |
61 | __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_raw_readq */" |
62 | : "=r" (ret) | |
63 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | |
f5e706ad | 64 | |
add79d68 | 65 | return ret; |
f5e706ad SR |
66 | } |
67 | ||
add79d68 SR |
68 | #define __raw_writeb __raw_writeb |
69 | static inline void __raw_writeb(u8 b, const volatile void __iomem *addr) | |
f5e706ad | 70 | { |
add79d68 SR |
71 | __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_raw_writeb */" |
72 | : /* no outputs */ | |
73 | : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | |
f5e706ad SR |
74 | } |
75 | ||
add79d68 SR |
76 | #define __raw_writew __raw_writew |
77 | static inline void __raw_writew(u16 w, const volatile void __iomem *addr) | |
f5e706ad | 78 | { |
add79d68 SR |
79 | __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_raw_writew */" |
80 | : /* no outputs */ | |
81 | : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | |
f5e706ad SR |
82 | } |
83 | ||
add79d68 SR |
84 | #define __raw_writel __raw_writel |
85 | static inline void __raw_writel(u32 l, const volatile void __iomem *addr) | |
f5e706ad | 86 | { |
add79d68 SR |
87 | __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_raw_writel */" |
88 | : /* no outputs */ | |
89 | : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | |
f5e706ad SR |
90 | } |
91 | ||
add79d68 SR |
92 | #define __raw_writeq __raw_writeq |
93 | static inline void __raw_writeq(u64 q, const volatile void __iomem *addr) | |
f5e706ad | 94 | { |
add79d68 SR |
95 | __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_raw_writeq */" |
96 | : /* no outputs */ | |
97 | : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E)); | |
f5e706ad SR |
98 | } |
99 | ||
add79d68 SR |
100 | /* Memory functions, same as I/O accesses on Ultra. |
101 | * Access memory as little endian bypassing | |
102 | * the cache by using ASI_PHYS_BYPASS_EC_E_L | |
103 | */ | |
79294d7e | 104 | #define readb readb |
7c3969c3 | 105 | #define readb_relaxed readb |
79294d7e | 106 | static inline u8 readb(const volatile void __iomem *addr) |
f5e706ad SR |
107 | { u8 ret; |
108 | ||
109 | __asm__ __volatile__("lduba\t[%1] %2, %0\t/* pci_readb */" | |
110 | : "=r" (ret) | |
111 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
112 | : "memory"); | |
113 | return ret; | |
114 | } | |
115 | ||
79294d7e | 116 | #define readw readw |
7c3969c3 | 117 | #define readw_relaxed readw |
79294d7e | 118 | static inline u16 readw(const volatile void __iomem *addr) |
f5e706ad SR |
119 | { u16 ret; |
120 | ||
121 | __asm__ __volatile__("lduha\t[%1] %2, %0\t/* pci_readw */" | |
122 | : "=r" (ret) | |
123 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
124 | : "memory"); | |
125 | ||
126 | return ret; | |
127 | } | |
128 | ||
79294d7e | 129 | #define readl readl |
7c3969c3 | 130 | #define readl_relaxed readl |
79294d7e | 131 | static inline u32 readl(const volatile void __iomem *addr) |
f5e706ad SR |
132 | { u32 ret; |
133 | ||
134 | __asm__ __volatile__("lduwa\t[%1] %2, %0\t/* pci_readl */" | |
135 | : "=r" (ret) | |
136 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
137 | : "memory"); | |
138 | ||
139 | return ret; | |
140 | } | |
141 | ||
79294d7e | 142 | #define readq readq |
1191ccb3 | 143 | #define readq_relaxed readq |
79294d7e | 144 | static inline u64 readq(const volatile void __iomem *addr) |
f5e706ad SR |
145 | { u64 ret; |
146 | ||
147 | __asm__ __volatile__("ldxa\t[%1] %2, %0\t/* pci_readq */" | |
148 | : "=r" (ret) | |
149 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
150 | : "memory"); | |
151 | ||
152 | return ret; | |
153 | } | |
154 | ||
79294d7e | 155 | #define writeb writeb |
7c3969c3 | 156 | #define writeb_relaxed writeb |
79294d7e | 157 | static inline void writeb(u8 b, volatile void __iomem *addr) |
f5e706ad SR |
158 | { |
159 | __asm__ __volatile__("stba\t%r0, [%1] %2\t/* pci_writeb */" | |
160 | : /* no outputs */ | |
161 | : "Jr" (b), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
162 | : "memory"); | |
163 | } | |
164 | ||
79294d7e | 165 | #define writew writew |
7c3969c3 | 166 | #define writew_relaxed writew |
79294d7e | 167 | static inline void writew(u16 w, volatile void __iomem *addr) |
f5e706ad SR |
168 | { |
169 | __asm__ __volatile__("stha\t%r0, [%1] %2\t/* pci_writew */" | |
170 | : /* no outputs */ | |
171 | : "Jr" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
172 | : "memory"); | |
173 | } | |
174 | ||
79294d7e | 175 | #define writel writel |
7c3969c3 | 176 | #define writel_relaxed writel |
79294d7e | 177 | static inline void writel(u32 l, volatile void __iomem *addr) |
f5e706ad SR |
178 | { |
179 | __asm__ __volatile__("stwa\t%r0, [%1] %2\t/* pci_writel */" | |
180 | : /* no outputs */ | |
181 | : "Jr" (l), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
182 | : "memory"); | |
183 | } | |
184 | ||
79294d7e | 185 | #define writeq writeq |
1191ccb3 | 186 | #define writeq_relaxed writeq |
79294d7e | 187 | static inline void writeq(u64 q, volatile void __iomem *addr) |
f5e706ad SR |
188 | { |
189 | __asm__ __volatile__("stxa\t%r0, [%1] %2\t/* pci_writeq */" | |
190 | : /* no outputs */ | |
191 | : "Jr" (q), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
192 | : "memory"); | |
193 | } | |
194 | ||
add79d68 SR |
195 | #define inb inb |
196 | static inline u8 inb(unsigned long addr) | |
f5e706ad | 197 | { |
453c9abd | 198 | return readb((volatile void __iomem *)addr); |
f5e706ad SR |
199 | } |
200 | ||
add79d68 SR |
201 | #define inw inw |
202 | static inline u16 inw(unsigned long addr) | |
f5e706ad | 203 | { |
453c9abd | 204 | return readw((volatile void __iomem *)addr); |
f5e706ad SR |
205 | } |
206 | ||
add79d68 SR |
207 | #define inl inl |
208 | static inline u32 inl(unsigned long addr) | |
f5e706ad | 209 | { |
453c9abd | 210 | return readl((volatile void __iomem *)addr); |
f5e706ad SR |
211 | } |
212 | ||
add79d68 SR |
213 | #define outb outb |
214 | static inline void outb(u8 b, unsigned long addr) | |
f5e706ad | 215 | { |
453c9abd | 216 | writeb(b, (volatile void __iomem *)addr); |
f5e706ad SR |
217 | } |
218 | ||
add79d68 SR |
219 | #define outw outw |
220 | static inline void outw(u16 w, unsigned long addr) | |
f5e706ad | 221 | { |
453c9abd | 222 | writew(w, (volatile void __iomem *)addr); |
f5e706ad SR |
223 | } |
224 | ||
add79d68 SR |
225 | #define outl outl |
226 | static inline void outl(u32 l, unsigned long addr) | |
f5e706ad | 227 | { |
453c9abd | 228 | writel(l, (volatile void __iomem *)addr); |
f5e706ad SR |
229 | } |
230 | ||
add79d68 SR |
231 | |
232 | #define inb_p(__addr) inb(__addr) | |
233 | #define outb_p(__b, __addr) outb(__b, __addr) | |
234 | #define inw_p(__addr) inw(__addr) | |
235 | #define outw_p(__w, __addr) outw(__w, __addr) | |
236 | #define inl_p(__addr) inl(__addr) | |
237 | #define outl_p(__l, __addr) outl(__l, __addr) | |
238 | ||
239 | void outsb(unsigned long, const void *, unsigned long); | |
240 | void outsw(unsigned long, const void *, unsigned long); | |
241 | void outsl(unsigned long, const void *, unsigned long); | |
242 | void insb(unsigned long, void *, unsigned long); | |
243 | void insw(unsigned long, void *, unsigned long); | |
244 | void insl(unsigned long, void *, unsigned long); | |
245 | ||
246 | static inline void ioread8_rep(void __iomem *port, void *buf, unsigned long count) | |
f5e706ad | 247 | { |
add79d68 SR |
248 | insb((unsigned long __force)port, buf, count); |
249 | } | |
250 | static inline void ioread16_rep(void __iomem *port, void *buf, unsigned long count) | |
251 | { | |
252 | insw((unsigned long __force)port, buf, count); | |
f5e706ad SR |
253 | } |
254 | ||
add79d68 | 255 | static inline void ioread32_rep(void __iomem *port, void *buf, unsigned long count) |
f5e706ad | 256 | { |
add79d68 SR |
257 | insl((unsigned long __force)port, buf, count); |
258 | } | |
259 | ||
260 | static inline void iowrite8_rep(void __iomem *port, const void *buf, unsigned long count) | |
261 | { | |
262 | outsb((unsigned long __force)port, buf, count); | |
f5e706ad SR |
263 | } |
264 | ||
add79d68 SR |
265 | static inline void iowrite16_rep(void __iomem *port, const void *buf, unsigned long count) |
266 | { | |
267 | outsw((unsigned long __force)port, buf, count); | |
268 | } | |
269 | ||
270 | static inline void iowrite32_rep(void __iomem *port, const void *buf, unsigned long count) | |
271 | { | |
272 | outsl((unsigned long __force)port, buf, count); | |
273 | } | |
274 | ||
f5e706ad SR |
275 | /* Valid I/O Space regions are anywhere, because each PCI bus supported |
276 | * can live in an arbitrary area of the physical address range. | |
277 | */ | |
278 | #define IO_SPACE_LIMIT 0xffffffffffffffffUL | |
279 | ||
280 | /* Now, SBUS variants, only difference from PCI is that we do | |
281 | * not use little-endian ASIs. | |
282 | */ | |
79294d7e | 283 | static inline u8 sbus_readb(const volatile void __iomem *addr) |
f5e706ad | 284 | { |
453c9abd | 285 | return __raw_readb(addr); |
f5e706ad SR |
286 | } |
287 | ||
79294d7e | 288 | static inline u16 sbus_readw(const volatile void __iomem *addr) |
f5e706ad | 289 | { |
453c9abd | 290 | return __raw_readw(addr); |
f5e706ad SR |
291 | } |
292 | ||
79294d7e | 293 | static inline u32 sbus_readl(const volatile void __iomem *addr) |
f5e706ad | 294 | { |
453c9abd | 295 | return __raw_readl(addr); |
f5e706ad SR |
296 | } |
297 | ||
79294d7e | 298 | static inline u64 sbus_readq(const volatile void __iomem *addr) |
f5e706ad | 299 | { |
453c9abd | 300 | return __raw_readq(addr); |
f5e706ad SR |
301 | } |
302 | ||
79294d7e | 303 | static inline void sbus_writeb(u8 b, volatile void __iomem *addr) |
f5e706ad | 304 | { |
453c9abd | 305 | __raw_writeb(b, addr); |
f5e706ad SR |
306 | } |
307 | ||
79294d7e | 308 | static inline void sbus_writew(u16 w, volatile void __iomem *addr) |
f5e706ad | 309 | { |
453c9abd | 310 | __raw_writew(w, addr); |
f5e706ad SR |
311 | } |
312 | ||
79294d7e | 313 | static inline void sbus_writel(u32 l, volatile void __iomem *addr) |
f5e706ad | 314 | { |
453c9abd | 315 | __raw_writel(l, addr); |
f5e706ad SR |
316 | } |
317 | ||
453c9abd | 318 | static inline void sbus_writeq(u64 q, volatile void __iomem *addr) |
f5e706ad | 319 | { |
453c9abd | 320 | __raw_writeq(q, addr); |
f5e706ad SR |
321 | } |
322 | ||
79294d7e | 323 | static inline void sbus_memset_io(volatile void __iomem *dst, int c, __kernel_size_t n) |
f5e706ad SR |
324 | { |
325 | while(n--) { | |
326 | sbus_writeb(c, dst); | |
327 | dst++; | |
328 | } | |
329 | } | |
330 | ||
79294d7e | 331 | static inline void memset_io(volatile void __iomem *dst, int c, __kernel_size_t n) |
f5e706ad SR |
332 | { |
333 | volatile void __iomem *d = dst; | |
334 | ||
335 | while (n--) { | |
336 | writeb(c, d); | |
337 | d++; | |
338 | } | |
339 | } | |
340 | ||
79294d7e SR |
341 | static inline void sbus_memcpy_fromio(void *dst, const volatile void __iomem *src, |
342 | __kernel_size_t n) | |
f11b478d JH |
343 | { |
344 | char *d = dst; | |
345 | ||
346 | while (n--) { | |
347 | char tmp = sbus_readb(src); | |
348 | *d++ = tmp; | |
349 | src++; | |
350 | } | |
351 | } | |
352 | ||
f11b478d | 353 | |
79294d7e SR |
354 | static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, |
355 | __kernel_size_t n) | |
f5e706ad SR |
356 | { |
357 | char *d = dst; | |
358 | ||
359 | while (n--) { | |
360 | char tmp = readb(src); | |
361 | *d++ = tmp; | |
362 | src++; | |
363 | } | |
364 | } | |
365 | ||
79294d7e SR |
366 | static inline void sbus_memcpy_toio(volatile void __iomem *dst, const void *src, |
367 | __kernel_size_t n) | |
f11b478d JH |
368 | { |
369 | const char *s = src; | |
370 | volatile void __iomem *d = dst; | |
371 | ||
372 | while (n--) { | |
373 | char tmp = *s++; | |
374 | sbus_writeb(tmp, d); | |
375 | d++; | |
376 | } | |
377 | } | |
378 | ||
79294d7e SR |
379 | static inline void memcpy_toio(volatile void __iomem *dst, const void *src, |
380 | __kernel_size_t n) | |
f5e706ad SR |
381 | { |
382 | const char *s = src; | |
383 | volatile void __iomem *d = dst; | |
384 | ||
385 | while (n--) { | |
386 | char tmp = *s++; | |
387 | writeb(tmp, d); | |
388 | d++; | |
389 | } | |
390 | } | |
391 | ||
f5e706ad SR |
392 | #define mmiowb() |
393 | ||
394 | #ifdef __KERNEL__ | |
395 | ||
396 | /* On sparc64 we have the whole physical IO address space accessible | |
397 | * using physically addressed loads and stores, so this does nothing. | |
398 | */ | |
399 | static inline void __iomem *ioremap(unsigned long offset, unsigned long size) | |
400 | { | |
401 | return (void __iomem *)offset; | |
402 | } | |
403 | ||
404 | #define ioremap_nocache(X,Y) ioremap((X),(Y)) | |
428695b8 | 405 | #define ioremap_wc(X,Y) ioremap((X),(Y)) |
556269c1 | 406 | #define ioremap_wt(X,Y) ioremap((X),(Y)) |
f5e706ad SR |
407 | |
408 | static inline void iounmap(volatile void __iomem *addr) | |
409 | { | |
410 | } | |
411 | ||
9555b47f RRD |
412 | #define ioread8 readb |
413 | #define ioread16 readw | |
414 | #define ioread16be __raw_readw | |
415 | #define ioread32 readl | |
416 | #define ioread32be __raw_readl | |
417 | #define iowrite8 writeb | |
418 | #define iowrite16 writew | |
419 | #define iowrite16be __raw_writew | |
420 | #define iowrite32 writel | |
421 | #define iowrite32be __raw_writel | |
f5e706ad SR |
422 | |
423 | /* Create a virtual mapping cookie for an IO port range */ | |
f05a6865 SR |
424 | void __iomem *ioport_map(unsigned long port, unsigned int nr); |
425 | void ioport_unmap(void __iomem *); | |
f5e706ad SR |
426 | |
427 | /* Create a virtual mapping cookie for a PCI BAR (memory or IO) */ | |
428 | struct pci_dev; | |
f05a6865 | 429 | void pci_iounmap(struct pci_dev *dev, void __iomem *); |
f5e706ad | 430 | |
63237eeb DM |
431 | static inline int sbus_can_dma_64bit(void) |
432 | { | |
433 | return 1; | |
434 | } | |
435 | static inline int sbus_can_burst64(void) | |
436 | { | |
437 | return 1; | |
438 | } | |
439 | struct device; | |
f05a6865 | 440 | void sbus_set_sbus64(struct device *, int); |
63237eeb | 441 | |
f5e706ad SR |
442 | /* |
443 | * Convert a physical pointer to a virtual kernel pointer for /dev/mem | |
444 | * access | |
445 | */ | |
446 | #define xlate_dev_mem_ptr(p) __va(p) | |
447 | ||
448 | /* | |
449 | * Convert a virtual cached pointer to an uncached pointer | |
450 | */ | |
451 | #define xlate_dev_kmem_ptr(p) p | |
452 | ||
453 | #endif | |
454 | ||
455 | #endif /* !(__SPARC64_IO_H) */ |