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Commit | Line | Data |
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f5e706ad SR |
1 | /* |
2 | * pgtable.h: SpitFire page table operations. | |
3 | * | |
4 | * Copyright 1996,1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
8 | #ifndef _SPARC64_PGTABLE_H | |
9 | #define _SPARC64_PGTABLE_H | |
10 | ||
11 | /* This file contains the functions and defines necessary to modify and use | |
12 | * the SpitFire page tables. | |
13 | */ | |
14 | ||
9849a569 | 15 | #include <asm-generic/5level-fixup.h> |
f5e706ad SR |
16 | #include <linux/compiler.h> |
17 | #include <linux/const.h> | |
18 | #include <asm/types.h> | |
19 | #include <asm/spitfire.h> | |
20 | #include <asm/asi.h> | |
f5e706ad SR |
21 | #include <asm/page.h> |
22 | #include <asm/processor.h> | |
23 | ||
24 | /* The kernel image occupies 0x4000000 to 0x6000000 (4MB --> 96MB). | |
25 | * The page copy blockops can use 0x6000000 to 0x8000000. | |
b18eb2d7 DM |
26 | * The 8K TSB is mapped in the 0x8000000 to 0x8400000 range. |
27 | * The 4M TSB is mapped in the 0x8400000 to 0x8800000 range. | |
f5e706ad SR |
28 | * The PROM resides in an area spanning 0xf0000000 to 0x100000000. |
29 | * The vmalloc area spans 0x100000000 to 0x200000000. | |
30 | * Since modules need to be in the lowest 32-bits of the address space, | |
31 | * we place them right before the OBP area from 0x10000000 to 0xf0000000. | |
32 | * There is a single static kernel PMD which maps from 0x0 to address | |
33 | * 0x400000000. | |
34 | */ | |
35 | #define TLBTEMP_BASE _AC(0x0000000006000000,UL) | |
b18eb2d7 DM |
36 | #define TSBMAP_8K_BASE _AC(0x0000000008000000,UL) |
37 | #define TSBMAP_4M_BASE _AC(0x0000000008400000,UL) | |
f5e706ad SR |
38 | #define MODULES_VADDR _AC(0x0000000010000000,UL) |
39 | #define MODULES_LEN _AC(0x00000000e0000000,UL) | |
40 | #define MODULES_END _AC(0x00000000f0000000,UL) | |
41 | #define LOW_OBP_ADDRESS _AC(0x00000000f0000000,UL) | |
42 | #define HI_OBP_ADDRESS _AC(0x0000000100000000,UL) | |
43 | #define VMALLOC_START _AC(0x0000000100000000,UL) | |
bb4e6e85 | 44 | #define VMEMMAP_BASE VMALLOC_END |
f5e706ad | 45 | |
f5e706ad SR |
46 | /* PMD_SHIFT determines the size of the area a second-level page |
47 | * table can map | |
48 | */ | |
37b3a8ff | 49 | #define PMD_SHIFT (PAGE_SHIFT + (PAGE_SHIFT-3)) |
f5e706ad SR |
50 | #define PMD_SIZE (_AC(1,UL) << PMD_SHIFT) |
51 | #define PMD_MASK (~(PMD_SIZE-1)) | |
2b77933c | 52 | #define PMD_BITS (PAGE_SHIFT - 3) |
f5e706ad | 53 | |
ac55c768 DM |
54 | /* PUD_SHIFT determines the size of the area a third-level page |
55 | * table can map | |
56 | */ | |
57 | #define PUD_SHIFT (PMD_SHIFT + PMD_BITS) | |
58 | #define PUD_SIZE (_AC(1,UL) << PUD_SHIFT) | |
59 | #define PUD_MASK (~(PUD_SIZE-1)) | |
60 | #define PUD_BITS (PAGE_SHIFT - 3) | |
61 | ||
62 | /* PGDIR_SHIFT determines what a fourth-level page table entry can map */ | |
63 | #define PGDIR_SHIFT (PUD_SHIFT + PUD_BITS) | |
f5e706ad SR |
64 | #define PGDIR_SIZE (_AC(1,UL) << PGDIR_SHIFT) |
65 | #define PGDIR_MASK (~(PGDIR_SIZE-1)) | |
2b77933c | 66 | #define PGDIR_BITS (PAGE_SHIFT - 3) |
f5e706ad | 67 | |
7c0fa0f2 DM |
68 | #if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS) |
69 | #error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support | |
70 | #endif | |
71 | ||
ac55c768 | 72 | #if (PGDIR_SHIFT + PGDIR_BITS) != 53 |
56a70b8c DM |
73 | #error Page table parameters do not cover virtual address space properly. |
74 | #endif | |
75 | ||
9e695d2e DM |
76 | #if (PMD_SHIFT != HPAGE_SHIFT) |
77 | #error PMD_SHIFT must equal HPAGE_SHIFT for transparent huge pages. | |
78 | #endif | |
79 | ||
f5e706ad SR |
80 | #ifndef __ASSEMBLY__ |
81 | ||
bb4e6e85 DM |
82 | extern unsigned long VMALLOC_END; |
83 | ||
84 | #define vmemmap ((struct page *)VMEMMAP_BASE) | |
85 | ||
f5e706ad SR |
86 | #include <linux/sched.h> |
87 | ||
0dd5b7b0 | 88 | bool kern_addr_valid(unsigned long addr); |
26cf4325 | 89 | |
f5e706ad | 90 | /* Entries per page directory level. */ |
37b3a8ff | 91 | #define PTRS_PER_PTE (1UL << (PAGE_SHIFT-3)) |
f5e706ad | 92 | #define PTRS_PER_PMD (1UL << PMD_BITS) |
ac55c768 | 93 | #define PTRS_PER_PUD (1UL << PUD_BITS) |
f5e706ad SR |
94 | #define PTRS_PER_PGD (1UL << PGDIR_BITS) |
95 | ||
96 | /* Kernel has a separate 44bit address space. */ | |
d016bf7e | 97 | #define FIRST_USER_ADDRESS 0UL |
f5e706ad | 98 | |
fe866433 DM |
99 | #define pmd_ERROR(e) \ |
100 | pr_err("%s:%d: bad pmd %p(%016lx) seen at (%pS)\n", \ | |
101 | __FILE__, __LINE__, &(e), pmd_val(e), __builtin_return_address(0)) | |
ac55c768 DM |
102 | #define pud_ERROR(e) \ |
103 | pr_err("%s:%d: bad pud %p(%016lx) seen at (%pS)\n", \ | |
104 | __FILE__, __LINE__, &(e), pud_val(e), __builtin_return_address(0)) | |
fe866433 DM |
105 | #define pgd_ERROR(e) \ |
106 | pr_err("%s:%d: bad pgd %p(%016lx) seen at (%pS)\n", \ | |
107 | __FILE__, __LINE__, &(e), pgd_val(e), __builtin_return_address(0)) | |
f5e706ad SR |
108 | |
109 | #endif /* !(__ASSEMBLY__) */ | |
110 | ||
111 | /* PTE bits which are the same in SUN4U and SUN4V format. */ | |
112 | #define _PAGE_VALID _AC(0x8000000000000000,UL) /* Valid TTE */ | |
113 | #define _PAGE_R _AC(0x8000000000000000,UL) /* Keep ref bit uptodate*/ | |
683d2fa6 | 114 | #define _PAGE_SPECIAL _AC(0x0200000000000000,UL) /* Special page */ |
a7b9403f | 115 | #define _PAGE_PMD_HUGE _AC(0x0100000000000000,UL) /* Huge page */ |
0dd5b7b0 | 116 | #define _PAGE_PUD_HUGE _PAGE_PMD_HUGE |
683d2fa6 DM |
117 | |
118 | /* Advertise support for _PAGE_SPECIAL */ | |
119 | #define __HAVE_ARCH_PTE_SPECIAL | |
f5e706ad SR |
120 | |
121 | /* SUN4U pte bits... */ | |
122 | #define _PAGE_SZ4MB_4U _AC(0x6000000000000000,UL) /* 4MB Page */ | |
123 | #define _PAGE_SZ512K_4U _AC(0x4000000000000000,UL) /* 512K Page */ | |
124 | #define _PAGE_SZ64K_4U _AC(0x2000000000000000,UL) /* 64K Page */ | |
125 | #define _PAGE_SZ8K_4U _AC(0x0000000000000000,UL) /* 8K Page */ | |
126 | #define _PAGE_NFO_4U _AC(0x1000000000000000,UL) /* No Fault Only */ | |
127 | #define _PAGE_IE_4U _AC(0x0800000000000000,UL) /* Invert Endianness */ | |
128 | #define _PAGE_SOFT2_4U _AC(0x07FC000000000000,UL) /* Software bits, set 2 */ | |
683d2fa6 | 129 | #define _PAGE_SPECIAL_4U _AC(0x0200000000000000,UL) /* Special page */ |
a7b9403f | 130 | #define _PAGE_PMD_HUGE_4U _AC(0x0100000000000000,UL) /* Huge page */ |
f5e706ad SR |
131 | #define _PAGE_RES1_4U _AC(0x0002000000000000,UL) /* Reserved */ |
132 | #define _PAGE_SZ32MB_4U _AC(0x0001000000000000,UL) /* (Panther) 32MB page */ | |
133 | #define _PAGE_SZ256MB_4U _AC(0x2001000000000000,UL) /* (Panther) 256MB page */ | |
134 | #define _PAGE_SZALL_4U _AC(0x6001000000000000,UL) /* All pgsz bits */ | |
135 | #define _PAGE_SN_4U _AC(0x0000800000000000,UL) /* (Cheetah) Snoop */ | |
136 | #define _PAGE_RES2_4U _AC(0x0000780000000000,UL) /* Reserved */ | |
137 | #define _PAGE_PADDR_4U _AC(0x000007FFFFFFE000,UL) /* (Cheetah) pa[42:13] */ | |
138 | #define _PAGE_SOFT_4U _AC(0x0000000000001F80,UL) /* Software bits: */ | |
139 | #define _PAGE_EXEC_4U _AC(0x0000000000001000,UL) /* Executable SW bit */ | |
140 | #define _PAGE_MODIFIED_4U _AC(0x0000000000000800,UL) /* Modified (dirty) */ | |
f5e706ad SR |
141 | #define _PAGE_ACCESSED_4U _AC(0x0000000000000400,UL) /* Accessed (ref'd) */ |
142 | #define _PAGE_READ_4U _AC(0x0000000000000200,UL) /* Readable SW Bit */ | |
143 | #define _PAGE_WRITE_4U _AC(0x0000000000000100,UL) /* Writable SW Bit */ | |
144 | #define _PAGE_PRESENT_4U _AC(0x0000000000000080,UL) /* Present */ | |
145 | #define _PAGE_L_4U _AC(0x0000000000000040,UL) /* Locked TTE */ | |
146 | #define _PAGE_CP_4U _AC(0x0000000000000020,UL) /* Cacheable in P-Cache */ | |
147 | #define _PAGE_CV_4U _AC(0x0000000000000010,UL) /* Cacheable in V-Cache */ | |
148 | #define _PAGE_E_4U _AC(0x0000000000000008,UL) /* side-Effect */ | |
149 | #define _PAGE_P_4U _AC(0x0000000000000004,UL) /* Privileged Page */ | |
150 | #define _PAGE_W_4U _AC(0x0000000000000002,UL) /* Writable */ | |
151 | ||
152 | /* SUN4V pte bits... */ | |
153 | #define _PAGE_NFO_4V _AC(0x4000000000000000,UL) /* No Fault Only */ | |
154 | #define _PAGE_SOFT2_4V _AC(0x3F00000000000000,UL) /* Software bits, set 2 */ | |
155 | #define _PAGE_MODIFIED_4V _AC(0x2000000000000000,UL) /* Modified (dirty) */ | |
156 | #define _PAGE_ACCESSED_4V _AC(0x1000000000000000,UL) /* Accessed (ref'd) */ | |
157 | #define _PAGE_READ_4V _AC(0x0800000000000000,UL) /* Readable SW Bit */ | |
158 | #define _PAGE_WRITE_4V _AC(0x0400000000000000,UL) /* Writable SW Bit */ | |
683d2fa6 | 159 | #define _PAGE_SPECIAL_4V _AC(0x0200000000000000,UL) /* Special page */ |
a7b9403f | 160 | #define _PAGE_PMD_HUGE_4V _AC(0x0100000000000000,UL) /* Huge page */ |
f5e706ad SR |
161 | #define _PAGE_PADDR_4V _AC(0x00FFFFFFFFFFE000,UL) /* paddr[55:13] */ |
162 | #define _PAGE_IE_4V _AC(0x0000000000001000,UL) /* Invert Endianness */ | |
163 | #define _PAGE_E_4V _AC(0x0000000000000800,UL) /* side-Effect */ | |
164 | #define _PAGE_CP_4V _AC(0x0000000000000400,UL) /* Cacheable in P-Cache */ | |
165 | #define _PAGE_CV_4V _AC(0x0000000000000200,UL) /* Cacheable in V-Cache */ | |
166 | #define _PAGE_P_4V _AC(0x0000000000000100,UL) /* Privileged Page */ | |
167 | #define _PAGE_EXEC_4V _AC(0x0000000000000080,UL) /* Executable Page */ | |
168 | #define _PAGE_W_4V _AC(0x0000000000000040,UL) /* Writable */ | |
169 | #define _PAGE_SOFT_4V _AC(0x0000000000000030,UL) /* Software bits */ | |
f5e706ad SR |
170 | #define _PAGE_PRESENT_4V _AC(0x0000000000000010,UL) /* Present */ |
171 | #define _PAGE_RESV_4V _AC(0x0000000000000008,UL) /* Reserved */ | |
172 | #define _PAGE_SZ16GB_4V _AC(0x0000000000000007,UL) /* 16GB Page */ | |
173 | #define _PAGE_SZ2GB_4V _AC(0x0000000000000006,UL) /* 2GB Page */ | |
174 | #define _PAGE_SZ256MB_4V _AC(0x0000000000000005,UL) /* 256MB Page */ | |
175 | #define _PAGE_SZ32MB_4V _AC(0x0000000000000004,UL) /* 32MB Page */ | |
176 | #define _PAGE_SZ4MB_4V _AC(0x0000000000000003,UL) /* 4MB Page */ | |
177 | #define _PAGE_SZ512K_4V _AC(0x0000000000000002,UL) /* 512K Page */ | |
178 | #define _PAGE_SZ64K_4V _AC(0x0000000000000001,UL) /* 64K Page */ | |
179 | #define _PAGE_SZ8K_4V _AC(0x0000000000000000,UL) /* 8K Page */ | |
180 | #define _PAGE_SZALL_4V _AC(0x0000000000000007,UL) /* All pgsz bits */ | |
181 | ||
f5e706ad SR |
182 | #define _PAGE_SZBITS_4U _PAGE_SZ8K_4U |
183 | #define _PAGE_SZBITS_4V _PAGE_SZ8K_4V | |
15b9350a | 184 | |
37b3a8ff DM |
185 | #if REAL_HPAGE_SHIFT != 22 |
186 | #error REAL_HPAGE_SHIFT and _PAGE_SZHUGE_foo must match up | |
187 | #endif | |
188 | ||
f5e706ad SR |
189 | #define _PAGE_SZHUGE_4U _PAGE_SZ4MB_4U |
190 | #define _PAGE_SZHUGE_4V _PAGE_SZ4MB_4V | |
f5e706ad SR |
191 | |
192 | /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */ | |
193 | #define __P000 __pgprot(0) | |
194 | #define __P001 __pgprot(0) | |
195 | #define __P010 __pgprot(0) | |
196 | #define __P011 __pgprot(0) | |
197 | #define __P100 __pgprot(0) | |
198 | #define __P101 __pgprot(0) | |
199 | #define __P110 __pgprot(0) | |
200 | #define __P111 __pgprot(0) | |
201 | ||
202 | #define __S000 __pgprot(0) | |
203 | #define __S001 __pgprot(0) | |
204 | #define __S010 __pgprot(0) | |
205 | #define __S011 __pgprot(0) | |
206 | #define __S100 __pgprot(0) | |
207 | #define __S101 __pgprot(0) | |
208 | #define __S110 __pgprot(0) | |
209 | #define __S111 __pgprot(0) | |
210 | ||
211 | #ifndef __ASSEMBLY__ | |
212 | ||
f05a6865 | 213 | pte_t mk_pte_io(unsigned long, pgprot_t, int, unsigned long); |
f5e706ad | 214 | |
f05a6865 | 215 | unsigned long pte_sz_bits(unsigned long size); |
f5e706ad SR |
216 | |
217 | extern pgprot_t PAGE_KERNEL; | |
218 | extern pgprot_t PAGE_KERNEL_LOCKED; | |
219 | extern pgprot_t PAGE_COPY; | |
220 | extern pgprot_t PAGE_SHARED; | |
221 | ||
08f80073 | 222 | /* XXX This ugliness is for the atyfb driver's sparc mmap() support. XXX */ |
f5e706ad SR |
223 | extern unsigned long _PAGE_IE; |
224 | extern unsigned long _PAGE_E; | |
225 | extern unsigned long _PAGE_CACHE; | |
226 | ||
227 | extern unsigned long pg_iobits; | |
228 | extern unsigned long _PAGE_ALL_SZ_BITS; | |
f5e706ad SR |
229 | |
230 | extern struct page *mem_map_zero; | |
231 | #define ZERO_PAGE(vaddr) (mem_map_zero) | |
232 | ||
233 | /* PFNs are real physical page numbers. However, mem_map only begins to record | |
234 | * per-page information starting at pfn_base. This is to handle systems where | |
235 | * the first physical page in the machine is at some huge physical address, | |
236 | * such as 4GB. This is common on a partitioned E10000, for example. | |
237 | */ | |
238 | static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) | |
239 | { | |
240 | unsigned long paddr = pfn << PAGE_SHIFT; | |
15b9350a DM |
241 | |
242 | BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); | |
243 | return __pte(paddr | pgprot_val(prot)); | |
f5e706ad SR |
244 | } |
245 | #define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) | |
246 | ||
9e695d2e | 247 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
a7b9403f | 248 | static inline pmd_t pfn_pmd(unsigned long page_nr, pgprot_t pgprot) |
9e695d2e | 249 | { |
a7b9403f DM |
250 | pte_t pte = pfn_pte(page_nr, pgprot); |
251 | ||
252 | return __pmd(pte_val(pte)); | |
9e695d2e | 253 | } |
a7b9403f | 254 | #define mk_pmd(page, pgprot) pfn_pmd(page_to_pfn(page), (pgprot)) |
9e695d2e DM |
255 | #endif |
256 | ||
f5e706ad SR |
257 | /* This one can be done with two shifts. */ |
258 | static inline unsigned long pte_pfn(pte_t pte) | |
259 | { | |
260 | unsigned long ret; | |
261 | ||
262 | __asm__ __volatile__( | |
263 | "\n661: sllx %1, %2, %0\n" | |
264 | " srlx %0, %3, %0\n" | |
265 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
266 | " .word 661b\n" | |
267 | " sllx %1, %4, %0\n" | |
268 | " srlx %0, %5, %0\n" | |
269 | " .previous\n" | |
270 | : "=r" (ret) | |
271 | : "r" (pte_val(pte)), | |
272 | "i" (21), "i" (21 + PAGE_SHIFT), | |
273 | "i" (8), "i" (8 + PAGE_SHIFT)); | |
274 | ||
275 | return ret; | |
276 | } | |
277 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | |
278 | ||
279 | static inline pte_t pte_modify(pte_t pte, pgprot_t prot) | |
280 | { | |
281 | unsigned long mask, tmp; | |
282 | ||
eaf85da8 DM |
283 | /* SUN4U: 0x630107ffffffec38 (negated == 0x9cfef800000013c7) |
284 | * SUN4V: 0x33ffffffffffee07 (negated == 0xcc000000000011f8) | |
f5e706ad SR |
285 | * |
286 | * Even if we use negation tricks the result is still a 6 | |
287 | * instruction sequence, so don't try to play fancy and just | |
288 | * do the most straightforward implementation. | |
289 | * | |
290 | * Note: We encode this into 3 sun4v 2-insn patch sequences. | |
291 | */ | |
292 | ||
15b9350a | 293 | BUILD_BUG_ON(_PAGE_SZBITS_4U != 0UL || _PAGE_SZBITS_4V != 0UL); |
f5e706ad SR |
294 | __asm__ __volatile__( |
295 | "\n661: sethi %%uhi(%2), %1\n" | |
296 | " sethi %%hi(%2), %0\n" | |
297 | "\n662: or %1, %%ulo(%2), %1\n" | |
298 | " or %0, %%lo(%2), %0\n" | |
299 | "\n663: sllx %1, 32, %1\n" | |
300 | " or %0, %1, %0\n" | |
301 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
302 | " .word 661b\n" | |
303 | " sethi %%uhi(%3), %1\n" | |
304 | " sethi %%hi(%3), %0\n" | |
305 | " .word 662b\n" | |
306 | " or %1, %%ulo(%3), %1\n" | |
307 | " or %0, %%lo(%3), %0\n" | |
308 | " .word 663b\n" | |
309 | " sllx %1, 32, %1\n" | |
310 | " or %0, %1, %0\n" | |
311 | " .previous\n" | |
494e5b6f KA |
312 | " .section .sun_m7_2insn_patch, \"ax\"\n" |
313 | " .word 661b\n" | |
314 | " sethi %%uhi(%4), %1\n" | |
315 | " sethi %%hi(%4), %0\n" | |
316 | " .word 662b\n" | |
317 | " or %1, %%ulo(%4), %1\n" | |
318 | " or %0, %%lo(%4), %0\n" | |
319 | " .word 663b\n" | |
320 | " sllx %1, 32, %1\n" | |
321 | " or %0, %1, %0\n" | |
322 | " .previous\n" | |
f5e706ad SR |
323 | : "=r" (mask), "=r" (tmp) |
324 | : "i" (_PAGE_PADDR_4U | _PAGE_MODIFIED_4U | _PAGE_ACCESSED_4U | | |
eaf85da8 | 325 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_E_4U | |
a7b9403f | 326 | _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4U), |
f5e706ad | 327 | "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | |
eaf85da8 | 328 | _PAGE_CP_4V | _PAGE_CV_4V | _PAGE_E_4V | |
494e5b6f KA |
329 | _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V), |
330 | "i" (_PAGE_PADDR_4V | _PAGE_MODIFIED_4V | _PAGE_ACCESSED_4V | | |
331 | _PAGE_CP_4V | _PAGE_E_4V | | |
a7b9403f | 332 | _PAGE_SPECIAL | _PAGE_PMD_HUGE | _PAGE_SZALL_4V)); |
f5e706ad SR |
333 | |
334 | return __pte((pte_val(pte) & mask) | (pgprot_val(prot) & ~mask)); | |
335 | } | |
336 | ||
a7b9403f DM |
337 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
338 | static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot) | |
339 | { | |
340 | pte_t pte = __pte(pmd_val(pmd)); | |
341 | ||
342 | pte = pte_modify(pte, newprot); | |
343 | ||
344 | return __pmd(pte_val(pte)); | |
345 | } | |
346 | #endif | |
347 | ||
f5e706ad SR |
348 | static inline pgprot_t pgprot_noncached(pgprot_t prot) |
349 | { | |
350 | unsigned long val = pgprot_val(prot); | |
351 | ||
352 | __asm__ __volatile__( | |
353 | "\n661: andn %0, %2, %0\n" | |
354 | " or %0, %3, %0\n" | |
355 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
356 | " .word 661b\n" | |
357 | " andn %0, %4, %0\n" | |
358 | " or %0, %5, %0\n" | |
359 | " .previous\n" | |
494e5b6f KA |
360 | " .section .sun_m7_2insn_patch, \"ax\"\n" |
361 | " .word 661b\n" | |
362 | " andn %0, %6, %0\n" | |
363 | " or %0, %5, %0\n" | |
364 | " .previous\n" | |
f5e706ad SR |
365 | : "=r" (val) |
366 | : "0" (val), "i" (_PAGE_CP_4U | _PAGE_CV_4U), "i" (_PAGE_E_4U), | |
494e5b6f KA |
367 | "i" (_PAGE_CP_4V | _PAGE_CV_4V), "i" (_PAGE_E_4V), |
368 | "i" (_PAGE_CP_4V)); | |
f5e706ad SR |
369 | |
370 | return __pgprot(val); | |
371 | } | |
372 | /* Various pieces of code check for platform support by ifdef testing | |
373 | * on "pgprot_noncached". That's broken and should be fixed, but for | |
374 | * now... | |
375 | */ | |
376 | #define pgprot_noncached pgprot_noncached | |
377 | ||
a7b9403f | 378 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
c7d9f77d NG |
379 | extern pte_t arch_make_huge_pte(pte_t entry, struct vm_area_struct *vma, |
380 | struct page *page, int writable); | |
381 | #define arch_make_huge_pte arch_make_huge_pte | |
382 | static inline unsigned long __pte_default_huge_mask(void) | |
f5e706ad SR |
383 | { |
384 | unsigned long mask; | |
385 | ||
386 | __asm__ __volatile__( | |
387 | "\n661: sethi %%uhi(%1), %0\n" | |
388 | " sllx %0, 32, %0\n" | |
389 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
390 | " .word 661b\n" | |
391 | " mov %2, %0\n" | |
392 | " nop\n" | |
393 | " .previous\n" | |
394 | : "=r" (mask) | |
395 | : "i" (_PAGE_SZHUGE_4U), "i" (_PAGE_SZHUGE_4V)); | |
396 | ||
24e49ee3 NG |
397 | return mask; |
398 | } | |
399 | ||
400 | static inline pte_t pte_mkhuge(pte_t pte) | |
401 | { | |
c7d9f77d | 402 | return __pte(pte_val(pte) | __pte_default_huge_mask()); |
24e49ee3 NG |
403 | } |
404 | ||
c7d9f77d | 405 | static inline bool is_default_hugetlb_pte(pte_t pte) |
24e49ee3 | 406 | { |
c7d9f77d NG |
407 | unsigned long mask = __pte_default_huge_mask(); |
408 | ||
409 | return (pte_val(pte) & mask) == mask; | |
f5e706ad | 410 | } |
24e49ee3 | 411 | |
7bc3777c NG |
412 | static inline bool is_hugetlb_pmd(pmd_t pmd) |
413 | { | |
414 | return !!(pmd_val(pmd) & _PAGE_PMD_HUGE); | |
415 | } | |
416 | ||
a7b9403f DM |
417 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
418 | static inline pmd_t pmd_mkhuge(pmd_t pmd) | |
419 | { | |
420 | pte_t pte = __pte(pmd_val(pmd)); | |
421 | ||
422 | pte = pte_mkhuge(pte); | |
423 | pte_val(pte) |= _PAGE_PMD_HUGE; | |
424 | ||
425 | return __pmd(pte_val(pte)); | |
426 | } | |
427 | #endif | |
24e49ee3 NG |
428 | #else |
429 | static inline bool is_hugetlb_pte(pte_t pte) | |
430 | { | |
431 | return false; | |
432 | } | |
f5e706ad SR |
433 | #endif |
434 | ||
435 | static inline pte_t pte_mkdirty(pte_t pte) | |
436 | { | |
437 | unsigned long val = pte_val(pte), tmp; | |
438 | ||
439 | __asm__ __volatile__( | |
440 | "\n661: or %0, %3, %0\n" | |
441 | " nop\n" | |
442 | "\n662: nop\n" | |
443 | " nop\n" | |
444 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
445 | " .word 661b\n" | |
446 | " sethi %%uhi(%4), %1\n" | |
447 | " sllx %1, 32, %1\n" | |
448 | " .word 662b\n" | |
449 | " or %1, %%lo(%4), %1\n" | |
450 | " or %0, %1, %0\n" | |
451 | " .previous\n" | |
452 | : "=r" (val), "=r" (tmp) | |
453 | : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), | |
454 | "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); | |
455 | ||
456 | return __pte(val); | |
457 | } | |
458 | ||
459 | static inline pte_t pte_mkclean(pte_t pte) | |
460 | { | |
461 | unsigned long val = pte_val(pte), tmp; | |
462 | ||
463 | __asm__ __volatile__( | |
464 | "\n661: andn %0, %3, %0\n" | |
465 | " nop\n" | |
466 | "\n662: nop\n" | |
467 | " nop\n" | |
468 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
469 | " .word 661b\n" | |
470 | " sethi %%uhi(%4), %1\n" | |
471 | " sllx %1, 32, %1\n" | |
472 | " .word 662b\n" | |
473 | " or %1, %%lo(%4), %1\n" | |
474 | " andn %0, %1, %0\n" | |
475 | " .previous\n" | |
476 | : "=r" (val), "=r" (tmp) | |
477 | : "0" (val), "i" (_PAGE_MODIFIED_4U | _PAGE_W_4U), | |
478 | "i" (_PAGE_MODIFIED_4V | _PAGE_W_4V)); | |
479 | ||
480 | return __pte(val); | |
481 | } | |
482 | ||
483 | static inline pte_t pte_mkwrite(pte_t pte) | |
484 | { | |
485 | unsigned long val = pte_val(pte), mask; | |
486 | ||
487 | __asm__ __volatile__( | |
488 | "\n661: mov %1, %0\n" | |
489 | " nop\n" | |
490 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
491 | " .word 661b\n" | |
492 | " sethi %%uhi(%2), %0\n" | |
493 | " sllx %0, 32, %0\n" | |
494 | " .previous\n" | |
495 | : "=r" (mask) | |
496 | : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); | |
497 | ||
498 | return __pte(val | mask); | |
499 | } | |
500 | ||
501 | static inline pte_t pte_wrprotect(pte_t pte) | |
502 | { | |
503 | unsigned long val = pte_val(pte), tmp; | |
504 | ||
505 | __asm__ __volatile__( | |
506 | "\n661: andn %0, %3, %0\n" | |
507 | " nop\n" | |
508 | "\n662: nop\n" | |
509 | " nop\n" | |
510 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
511 | " .word 661b\n" | |
512 | " sethi %%uhi(%4), %1\n" | |
513 | " sllx %1, 32, %1\n" | |
514 | " .word 662b\n" | |
515 | " or %1, %%lo(%4), %1\n" | |
516 | " andn %0, %1, %0\n" | |
517 | " .previous\n" | |
518 | : "=r" (val), "=r" (tmp) | |
519 | : "0" (val), "i" (_PAGE_WRITE_4U | _PAGE_W_4U), | |
520 | "i" (_PAGE_WRITE_4V | _PAGE_W_4V)); | |
521 | ||
522 | return __pte(val); | |
523 | } | |
524 | ||
525 | static inline pte_t pte_mkold(pte_t pte) | |
526 | { | |
527 | unsigned long mask; | |
528 | ||
529 | __asm__ __volatile__( | |
530 | "\n661: mov %1, %0\n" | |
531 | " nop\n" | |
532 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
533 | " .word 661b\n" | |
534 | " sethi %%uhi(%2), %0\n" | |
535 | " sllx %0, 32, %0\n" | |
536 | " .previous\n" | |
537 | : "=r" (mask) | |
538 | : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); | |
539 | ||
540 | mask |= _PAGE_R; | |
541 | ||
542 | return __pte(pte_val(pte) & ~mask); | |
543 | } | |
544 | ||
545 | static inline pte_t pte_mkyoung(pte_t pte) | |
546 | { | |
547 | unsigned long mask; | |
548 | ||
549 | __asm__ __volatile__( | |
550 | "\n661: mov %1, %0\n" | |
551 | " nop\n" | |
552 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
553 | " .word 661b\n" | |
554 | " sethi %%uhi(%2), %0\n" | |
555 | " sllx %0, 32, %0\n" | |
556 | " .previous\n" | |
557 | : "=r" (mask) | |
558 | : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); | |
559 | ||
560 | mask |= _PAGE_R; | |
561 | ||
562 | return __pte(pte_val(pte) | mask); | |
563 | } | |
564 | ||
565 | static inline pte_t pte_mkspecial(pte_t pte) | |
566 | { | |
683d2fa6 | 567 | pte_val(pte) |= _PAGE_SPECIAL; |
f5e706ad SR |
568 | return pte; |
569 | } | |
570 | ||
571 | static inline unsigned long pte_young(pte_t pte) | |
572 | { | |
573 | unsigned long mask; | |
574 | ||
575 | __asm__ __volatile__( | |
576 | "\n661: mov %1, %0\n" | |
577 | " nop\n" | |
578 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
579 | " .word 661b\n" | |
580 | " sethi %%uhi(%2), %0\n" | |
581 | " sllx %0, 32, %0\n" | |
582 | " .previous\n" | |
583 | : "=r" (mask) | |
584 | : "i" (_PAGE_ACCESSED_4U), "i" (_PAGE_ACCESSED_4V)); | |
585 | ||
586 | return (pte_val(pte) & mask); | |
587 | } | |
588 | ||
589 | static inline unsigned long pte_dirty(pte_t pte) | |
590 | { | |
591 | unsigned long mask; | |
592 | ||
593 | __asm__ __volatile__( | |
594 | "\n661: mov %1, %0\n" | |
595 | " nop\n" | |
596 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
597 | " .word 661b\n" | |
598 | " sethi %%uhi(%2), %0\n" | |
599 | " sllx %0, 32, %0\n" | |
600 | " .previous\n" | |
601 | : "=r" (mask) | |
602 | : "i" (_PAGE_MODIFIED_4U), "i" (_PAGE_MODIFIED_4V)); | |
603 | ||
604 | return (pte_val(pte) & mask); | |
605 | } | |
606 | ||
607 | static inline unsigned long pte_write(pte_t pte) | |
608 | { | |
609 | unsigned long mask; | |
610 | ||
611 | __asm__ __volatile__( | |
612 | "\n661: mov %1, %0\n" | |
613 | " nop\n" | |
614 | " .section .sun4v_2insn_patch, \"ax\"\n" | |
615 | " .word 661b\n" | |
616 | " sethi %%uhi(%2), %0\n" | |
617 | " sllx %0, 32, %0\n" | |
618 | " .previous\n" | |
619 | : "=r" (mask) | |
620 | : "i" (_PAGE_WRITE_4U), "i" (_PAGE_WRITE_4V)); | |
621 | ||
622 | return (pte_val(pte) & mask); | |
623 | } | |
624 | ||
625 | static inline unsigned long pte_exec(pte_t pte) | |
626 | { | |
627 | unsigned long mask; | |
628 | ||
629 | __asm__ __volatile__( | |
630 | "\n661: sethi %%hi(%1), %0\n" | |
631 | " .section .sun4v_1insn_patch, \"ax\"\n" | |
632 | " .word 661b\n" | |
633 | " mov %2, %0\n" | |
634 | " .previous\n" | |
635 | : "=r" (mask) | |
636 | : "i" (_PAGE_EXEC_4U), "i" (_PAGE_EXEC_4V)); | |
637 | ||
638 | return (pte_val(pte) & mask); | |
639 | } | |
640 | ||
f5e706ad SR |
641 | static inline unsigned long pte_present(pte_t pte) |
642 | { | |
643 | unsigned long val = pte_val(pte); | |
644 | ||
645 | __asm__ __volatile__( | |
646 | "\n661: and %0, %2, %0\n" | |
647 | " .section .sun4v_1insn_patch, \"ax\"\n" | |
648 | " .word 661b\n" | |
649 | " and %0, %3, %0\n" | |
650 | " .previous\n" | |
651 | : "=r" (val) | |
652 | : "0" (val), "i" (_PAGE_PRESENT_4U), "i" (_PAGE_PRESENT_4V)); | |
653 | ||
654 | return val; | |
655 | } | |
656 | ||
4a9d1946 | 657 | #define pte_accessible pte_accessible |
20841405 | 658 | static inline unsigned long pte_accessible(struct mm_struct *mm, pte_t a) |
4a9d1946 DM |
659 | { |
660 | return pte_val(a) & _PAGE_VALID; | |
661 | } | |
662 | ||
683d2fa6 | 663 | static inline unsigned long pte_special(pte_t pte) |
f5e706ad | 664 | { |
683d2fa6 | 665 | return pte_val(pte) & _PAGE_SPECIAL; |
f5e706ad SR |
666 | } |
667 | ||
a7b9403f | 668 | static inline unsigned long pmd_large(pmd_t pmd) |
89a77915 | 669 | { |
a7b9403f DM |
670 | pte_t pte = __pte(pmd_val(pmd)); |
671 | ||
04df419d | 672 | return pte_val(pte) & _PAGE_PMD_HUGE; |
89a77915 DM |
673 | } |
674 | ||
0dd5b7b0 | 675 | static inline unsigned long pmd_pfn(pmd_t pmd) |
9e695d2e | 676 | { |
a7b9403f DM |
677 | pte_t pte = __pte(pmd_val(pmd)); |
678 | ||
0dd5b7b0 | 679 | return pte_pfn(pte); |
9e695d2e DM |
680 | } |
681 | ||
0dd5b7b0 | 682 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
c164e038 KS |
683 | static inline unsigned long pmd_dirty(pmd_t pmd) |
684 | { | |
685 | pte_t pte = __pte(pmd_val(pmd)); | |
686 | ||
687 | return pte_dirty(pte); | |
688 | } | |
689 | ||
0dd5b7b0 | 690 | static inline unsigned long pmd_young(pmd_t pmd) |
9e695d2e | 691 | { |
a7b9403f DM |
692 | pte_t pte = __pte(pmd_val(pmd)); |
693 | ||
0dd5b7b0 | 694 | return pte_young(pte); |
9e695d2e DM |
695 | } |
696 | ||
0dd5b7b0 | 697 | static inline unsigned long pmd_write(pmd_t pmd) |
9e695d2e | 698 | { |
a7b9403f | 699 | pte_t pte = __pte(pmd_val(pmd)); |
9e695d2e | 700 | |
0dd5b7b0 | 701 | return pte_write(pte); |
9e695d2e DM |
702 | } |
703 | ||
a7b9403f | 704 | static inline unsigned long pmd_trans_huge(pmd_t pmd) |
9e695d2e | 705 | { |
a7b9403f DM |
706 | pte_t pte = __pte(pmd_val(pmd)); |
707 | ||
708 | return pte_val(pte) & _PAGE_PMD_HUGE; | |
9e695d2e DM |
709 | } |
710 | ||
9e695d2e DM |
711 | static inline pmd_t pmd_mkold(pmd_t pmd) |
712 | { | |
a7b9403f DM |
713 | pte_t pte = __pte(pmd_val(pmd)); |
714 | ||
715 | pte = pte_mkold(pte); | |
716 | ||
717 | return __pmd(pte_val(pte)); | |
9e695d2e DM |
718 | } |
719 | ||
720 | static inline pmd_t pmd_wrprotect(pmd_t pmd) | |
721 | { | |
a7b9403f DM |
722 | pte_t pte = __pte(pmd_val(pmd)); |
723 | ||
724 | pte = pte_wrprotect(pte); | |
725 | ||
726 | return __pmd(pte_val(pte)); | |
9e695d2e DM |
727 | } |
728 | ||
729 | static inline pmd_t pmd_mkdirty(pmd_t pmd) | |
730 | { | |
a7b9403f DM |
731 | pte_t pte = __pte(pmd_val(pmd)); |
732 | ||
733 | pte = pte_mkdirty(pte); | |
734 | ||
735 | return __pmd(pte_val(pte)); | |
9e695d2e DM |
736 | } |
737 | ||
79cedb8f MK |
738 | static inline pmd_t pmd_mkclean(pmd_t pmd) |
739 | { | |
740 | pte_t pte = __pte(pmd_val(pmd)); | |
741 | ||
742 | pte = pte_mkclean(pte); | |
743 | ||
744 | return __pmd(pte_val(pte)); | |
745 | } | |
746 | ||
9e695d2e DM |
747 | static inline pmd_t pmd_mkyoung(pmd_t pmd) |
748 | { | |
a7b9403f DM |
749 | pte_t pte = __pte(pmd_val(pmd)); |
750 | ||
751 | pte = pte_mkyoung(pte); | |
752 | ||
753 | return __pmd(pte_val(pte)); | |
9e695d2e DM |
754 | } |
755 | ||
756 | static inline pmd_t pmd_mkwrite(pmd_t pmd) | |
757 | { | |
a7b9403f DM |
758 | pte_t pte = __pte(pmd_val(pmd)); |
759 | ||
760 | pte = pte_mkwrite(pte); | |
761 | ||
a7b9403f | 762 | return __pmd(pte_val(pte)); |
9e695d2e DM |
763 | } |
764 | ||
a7b9403f DM |
765 | static inline pgprot_t pmd_pgprot(pmd_t entry) |
766 | { | |
767 | unsigned long val = pmd_val(entry); | |
768 | ||
769 | return __pgprot(val); | |
770 | } | |
9e695d2e DM |
771 | #endif |
772 | ||
773 | static inline int pmd_present(pmd_t pmd) | |
774 | { | |
2b77933c | 775 | return pmd_val(pmd) != 0UL; |
9e695d2e DM |
776 | } |
777 | ||
778 | #define pmd_none(pmd) (!pmd_val(pmd)) | |
779 | ||
26cf4325 DM |
780 | /* pmd_bad() is only called on non-trans-huge PMDs. Our encoding is |
781 | * very simple, it's just the physical address. PTE tables are of | |
782 | * size PAGE_SIZE so make sure the sub-PAGE_SIZE bits are clear and | |
783 | * the top bits outside of the range of any physical address size we | |
784 | * support are clear as well. We also validate the physical itself. | |
785 | */ | |
0dd5b7b0 | 786 | #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) |
26cf4325 DM |
787 | |
788 | #define pud_none(pud) (!pud_val(pud)) | |
789 | ||
0dd5b7b0 | 790 | #define pud_bad(pud) (pud_val(pud) & ~PAGE_MASK) |
26cf4325 | 791 | |
ac55c768 DM |
792 | #define pgd_none(pgd) (!pgd_val(pgd)) |
793 | ||
0dd5b7b0 | 794 | #define pgd_bad(pgd) (pgd_val(pgd) & ~PAGE_MASK) |
ac55c768 | 795 | |
9e695d2e | 796 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
f05a6865 SR |
797 | void set_pmd_at(struct mm_struct *mm, unsigned long addr, |
798 | pmd_t *pmdp, pmd_t pmd); | |
9e695d2e DM |
799 | #else |
800 | static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr, | |
801 | pmd_t *pmdp, pmd_t pmd) | |
802 | { | |
803 | *pmdp = pmd; | |
804 | } | |
805 | #endif | |
806 | ||
807 | static inline void pmd_set(struct mm_struct *mm, pmd_t *pmdp, pte_t *ptep) | |
808 | { | |
a7b9403f | 809 | unsigned long val = __pa((unsigned long) (ptep)); |
9e695d2e DM |
810 | |
811 | pmd_val(*pmdp) = val; | |
812 | } | |
813 | ||
f5e706ad | 814 | #define pud_set(pudp, pmdp) \ |
a7b9403f | 815 | (pud_val(*(pudp)) = (__pa((unsigned long) (pmdp)))) |
9e695d2e DM |
816 | static inline unsigned long __pmd_page(pmd_t pmd) |
817 | { | |
a7b9403f DM |
818 | pte_t pte = __pte(pmd_val(pmd)); |
819 | unsigned long pfn; | |
820 | ||
821 | pfn = pte_pfn(pte); | |
822 | ||
823 | return ((unsigned long) __va(pfn << PAGE_SHIFT)); | |
9e695d2e | 824 | } |
f5e706ad SR |
825 | #define pmd_page(pmd) virt_to_page((void *)__pmd_page(pmd)) |
826 | #define pud_page_vaddr(pud) \ | |
a7b9403f | 827 | ((unsigned long) __va(pud_val(pud))) |
f5e706ad | 828 | #define pud_page(pud) virt_to_page((void *)pud_page_vaddr(pud)) |
2b77933c | 829 | #define pmd_clear(pmdp) (pmd_val(*(pmdp)) = 0UL) |
f5e706ad | 830 | #define pud_present(pud) (pud_val(pud) != 0U) |
2b77933c | 831 | #define pud_clear(pudp) (pud_val(*(pudp)) = 0UL) |
ac55c768 DM |
832 | #define pgd_page_vaddr(pgd) \ |
833 | ((unsigned long) __va(pgd_val(pgd))) | |
834 | #define pgd_present(pgd) (pgd_val(pgd) != 0U) | |
acff7fdb | 835 | #define pgd_clear(pgdp) (pgd_val(*(pgdp)) = 0UL) |
f5e706ad | 836 | |
0dd5b7b0 DM |
837 | static inline unsigned long pud_large(pud_t pud) |
838 | { | |
839 | pte_t pte = __pte(pud_val(pud)); | |
840 | ||
841 | return pte_val(pte) & _PAGE_PMD_HUGE; | |
842 | } | |
843 | ||
844 | static inline unsigned long pud_pfn(pud_t pud) | |
845 | { | |
846 | pte_t pte = __pte(pud_val(pud)); | |
847 | ||
848 | return pte_pfn(pte); | |
849 | } | |
850 | ||
f5e706ad SR |
851 | /* Same in both SUN4V and SUN4U. */ |
852 | #define pte_none(pte) (!pte_val(pte)) | |
853 | ||
ac55c768 DM |
854 | #define pgd_set(pgdp, pudp) \ |
855 | (pgd_val(*(pgdp)) = (__pa((unsigned long) (pudp)))) | |
856 | ||
f5e706ad SR |
857 | /* to find an entry in a page-table-directory. */ |
858 | #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD - 1)) | |
859 | #define pgd_offset(mm, address) ((mm)->pgd + pgd_index(address)) | |
860 | ||
861 | /* to find an entry in a kernel page-table-directory */ | |
862 | #define pgd_offset_k(address) pgd_offset(&init_mm, address) | |
863 | ||
ac55c768 DM |
864 | /* Find an entry in the third-level page table.. */ |
865 | #define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD - 1)) | |
866 | #define pud_offset(pgdp, address) \ | |
867 | ((pud_t *) pgd_page_vaddr(*(pgdp)) + pud_index(address)) | |
868 | ||
f5e706ad SR |
869 | /* Find an entry in the second-level page table.. */ |
870 | #define pmd_offset(pudp, address) \ | |
871 | ((pmd_t *) pud_page_vaddr(*(pudp)) + \ | |
872 | (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))) | |
873 | ||
874 | /* Find an entry in the third-level page table.. */ | |
875 | #define pte_index(dir, address) \ | |
876 | ((pte_t *) __pmd_page(*(dir)) + \ | |
877 | ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))) | |
878 | #define pte_offset_kernel pte_index | |
879 | #define pte_offset_map pte_index | |
f5e706ad | 880 | #define pte_unmap(pte) do { } while (0) |
f5e706ad | 881 | |
589ee628 IM |
882 | /* We cannot include <linux/mm_types.h> at this point yet: */ |
883 | extern struct mm_struct init_mm; | |
884 | ||
f5e706ad | 885 | /* Actual page table PTE updates. */ |
f05a6865 | 886 | void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, |
c7d9f77d NG |
887 | pte_t *ptep, pte_t orig, int fullmm, |
888 | unsigned int hugepage_shift); | |
f5e706ad | 889 | |
24e49ee3 | 890 | static void maybe_tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, |
c7d9f77d NG |
891 | pte_t *ptep, pte_t orig, int fullmm, |
892 | unsigned int hugepage_shift) | |
24e49ee3 NG |
893 | { |
894 | /* It is more efficient to let flush_tlb_kernel_range() | |
895 | * handle init_mm tlb flushes. | |
896 | * | |
897 | * SUN4V NOTE: _PAGE_VALID is the same value in both the SUN4U | |
898 | * and SUN4V pte layout, so this inline test is fine. | |
899 | */ | |
900 | if (likely(mm != &init_mm) && pte_accessible(mm, orig)) | |
c7d9f77d | 901 | tlb_batch_add(mm, vaddr, ptep, orig, fullmm, hugepage_shift); |
24e49ee3 NG |
902 | } |
903 | ||
8809aa2d AK |
904 | #define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR |
905 | static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm, | |
906 | unsigned long addr, | |
907 | pmd_t *pmdp) | |
9e695d2e DM |
908 | { |
909 | pmd_t pmd = *pmdp; | |
2b77933c | 910 | set_pmd_at(mm, addr, pmdp, __pmd(0UL)); |
9e695d2e DM |
911 | return pmd; |
912 | } | |
913 | ||
90f08e39 PZ |
914 | static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr, |
915 | pte_t *ptep, pte_t pte, int fullmm) | |
f5e706ad SR |
916 | { |
917 | pte_t orig = *ptep; | |
918 | ||
919 | *ptep = pte; | |
c7d9f77d | 920 | maybe_tlb_batch_add(mm, addr, ptep, orig, fullmm, PAGE_SHIFT); |
f5e706ad SR |
921 | } |
922 | ||
90f08e39 PZ |
923 | #define set_pte_at(mm,addr,ptep,pte) \ |
924 | __set_pte_at((mm), (addr), (ptep), (pte), 0) | |
925 | ||
f5e706ad SR |
926 | #define pte_clear(mm,addr,ptep) \ |
927 | set_pte_at((mm), (addr), (ptep), __pte(0UL)) | |
928 | ||
90f08e39 PZ |
929 | #define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL |
930 | #define pte_clear_not_present_full(mm,addr,ptep,fullmm) \ | |
931 | __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm)) | |
932 | ||
f5e706ad SR |
933 | #ifdef DCACHE_ALIASING_POSSIBLE |
934 | #define __HAVE_ARCH_MOVE_PTE | |
935 | #define move_pte(pte, prot, old_addr, new_addr) \ | |
936 | ({ \ | |
937 | pte_t newpte = (pte); \ | |
938 | if (tlb_type != hypervisor && pte_present(pte)) { \ | |
939 | unsigned long this_pfn = pte_pfn(pte); \ | |
940 | \ | |
941 | if (pfn_valid(this_pfn) && \ | |
942 | (((old_addr) ^ (new_addr)) & (1 << 13))) \ | |
943 | flush_dcache_page_all(current->mm, \ | |
944 | pfn_to_page(this_pfn)); \ | |
945 | } \ | |
946 | newpte; \ | |
947 | }) | |
948 | #endif | |
949 | ||
2b77933c | 950 | extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; |
f5e706ad | 951 | |
f05a6865 SR |
952 | void paging_init(void); |
953 | unsigned long find_ecache_flush_span(unsigned long size); | |
f5e706ad | 954 | |
cb1b8209 | 955 | struct seq_file; |
f05a6865 | 956 | void mmu_info(struct seq_file *); |
cb1b8209 | 957 | |
f5e706ad | 958 | struct vm_area_struct; |
f05a6865 | 959 | void update_mmu_cache(struct vm_area_struct *, unsigned long, pte_t *); |
9e695d2e | 960 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE |
f05a6865 SR |
961 | void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, |
962 | pmd_t *pmd); | |
9e695d2e | 963 | |
51e5ef1b DM |
964 | #define __HAVE_ARCH_PMDP_INVALIDATE |
965 | extern void pmdp_invalidate(struct vm_area_struct *vma, unsigned long address, | |
966 | pmd_t *pmdp); | |
967 | ||
9e695d2e | 968 | #define __HAVE_ARCH_PGTABLE_DEPOSIT |
f05a6865 SR |
969 | void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp, |
970 | pgtable_t pgtable); | |
9e695d2e DM |
971 | |
972 | #define __HAVE_ARCH_PGTABLE_WITHDRAW | |
f05a6865 | 973 | pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp); |
9e695d2e | 974 | #endif |
f5e706ad SR |
975 | |
976 | /* Encode and de-code a swap entry */ | |
977 | #define __swp_type(entry) (((entry).val >> PAGE_SHIFT) & 0xffUL) | |
978 | #define __swp_offset(entry) ((entry).val >> (PAGE_SHIFT + 8UL)) | |
979 | #define __swp_entry(type, offset) \ | |
980 | ( (swp_entry_t) \ | |
981 | { \ | |
982 | (((long)(type) << PAGE_SHIFT) | \ | |
983 | ((long)(offset) << (PAGE_SHIFT + 8UL))) \ | |
984 | } ) | |
985 | #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) | |
986 | #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) | |
987 | ||
f05a6865 | 988 | int page_in_phys_avail(unsigned long paddr); |
f5e706ad | 989 | |
f5e706ad SR |
990 | /* |
991 | * For sparc32&64, the pfn in io_remap_pfn_range() carries <iospace> in | |
992 | * its high 4 bits. These macros/functions put it there or get it from there. | |
993 | */ | |
994 | #define MK_IOSPACE_PFN(space, pfn) (pfn | (space << (BITS_PER_LONG - 4))) | |
995 | #define GET_IOSPACE(pfn) (pfn >> (BITS_PER_LONG - 4)) | |
996 | #define GET_PFN(pfn) (pfn & 0x0fffffffffffffffUL) | |
997 | ||
f05a6865 SR |
998 | int remap_pfn_range(struct vm_area_struct *, unsigned long, unsigned long, |
999 | unsigned long, pgprot_t); | |
3e37fd31 DM |
1000 | |
1001 | static inline int io_remap_pfn_range(struct vm_area_struct *vma, | |
1002 | unsigned long from, unsigned long pfn, | |
1003 | unsigned long size, pgprot_t prot) | |
1004 | { | |
1005 | unsigned long offset = GET_PFN(pfn) << PAGE_SHIFT; | |
1006 | int space = GET_IOSPACE(pfn); | |
1007 | unsigned long phys_base; | |
1008 | ||
1009 | phys_base = offset | (((unsigned long) space) << 32UL); | |
1010 | ||
1011 | return remap_pfn_range(vma, from, phys_base >> PAGE_SHIFT, size, prot); | |
1012 | } | |
40d158e6 | 1013 | #define io_remap_pfn_range io_remap_pfn_range |
3e37fd31 | 1014 | |
f36391d2 | 1015 | #include <asm/tlbflush.h> |
f5e706ad SR |
1016 | #include <asm-generic/pgtable.h> |
1017 | ||
1018 | /* We provide our own get_unmapped_area to cope with VA holes and | |
1019 | * SHM area cache aliasing for userland. | |
1020 | */ | |
1021 | #define HAVE_ARCH_UNMAPPED_AREA | |
1022 | #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN | |
1023 | ||
1024 | /* We provide a special get_unmapped_area for framebuffer mmaps to try and use | |
1025 | * the largest alignment possible such that larget PTEs can be used. | |
1026 | */ | |
f05a6865 SR |
1027 | unsigned long get_fb_unmapped_area(struct file *filp, unsigned long, |
1028 | unsigned long, unsigned long, | |
1029 | unsigned long); | |
f5e706ad SR |
1030 | #define HAVE_ARCH_FB_UNMAPPED_AREA |
1031 | ||
f05a6865 SR |
1032 | void pgtable_cache_init(void); |
1033 | void sun4v_register_fault_status(void); | |
1034 | void sun4v_ktsb_register(void); | |
1035 | void __init cheetah_ecache_flush_init(void); | |
1036 | void sun4v_patch_tlb_handlers(void); | |
f5e706ad SR |
1037 | |
1038 | extern unsigned long cmdline_memory_size; | |
1039 | ||
f05a6865 | 1040 | asmlinkage void do_sparc64_fault(struct pt_regs *regs); |
b539c467 | 1041 | |
f5e706ad SR |
1042 | #endif /* !(__ASSEMBLY__) */ |
1043 | ||
1044 | #endif /* !(_SPARC64_PGTABLE_H) */ |