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Commit | Line | Data |
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4a907dec | 1 | /* irq.c: UltraSparc IRQ handling/init/registry. |
1da177e4 | 2 | * |
227c3311 | 3 | * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
6 | */ | |
7 | ||
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/sched.h> | |
9843099f | 10 | #include <linux/linkage.h> |
1da177e4 LT |
11 | #include <linux/ptrace.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/kernel_stat.h> | |
14 | #include <linux/signal.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/random.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/proc_fs.h> | |
22 | #include <linux/seq_file.h> | |
9960e9e8 | 23 | #include <linux/ftrace.h> |
e18e2a00 | 24 | #include <linux/irq.h> |
2e2dc1d7 | 25 | #include <linux/kmemleak.h> |
1da177e4 LT |
26 | |
27 | #include <asm/ptrace.h> | |
28 | #include <asm/processor.h> | |
29 | #include <asm/atomic.h> | |
30 | #include <asm/system.h> | |
31 | #include <asm/irq.h> | |
2e457ef6 | 32 | #include <asm/io.h> |
1da177e4 LT |
33 | #include <asm/iommu.h> |
34 | #include <asm/upa.h> | |
35 | #include <asm/oplib.h> | |
25c7581b | 36 | #include <asm/prom.h> |
1da177e4 LT |
37 | #include <asm/timer.h> |
38 | #include <asm/smp.h> | |
39 | #include <asm/starfire.h> | |
40 | #include <asm/uaccess.h> | |
41 | #include <asm/cache.h> | |
42 | #include <asm/cpudata.h> | |
63b61452 | 43 | #include <asm/auxio.h> |
92704a1c | 44 | #include <asm/head.h> |
4a907dec | 45 | #include <asm/hypervisor.h> |
42d5f99b | 46 | #include <asm/cacheflush.h> |
1da177e4 | 47 | |
d91aa123 | 48 | #include "entry.h" |
280ff974 | 49 | #include "cpumap.h" |
ec687886 | 50 | #include "kstack.h" |
e18e2a00 DM |
51 | |
52 | #define NUM_IVECS (IMAP_INR + 1) | |
d91aa123 | 53 | |
10397e40 | 54 | struct ino_bucket *ivector_table; |
eb2d8d60 | 55 | unsigned long ivector_table_pa; |
1da177e4 | 56 | |
42d5f99b DM |
57 | /* On several sun4u processors, it is illegal to mix bypass and |
58 | * non-bypass accesses. Therefore we access all INO buckets | |
59 | * using bypass accesses only. | |
60 | */ | |
61 | static unsigned long bucket_get_chain_pa(unsigned long bucket_pa) | |
62 | { | |
63 | unsigned long ret; | |
64 | ||
65 | __asm__ __volatile__("ldxa [%1] %2, %0" | |
66 | : "=&r" (ret) | |
67 | : "r" (bucket_pa + | |
68 | offsetof(struct ino_bucket, | |
69 | __irq_chain_pa)), | |
70 | "i" (ASI_PHYS_USE_EC)); | |
71 | ||
72 | return ret; | |
73 | } | |
74 | ||
75 | static void bucket_clear_chain_pa(unsigned long bucket_pa) | |
76 | { | |
77 | __asm__ __volatile__("stxa %%g0, [%0] %1" | |
78 | : /* no outputs */ | |
79 | : "r" (bucket_pa + | |
80 | offsetof(struct ino_bucket, | |
81 | __irq_chain_pa)), | |
82 | "i" (ASI_PHYS_USE_EC)); | |
83 | } | |
84 | ||
85 | static unsigned int bucket_get_virt_irq(unsigned long bucket_pa) | |
86 | { | |
87 | unsigned int ret; | |
88 | ||
89 | __asm__ __volatile__("lduwa [%1] %2, %0" | |
90 | : "=&r" (ret) | |
91 | : "r" (bucket_pa + | |
92 | offsetof(struct ino_bucket, | |
93 | __virt_irq)), | |
94 | "i" (ASI_PHYS_USE_EC)); | |
95 | ||
96 | return ret; | |
97 | } | |
98 | ||
99 | static void bucket_set_virt_irq(unsigned long bucket_pa, | |
100 | unsigned int virt_irq) | |
101 | { | |
102 | __asm__ __volatile__("stwa %0, [%1] %2" | |
103 | : /* no outputs */ | |
104 | : "r" (virt_irq), | |
105 | "r" (bucket_pa + | |
106 | offsetof(struct ino_bucket, | |
107 | __virt_irq)), | |
108 | "i" (ASI_PHYS_USE_EC)); | |
109 | } | |
110 | ||
eb2d8d60 | 111 | #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa) |
1da177e4 | 112 | |
93b3238e | 113 | static struct { |
93b3238e DM |
114 | unsigned int dev_handle; |
115 | unsigned int dev_ino; | |
256c1df3 | 116 | unsigned int in_use; |
45b3f4cc | 117 | } virt_irq_table[NR_IRQS]; |
759f89e0 | 118 | static DEFINE_SPINLOCK(virt_irq_alloc_lock); |
8047e247 | 119 | |
256c1df3 | 120 | unsigned char virt_irq_alloc(unsigned int dev_handle, |
bb74b734 | 121 | unsigned int dev_ino) |
8047e247 | 122 | { |
759f89e0 | 123 | unsigned long flags; |
8047e247 DM |
124 | unsigned char ent; |
125 | ||
126 | BUILD_BUG_ON(NR_IRQS >= 256); | |
127 | ||
759f89e0 DM |
128 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
129 | ||
35a17eb6 | 130 | for (ent = 1; ent < NR_IRQS; ent++) { |
45b3f4cc | 131 | if (!virt_irq_table[ent].in_use) |
35a17eb6 DM |
132 | break; |
133 | } | |
8047e247 DM |
134 | if (ent >= NR_IRQS) { |
135 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
759f89e0 DM |
136 | ent = 0; |
137 | } else { | |
45b3f4cc DM |
138 | virt_irq_table[ent].dev_handle = dev_handle; |
139 | virt_irq_table[ent].dev_ino = dev_ino; | |
140 | virt_irq_table[ent].in_use = 1; | |
8047e247 DM |
141 | } |
142 | ||
759f89e0 | 143 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 DM |
144 | |
145 | return ent; | |
146 | } | |
147 | ||
5746c99d | 148 | #ifdef CONFIG_PCI_MSI |
759f89e0 | 149 | void virt_irq_free(unsigned int virt_irq) |
8047e247 | 150 | { |
759f89e0 | 151 | unsigned long flags; |
8047e247 | 152 | |
35a17eb6 DM |
153 | if (virt_irq >= NR_IRQS) |
154 | return; | |
155 | ||
759f89e0 DM |
156 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
157 | ||
45b3f4cc | 158 | virt_irq_table[virt_irq].in_use = 0; |
35a17eb6 | 159 | |
759f89e0 | 160 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 | 161 | } |
5746c99d | 162 | #endif |
8047e247 | 163 | |
1da177e4 | 164 | /* |
e18e2a00 | 165 | * /proc/interrupts printing: |
1da177e4 | 166 | */ |
1da177e4 LT |
167 | |
168 | int show_interrupts(struct seq_file *p, void *v) | |
169 | { | |
e18e2a00 DM |
170 | int i = *(loff_t *) v, j; |
171 | struct irqaction * action; | |
1da177e4 | 172 | unsigned long flags; |
1da177e4 | 173 | |
e18e2a00 DM |
174 | if (i == 0) { |
175 | seq_printf(p, " "); | |
176 | for_each_online_cpu(j) | |
177 | seq_printf(p, "CPU%d ",j); | |
178 | seq_putc(p, '\n'); | |
179 | } | |
180 | ||
181 | if (i < NR_IRQS) { | |
239007b8 | 182 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); |
e18e2a00 DM |
183 | action = irq_desc[i].action; |
184 | if (!action) | |
185 | goto skip; | |
186 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
187 | #ifndef CONFIG_SMP |
188 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
189 | #else | |
e18e2a00 | 190 | for_each_online_cpu(j) |
e81838d2 | 191 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); |
1da177e4 | 192 | #endif |
9f2264ac | 193 | seq_printf(p, " %9s", irq_desc[i].irq_data.chip->name); |
e18e2a00 DM |
194 | seq_printf(p, " %s", action->name); |
195 | ||
196 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 197 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 198 | |
1da177e4 | 199 | seq_putc(p, '\n'); |
e18e2a00 | 200 | skip: |
239007b8 | 201 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); |
e5553a6d DM |
202 | } else if (i == NR_IRQS) { |
203 | seq_printf(p, "NMI: "); | |
204 | for_each_online_cpu(j) | |
205 | seq_printf(p, "%10u ", cpu_data(j).__nmi_count); | |
206 | seq_printf(p, " Non-maskable interrupts\n"); | |
1da177e4 | 207 | } |
1da177e4 LT |
208 | return 0; |
209 | } | |
210 | ||
ebd8c56c DM |
211 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
212 | { | |
213 | unsigned int tid; | |
214 | ||
215 | if (this_is_starfire) { | |
216 | tid = starfire_translate(imap, cpuid); | |
217 | tid <<= IMAP_TID_SHIFT; | |
218 | tid &= IMAP_TID_UPA; | |
219 | } else { | |
220 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
221 | unsigned long ver; | |
222 | ||
223 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
224 | if ((ver >> 32UL) == __JALAPENO_ID || | |
225 | (ver >> 32UL) == __SERRANO_ID) { | |
226 | tid = cpuid << IMAP_TID_SHIFT; | |
227 | tid &= IMAP_TID_JBUS; | |
228 | } else { | |
229 | unsigned int a = cpuid & 0x1f; | |
230 | unsigned int n = (cpuid >> 5) & 0x1f; | |
231 | ||
232 | tid = ((a << IMAP_AID_SHIFT) | | |
233 | (n << IMAP_NID_SHIFT)); | |
234 | tid &= (IMAP_AID_SAFARI | | |
a419aef8 | 235 | IMAP_NID_SAFARI); |
ebd8c56c DM |
236 | } |
237 | } else { | |
238 | tid = cpuid << IMAP_TID_SHIFT; | |
239 | tid &= IMAP_TID_UPA; | |
240 | } | |
241 | } | |
242 | ||
243 | return tid; | |
244 | } | |
245 | ||
e18e2a00 DM |
246 | struct irq_handler_data { |
247 | unsigned long iclr; | |
248 | unsigned long imap; | |
8047e247 | 249 | |
e18e2a00 | 250 | void (*pre_handler)(unsigned int, void *, void *); |
8d57d3ad DM |
251 | void *arg1; |
252 | void *arg2; | |
e18e2a00 | 253 | }; |
1da177e4 | 254 | |
e18e2a00 | 255 | #ifdef CONFIG_SMP |
1091ce62 | 256 | static int irq_choose_cpu(unsigned int virt_irq, const struct cpumask *affinity) |
088dd1f8 | 257 | { |
e65e49d0 | 258 | cpumask_t mask; |
e18e2a00 | 259 | int cpuid; |
088dd1f8 | 260 | |
1091ce62 | 261 | cpumask_copy(&mask, affinity); |
280ff974 HP |
262 | if (cpus_equal(mask, cpu_online_map)) { |
263 | cpuid = map_to_cpu(virt_irq); | |
e18e2a00 DM |
264 | } else { |
265 | cpumask_t tmp; | |
088dd1f8 | 266 | |
e18e2a00 | 267 | cpus_and(tmp, cpu_online_map, mask); |
280ff974 | 268 | cpuid = cpus_empty(tmp) ? map_to_cpu(virt_irq) : first_cpu(tmp); |
1da177e4 | 269 | } |
088dd1f8 | 270 | |
e18e2a00 DM |
271 | return cpuid; |
272 | } | |
273 | #else | |
6abce771 DM |
274 | #define irq_choose_cpu(virt_irq, affinity) \ |
275 | real_hard_smp_processor_id() | |
e18e2a00 | 276 | #endif |
1da177e4 | 277 | |
4832b992 | 278 | static void sun4u_irq_enable(struct irq_data *data) |
e3999574 | 279 | { |
4832b992 | 280 | struct irq_handler_data *handler_data = data->handler_data; |
e3999574 | 281 | |
cae78728 | 282 | if (likely(handler_data)) { |
861fe906 | 283 | unsigned long cpuid, imap, val; |
e18e2a00 | 284 | unsigned int tid; |
e3999574 | 285 | |
4832b992 | 286 | cpuid = irq_choose_cpu(data->irq, data->affinity); |
cae78728 | 287 | imap = handler_data->imap; |
e3999574 | 288 | |
e18e2a00 | 289 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 290 | |
861fe906 DM |
291 | val = upa_readq(imap); |
292 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
293 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
294 | val |= tid | IMAP_VALID; | |
295 | upa_writeq(val, imap); | |
cae78728 | 296 | upa_writeq(ICLR_IDLE, handler_data->iclr); |
e3999574 | 297 | } |
e3999574 DM |
298 | } |
299 | ||
4832b992 SR |
300 | static int sun4u_set_affinity(struct irq_data *data, |
301 | const struct cpumask *mask, bool force) | |
b53bcb67 | 302 | { |
4832b992 | 303 | struct irq_handler_data *handler_data = data->handler_data; |
1091ce62 | 304 | |
cae78728 | 305 | if (likely(handler_data)) { |
1091ce62 DM |
306 | unsigned long cpuid, imap, val; |
307 | unsigned int tid; | |
308 | ||
4832b992 | 309 | cpuid = irq_choose_cpu(data->irq, mask); |
cae78728 | 310 | imap = handler_data->imap; |
1091ce62 DM |
311 | |
312 | tid = sun4u_compute_tid(imap, cpuid); | |
313 | ||
314 | val = upa_readq(imap); | |
315 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
316 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
317 | val |= tid | IMAP_VALID; | |
318 | upa_writeq(val, imap); | |
cae78728 | 319 | upa_writeq(ICLR_IDLE, handler_data->iclr); |
1091ce62 | 320 | } |
d5dedd45 YL |
321 | |
322 | return 0; | |
b53bcb67 DM |
323 | } |
324 | ||
d0cac39e DM |
325 | /* Don't do anything. The desc->status check for IRQ_DISABLED in |
326 | * handler_irq() will skip the handler call and that will leave the | |
327 | * interrupt in the sent state. The next ->enable() call will hit the | |
328 | * ICLR register to reset the state machine. | |
329 | * | |
330 | * This scheme is necessary, instead of clearing the Valid bit in the | |
331 | * IMAP register, to handle the case of IMAP registers being shared by | |
332 | * multiple INOs (and thus ICLR registers). Since we use a different | |
333 | * virtual IRQ for each shared IMAP instance, the generic code thinks | |
334 | * there is only one user so it prematurely calls ->disable() on | |
335 | * free_irq(). | |
336 | * | |
337 | * We have to provide an explicit ->disable() method instead of using | |
338 | * NULL to get the default. The reason is that if the generic code | |
339 | * sees that, it also hooks up a default ->shutdown method which | |
340 | * invokes ->mask() which we do not want. See irq_chip_set_defaults(). | |
341 | */ | |
4832b992 | 342 | static void sun4u_irq_disable(struct irq_data *data) |
1da177e4 | 343 | { |
088dd1f8 DM |
344 | } |
345 | ||
4832b992 | 346 | static void sun4u_irq_eoi(struct irq_data *data) |
088dd1f8 | 347 | { |
4832b992 SR |
348 | struct irq_handler_data *handler_data = data->handler_data; |
349 | struct irq_desc *desc = irq_desc + data->irq; | |
5a606b72 DM |
350 | |
351 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
352 | return; | |
088dd1f8 | 353 | |
cae78728 SR |
354 | if (likely(handler_data)) |
355 | upa_writeq(ICLR_IDLE, handler_data->iclr); | |
088dd1f8 DM |
356 | } |
357 | ||
4832b992 | 358 | static void sun4v_irq_enable(struct irq_data *data) |
088dd1f8 | 359 | { |
4832b992 SR |
360 | unsigned int ino = virt_irq_table[data->irq].dev_ino; |
361 | unsigned long cpuid = irq_choose_cpu(data->irq, data->affinity); | |
77182300 DM |
362 | int err; |
363 | ||
364 | err = sun4v_intr_settarget(ino, cpuid); | |
365 | if (err != HV_EOK) | |
366 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
367 | "err(%d)\n", ino, cpuid, err); | |
368 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); | |
369 | if (err != HV_EOK) | |
370 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
371 | "err(%d)\n", ino, err); | |
372 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
373 | if (err != HV_EOK) | |
374 | printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", | |
375 | ino, err); | |
088dd1f8 DM |
376 | } |
377 | ||
4832b992 SR |
378 | static int sun4v_set_affinity(struct irq_data *data, |
379 | const struct cpumask *mask, bool force) | |
b53bcb67 | 380 | { |
4832b992 SR |
381 | unsigned int ino = virt_irq_table[data->irq].dev_ino; |
382 | unsigned long cpuid = irq_choose_cpu(data->irq, mask); | |
77182300 DM |
383 | int err; |
384 | ||
385 | err = sun4v_intr_settarget(ino, cpuid); | |
386 | if (err != HV_EOK) | |
387 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
388 | "err(%d)\n", ino, cpuid, err); | |
d5dedd45 YL |
389 | |
390 | return 0; | |
b53bcb67 DM |
391 | } |
392 | ||
4832b992 | 393 | static void sun4v_irq_disable(struct irq_data *data) |
1da177e4 | 394 | { |
4832b992 | 395 | unsigned int ino = virt_irq_table[data->irq].dev_ino; |
77182300 | 396 | int err; |
1da177e4 | 397 | |
77182300 DM |
398 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
399 | if (err != HV_EOK) | |
400 | printk(KERN_ERR "sun4v_intr_setenabled(%x): " | |
401 | "err(%d)\n", ino, err); | |
e18e2a00 | 402 | } |
1da177e4 | 403 | |
4832b992 | 404 | static void sun4v_irq_eoi(struct irq_data *data) |
e18e2a00 | 405 | { |
4832b992 SR |
406 | unsigned int ino = virt_irq_table[data->irq].dev_ino; |
407 | struct irq_desc *desc = irq_desc + data->irq; | |
77182300 | 408 | int err; |
5a606b72 DM |
409 | |
410 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
411 | return; | |
1da177e4 | 412 | |
77182300 DM |
413 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
414 | if (err != HV_EOK) | |
415 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
416 | "err(%d)\n", ino, err); | |
1da177e4 LT |
417 | } |
418 | ||
4832b992 | 419 | static void sun4v_virq_enable(struct irq_data *data) |
4a907dec | 420 | { |
77182300 DM |
421 | unsigned long cpuid, dev_handle, dev_ino; |
422 | int err; | |
423 | ||
4832b992 | 424 | cpuid = irq_choose_cpu(data->irq, data->affinity); |
77182300 | 425 | |
4832b992 SR |
426 | dev_handle = virt_irq_table[data->irq].dev_handle; |
427 | dev_ino = virt_irq_table[data->irq].dev_ino; | |
77182300 DM |
428 | |
429 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
430 | if (err != HV_EOK) | |
431 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
432 | "err(%d)\n", | |
433 | dev_handle, dev_ino, cpuid, err); | |
434 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
435 | HV_INTR_STATE_IDLE); | |
436 | if (err != HV_EOK) | |
437 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
438 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
439 | dev_handle, dev_ino, err); | |
440 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
441 | HV_INTR_ENABLED); | |
442 | if (err != HV_EOK) | |
443 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
444 | "HV_INTR_ENABLED): err(%d)\n", | |
445 | dev_handle, dev_ino, err); | |
4a907dec DM |
446 | } |
447 | ||
4832b992 SR |
448 | static int sun4v_virt_set_affinity(struct irq_data *data, |
449 | const struct cpumask *mask, bool force) | |
b53bcb67 | 450 | { |
77182300 DM |
451 | unsigned long cpuid, dev_handle, dev_ino; |
452 | int err; | |
b53bcb67 | 453 | |
4832b992 | 454 | cpuid = irq_choose_cpu(data->irq, mask); |
b53bcb67 | 455 | |
4832b992 SR |
456 | dev_handle = virt_irq_table[data->irq].dev_handle; |
457 | dev_ino = virt_irq_table[data->irq].dev_ino; | |
b53bcb67 | 458 | |
77182300 DM |
459 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); |
460 | if (err != HV_EOK) | |
461 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
462 | "err(%d)\n", | |
463 | dev_handle, dev_ino, cpuid, err); | |
d5dedd45 YL |
464 | |
465 | return 0; | |
b53bcb67 DM |
466 | } |
467 | ||
4832b992 | 468 | static void sun4v_virq_disable(struct irq_data *data) |
4a907dec | 469 | { |
77182300 DM |
470 | unsigned long dev_handle, dev_ino; |
471 | int err; | |
472 | ||
4832b992 SR |
473 | dev_handle = virt_irq_table[data->irq].dev_handle; |
474 | dev_ino = virt_irq_table[data->irq].dev_ino; | |
77182300 DM |
475 | |
476 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
477 | HV_INTR_DISABLED); | |
478 | if (err != HV_EOK) | |
479 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
480 | "HV_INTR_DISABLED): err(%d)\n", | |
481 | dev_handle, dev_ino, err); | |
4a907dec DM |
482 | } |
483 | ||
4832b992 | 484 | static void sun4v_virq_eoi(struct irq_data *data) |
4a907dec | 485 | { |
4832b992 | 486 | struct irq_desc *desc = irq_desc + data->irq; |
77182300 DM |
487 | unsigned long dev_handle, dev_ino; |
488 | int err; | |
5a606b72 DM |
489 | |
490 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
491 | return; | |
4a907dec | 492 | |
4832b992 SR |
493 | dev_handle = virt_irq_table[data->irq].dev_handle; |
494 | dev_ino = virt_irq_table[data->irq].dev_ino; | |
4a907dec | 495 | |
77182300 DM |
496 | err = sun4v_vintr_set_state(dev_handle, dev_ino, |
497 | HV_INTR_STATE_IDLE); | |
498 | if (err != HV_EOK) | |
499 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
500 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
501 | dev_handle, dev_ino, err); | |
4a907dec DM |
502 | } |
503 | ||
729e7d7e | 504 | static struct irq_chip sun4u_irq = { |
4832b992 SR |
505 | .name = "sun4u", |
506 | .irq_enable = sun4u_irq_enable, | |
507 | .irq_disable = sun4u_irq_disable, | |
508 | .irq_eoi = sun4u_irq_eoi, | |
509 | .irq_set_affinity = sun4u_set_affinity, | |
e18e2a00 | 510 | }; |
088dd1f8 | 511 | |
729e7d7e | 512 | static struct irq_chip sun4v_irq = { |
4832b992 SR |
513 | .name = "sun4v", |
514 | .irq_enable = sun4v_irq_enable, | |
515 | .irq_disable = sun4v_irq_disable, | |
516 | .irq_eoi = sun4v_irq_eoi, | |
517 | .irq_set_affinity = sun4v_set_affinity, | |
e18e2a00 | 518 | }; |
1da177e4 | 519 | |
4a907dec | 520 | static struct irq_chip sun4v_virq = { |
4832b992 SR |
521 | .name = "vsun4v", |
522 | .irq_enable = sun4v_virq_enable, | |
523 | .irq_disable = sun4v_virq_disable, | |
524 | .irq_eoi = sun4v_virq_eoi, | |
525 | .irq_set_affinity = sun4v_virt_set_affinity, | |
4a907dec DM |
526 | }; |
527 | ||
edde08f2 | 528 | static void pre_flow_handler(unsigned int virt_irq, |
8d57d3ad DM |
529 | struct irq_desc *desc) |
530 | { | |
e6ebd529 | 531 | struct irq_handler_data *handler_data = get_irq_data(virt_irq); |
8d57d3ad DM |
532 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
533 | ||
cae78728 | 534 | handler_data->pre_handler(ino, handler_data->arg1, handler_data->arg2); |
8d57d3ad DM |
535 | |
536 | handle_fasteoi_irq(virt_irq, desc); | |
537 | } | |
538 | ||
e18e2a00 DM |
539 | void irq_install_pre_handler(int virt_irq, |
540 | void (*func)(unsigned int, void *, void *), | |
541 | void *arg1, void *arg2) | |
542 | { | |
e6ebd529 | 543 | struct irq_handler_data *handler_data = get_irq_data(virt_irq); |
8d57d3ad | 544 | struct irq_desc *desc = irq_desc + virt_irq; |
088dd1f8 | 545 | |
cae78728 SR |
546 | handler_data->pre_handler = func; |
547 | handler_data->arg1 = arg1; | |
548 | handler_data->arg2 = arg2; | |
24ac26d4 | 549 | |
8d57d3ad | 550 | desc->handle_irq = pre_flow_handler; |
e18e2a00 | 551 | } |
1da177e4 | 552 | |
e18e2a00 DM |
553 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
554 | { | |
555 | struct ino_bucket *bucket; | |
cae78728 | 556 | struct irq_handler_data *handler_data; |
42d5f99b | 557 | unsigned int virt_irq; |
e18e2a00 | 558 | int ino; |
1da177e4 | 559 | |
e18e2a00 | 560 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 561 | |
861fe906 | 562 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
e18e2a00 | 563 | bucket = &ivector_table[ino]; |
42d5f99b DM |
564 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
565 | if (!virt_irq) { | |
256c1df3 | 566 | virt_irq = virt_irq_alloc(0, ino); |
42d5f99b | 567 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
568 | set_irq_chip_and_handler_name(virt_irq, |
569 | &sun4u_irq, | |
570 | handle_fasteoi_irq, | |
571 | "IVEC"); | |
fd0504c3 | 572 | } |
1da177e4 | 573 | |
e6ebd529 | 574 | handler_data = get_irq_data(virt_irq); |
cae78728 | 575 | if (unlikely(handler_data)) |
e18e2a00 | 576 | goto out; |
fd0504c3 | 577 | |
cae78728 SR |
578 | handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
579 | if (unlikely(!handler_data)) { | |
e18e2a00 DM |
580 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); |
581 | prom_halt(); | |
1da177e4 | 582 | } |
e6ebd529 | 583 | set_irq_data(virt_irq, handler_data); |
1da177e4 | 584 | |
cae78728 SR |
585 | handler_data->imap = imap; |
586 | handler_data->iclr = iclr; | |
1da177e4 | 587 | |
e18e2a00 | 588 | out: |
42d5f99b | 589 | return virt_irq; |
e18e2a00 | 590 | } |
1da177e4 | 591 | |
4a907dec DM |
592 | static unsigned int sun4v_build_common(unsigned long sysino, |
593 | struct irq_chip *chip) | |
1da177e4 | 594 | { |
8047e247 | 595 | struct ino_bucket *bucket; |
cae78728 | 596 | struct irq_handler_data *handler_data; |
42d5f99b | 597 | unsigned int virt_irq; |
8047e247 | 598 | |
e18e2a00 | 599 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 600 | |
e18e2a00 | 601 | bucket = &ivector_table[sysino]; |
42d5f99b DM |
602 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
603 | if (!virt_irq) { | |
256c1df3 | 604 | virt_irq = virt_irq_alloc(0, sysino); |
42d5f99b | 605 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
606 | set_irq_chip_and_handler_name(virt_irq, chip, |
607 | handle_fasteoi_irq, | |
608 | "IVEC"); | |
1da177e4 | 609 | } |
1da177e4 | 610 | |
e6ebd529 | 611 | handler_data = get_irq_data(virt_irq); |
cae78728 | 612 | if (unlikely(handler_data)) |
1da177e4 | 613 | goto out; |
1da177e4 | 614 | |
cae78728 SR |
615 | handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
616 | if (unlikely(!handler_data)) { | |
e18e2a00 DM |
617 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); |
618 | prom_halt(); | |
619 | } | |
e6ebd529 | 620 | set_irq_data(virt_irq, handler_data); |
1da177e4 | 621 | |
e18e2a00 DM |
622 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
623 | * is done by hypervisor calls on sun4v platforms, not by direct | |
624 | * register accesses. | |
625 | */ | |
cae78728 SR |
626 | handler_data->imap = ~0UL; |
627 | handler_data->iclr = ~0UL; | |
1da177e4 | 628 | |
e18e2a00 | 629 | out: |
42d5f99b | 630 | return virt_irq; |
e18e2a00 | 631 | } |
1da177e4 | 632 | |
4a907dec DM |
633 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
634 | { | |
635 | unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); | |
636 | ||
637 | return sun4v_build_common(sysino, &sun4v_irq); | |
638 | } | |
639 | ||
640 | unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |
641 | { | |
cae78728 | 642 | struct irq_handler_data *handler_data; |
b80e6998 | 643 | unsigned long hv_err, cookie; |
b7c2a757 DM |
644 | struct ino_bucket *bucket; |
645 | struct irq_desc *desc; | |
42d5f99b | 646 | unsigned int virt_irq; |
b80e6998 DM |
647 | |
648 | bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); | |
649 | if (unlikely(!bucket)) | |
650 | return 0; | |
25ad403f DM |
651 | |
652 | /* The only reference we store to the IRQ bucket is | |
653 | * by physical address which kmemleak can't see, tell | |
654 | * it that this object explicitly is not a leak and | |
655 | * should be scanned. | |
656 | */ | |
657 | kmemleak_not_leak(bucket); | |
658 | ||
42d5f99b DM |
659 | __flush_dcache_range((unsigned long) bucket, |
660 | ((unsigned long) bucket + | |
661 | sizeof(struct ino_bucket))); | |
b80e6998 | 662 | |
256c1df3 | 663 | virt_irq = virt_irq_alloc(devhandle, devino); |
42d5f99b | 664 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
665 | |
666 | set_irq_chip_and_handler_name(virt_irq, &sun4v_virq, | |
667 | handle_fasteoi_irq, | |
668 | "IVEC"); | |
4a907dec | 669 | |
cae78728 SR |
670 | handler_data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
671 | if (unlikely(!handler_data)) | |
b80e6998 | 672 | return 0; |
4a907dec | 673 | |
b7c2a757 DM |
674 | /* In order to make the LDC channel startup sequence easier, |
675 | * especially wrt. locking, we do not let request_irq() enable | |
676 | * the interrupt. | |
677 | */ | |
678 | desc = irq_desc + virt_irq; | |
679 | desc->status |= IRQ_NOAUTOEN; | |
680 | ||
e6ebd529 | 681 | set_irq_data(virt_irq, handler_data); |
4a907dec | 682 | |
b80e6998 DM |
683 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
684 | * is done by hypervisor calls on sun4v platforms, not by direct | |
685 | * register accesses. | |
686 | */ | |
cae78728 SR |
687 | handler_data->imap = ~0UL; |
688 | handler_data->iclr = ~0UL; | |
b80e6998 DM |
689 | |
690 | cookie = ~__pa(bucket); | |
691 | hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie); | |
4a907dec DM |
692 | if (hv_err) { |
693 | prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " | |
694 | "err=%lu\n", devhandle, devino, hv_err); | |
695 | prom_halt(); | |
696 | } | |
697 | ||
42d5f99b | 698 | return virt_irq; |
4a907dec DM |
699 | } |
700 | ||
e18e2a00 DM |
701 | void ack_bad_irq(unsigned int virt_irq) |
702 | { | |
45b3f4cc | 703 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
ab66a50e | 704 | |
77182300 DM |
705 | if (!ino) |
706 | ino = 0xdeadbeef; | |
6a76267f | 707 | |
e18e2a00 DM |
708 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
709 | ino, virt_irq); | |
1da177e4 LT |
710 | } |
711 | ||
4f70f7a9 DM |
712 | void *hardirq_stack[NR_CPUS]; |
713 | void *softirq_stack[NR_CPUS]; | |
714 | ||
d4d1ec48 | 715 | void __irq_entry handler_irq(int pil, struct pt_regs *regs) |
1da177e4 | 716 | { |
eb2d8d60 | 717 | unsigned long pstate, bucket_pa; |
6d24c8dc | 718 | struct pt_regs *old_regs; |
4f70f7a9 | 719 | void *orig_sp; |
1da177e4 | 720 | |
d4d1ec48 | 721 | clear_softint(1 << pil); |
1da177e4 | 722 | |
6d24c8dc | 723 | old_regs = set_irq_regs(regs); |
1da177e4 | 724 | irq_enter(); |
1da177e4 | 725 | |
a650d383 DM |
726 | /* Grab an atomic snapshot of the pending IVECs. */ |
727 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
728 | "wrpr %0, %3, %%pstate\n\t" | |
729 | "ldx [%2], %1\n\t" | |
730 | "stx %%g0, [%2]\n\t" | |
731 | "wrpr %0, 0x0, %%pstate\n\t" | |
eb2d8d60 DM |
732 | : "=&r" (pstate), "=&r" (bucket_pa) |
733 | : "r" (irq_work_pa(smp_processor_id())), | |
a650d383 DM |
734 | "i" (PSTATE_IE) |
735 | : "memory"); | |
736 | ||
4f70f7a9 DM |
737 | orig_sp = set_hardirq_stack(); |
738 | ||
eb2d8d60 | 739 | while (bucket_pa) { |
8d57d3ad | 740 | struct irq_desc *desc; |
eb2d8d60 DM |
741 | unsigned long next_pa; |
742 | unsigned int virt_irq; | |
1da177e4 | 743 | |
42d5f99b DM |
744 | next_pa = bucket_get_chain_pa(bucket_pa); |
745 | virt_irq = bucket_get_virt_irq(bucket_pa); | |
746 | bucket_clear_chain_pa(bucket_pa); | |
fd0504c3 | 747 | |
8d57d3ad DM |
748 | desc = irq_desc + virt_irq; |
749 | ||
d0cac39e DM |
750 | if (!(desc->status & IRQ_DISABLED)) |
751 | desc->handle_irq(virt_irq, desc); | |
eb2d8d60 DM |
752 | |
753 | bucket_pa = next_pa; | |
1da177e4 | 754 | } |
e18e2a00 | 755 | |
4f70f7a9 DM |
756 | restore_hardirq_stack(orig_sp); |
757 | ||
1da177e4 | 758 | irq_exit(); |
6d24c8dc | 759 | set_irq_regs(old_regs); |
1da177e4 LT |
760 | } |
761 | ||
4f70f7a9 DM |
762 | void do_softirq(void) |
763 | { | |
764 | unsigned long flags; | |
765 | ||
766 | if (in_interrupt()) | |
767 | return; | |
768 | ||
769 | local_irq_save(flags); | |
770 | ||
771 | if (local_softirq_pending()) { | |
772 | void *orig_sp, *sp = softirq_stack[smp_processor_id()]; | |
773 | ||
774 | sp += THREAD_SIZE - 192 - STACK_BIAS; | |
775 | ||
776 | __asm__ __volatile__("mov %%sp, %0\n\t" | |
777 | "mov %1, %%sp" | |
778 | : "=&r" (orig_sp) | |
779 | : "r" (sp)); | |
780 | __do_softirq(); | |
781 | __asm__ __volatile__("mov %0, %%sp" | |
782 | : : "r" (orig_sp)); | |
783 | } | |
784 | ||
785 | local_irq_restore(flags); | |
786 | } | |
787 | ||
e0204409 DM |
788 | #ifdef CONFIG_HOTPLUG_CPU |
789 | void fixup_irqs(void) | |
790 | { | |
791 | unsigned int irq; | |
792 | ||
793 | for (irq = 0; irq < NR_IRQS; irq++) { | |
794 | unsigned long flags; | |
795 | ||
239007b8 | 796 | raw_spin_lock_irqsave(&irq_desc[irq].lock, flags); |
e0204409 DM |
797 | if (irq_desc[irq].action && |
798 | !(irq_desc[irq].status & IRQ_PER_CPU)) { | |
4832b992 SR |
799 | struct irq_data *data = irq_get_irq_data(irq); |
800 | ||
801 | if (data->chip->irq_set_affinity) | |
802 | data->chip->irq_set_affinity(data, | |
803 | data->affinity, | |
804 | false); | |
e0204409 | 805 | } |
239007b8 | 806 | raw_spin_unlock_irqrestore(&irq_desc[irq].lock, flags); |
e0204409 | 807 | } |
2eb2f779 DM |
808 | |
809 | tick_ops->disable_irq(); | |
e0204409 DM |
810 | } |
811 | #endif | |
812 | ||
cdd5186f DM |
813 | struct sun5_timer { |
814 | u64 count0; | |
815 | u64 limit0; | |
816 | u64 count1; | |
817 | u64 limit1; | |
818 | }; | |
1da177e4 | 819 | |
cdd5186f | 820 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
821 | static u64 prom_limit0, prom_limit1; |
822 | ||
823 | static void map_prom_timers(void) | |
824 | { | |
25c7581b | 825 | struct device_node *dp; |
6a23acf3 | 826 | const unsigned int *addr; |
1da177e4 LT |
827 | |
828 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
829 | dp = of_find_node_by_path("/"); |
830 | dp = dp->child; | |
831 | while (dp) { | |
832 | if (!strcmp(dp->name, "counter-timer")) | |
833 | break; | |
834 | dp = dp->sibling; | |
835 | } | |
1da177e4 LT |
836 | |
837 | /* Assume if node is not present, PROM uses different tick mechanism | |
838 | * which we should not care about. | |
839 | */ | |
25c7581b | 840 | if (!dp) { |
1da177e4 LT |
841 | prom_timers = (struct sun5_timer *) 0; |
842 | return; | |
843 | } | |
844 | ||
845 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
846 | addr = of_get_property(dp, "address", NULL); |
847 | if (!addr) { | |
1da177e4 LT |
848 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
849 | prom_timers = (struct sun5_timer *) 0; | |
850 | return; | |
851 | } | |
852 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
853 | } | |
854 | ||
855 | static void kill_prom_timer(void) | |
856 | { | |
857 | if (!prom_timers) | |
858 | return; | |
859 | ||
860 | /* Save them away for later. */ | |
861 | prom_limit0 = prom_timers->limit0; | |
862 | prom_limit1 = prom_timers->limit1; | |
863 | ||
864 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
865 | * We turn both off here just to be paranoid. | |
866 | */ | |
867 | prom_timers->limit0 = 0; | |
868 | prom_timers->limit1 = 0; | |
869 | ||
870 | /* Wheee, eat the interrupt packet too... */ | |
871 | __asm__ __volatile__( | |
872 | " mov 0x40, %%g2\n" | |
873 | " ldxa [%%g0] %0, %%g1\n" | |
874 | " ldxa [%%g2] %1, %%g1\n" | |
875 | " stxa %%g0, [%%g0] %0\n" | |
876 | " membar #Sync\n" | |
877 | : /* no outputs */ | |
878 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
879 | : "g1", "g2"); | |
880 | } | |
881 | ||
9843099f | 882 | void notrace init_irqwork_curcpu(void) |
1da177e4 | 883 | { |
1da177e4 LT |
884 | int cpu = hard_smp_processor_id(); |
885 | ||
eb2d8d60 | 886 | trap_block[cpu].irq_worklist_pa = 0UL; |
1da177e4 LT |
887 | } |
888 | ||
5cbc3073 DM |
889 | /* Please be very careful with register_one_mondo() and |
890 | * sun4v_register_mondo_queues(). | |
891 | * | |
892 | * On SMP this gets invoked from the CPU trampoline before | |
893 | * the cpu has fully taken over the trap table from OBP, | |
894 | * and it's kernel stack + %g6 thread register state is | |
895 | * not fully cooked yet. | |
896 | * | |
897 | * Therefore you cannot make any OBP calls, not even prom_printf, | |
898 | * from these two routines. | |
899 | */ | |
bd4352ca | 900 | static void __cpuinit notrace register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) |
ac29c11d | 901 | { |
5cbc3073 | 902 | unsigned long num_entries = (qmask + 1) / 64; |
94f8762d DM |
903 | unsigned long status; |
904 | ||
905 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
906 | if (status != HV_EOK) { | |
907 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
908 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
909 | prom_halt(); |
910 | } | |
911 | } | |
912 | ||
9843099f | 913 | void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 914 | { |
b5a37e96 DM |
915 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
916 | ||
5cbc3073 DM |
917 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
918 | tb->cpu_mondo_qmask); | |
919 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, | |
920 | tb->dev_mondo_qmask); | |
921 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, | |
922 | tb->resum_qmask); | |
923 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, | |
924 | tb->nonresum_qmask); | |
b5a37e96 DM |
925 | } |
926 | ||
14a2ff6e DM |
927 | /* Each queue region must be a power of 2 multiple of 64 bytes in |
928 | * size. The base real address must be aligned to the size of the | |
929 | * region. Thus, an 8KB queue must be 8KB aligned, for example. | |
930 | */ | |
931 | static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask) | |
b5a37e96 | 932 | { |
5cbc3073 | 933 | unsigned long size = PAGE_ALIGN(qmask + 1); |
14a2ff6e DM |
934 | unsigned long order = get_order(size); |
935 | unsigned long p; | |
5b0c0572 | 936 | |
14a2ff6e | 937 | p = __get_free_pages(GFP_KERNEL, order); |
5cbc3073 | 938 | if (!p) { |
14a2ff6e | 939 | prom_printf("SUN4V: Error, cannot allocate queue.\n"); |
5b0c0572 DM |
940 | prom_halt(); |
941 | } | |
942 | ||
5cbc3073 | 943 | *pa_ptr = __pa(p); |
5b0c0572 DM |
944 | } |
945 | ||
b434e719 | 946 | static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) |
1d2f1f90 DM |
947 | { |
948 | #ifdef CONFIG_SMP | |
14a2ff6e | 949 | unsigned long page; |
1d2f1f90 DM |
950 | |
951 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
952 | ||
14a2ff6e | 953 | page = get_zeroed_page(GFP_KERNEL); |
1d2f1f90 DM |
954 | if (!page) { |
955 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
956 | prom_halt(); | |
957 | } | |
958 | ||
959 | tb->cpu_mondo_block_pa = __pa(page); | |
960 | tb->cpu_list_pa = __pa(page + 64); | |
961 | #endif | |
962 | } | |
963 | ||
b434e719 DM |
964 | /* Allocate mondo and error queues for all possible cpus. */ |
965 | static void __init sun4v_init_mondo_queues(void) | |
ac29c11d | 966 | { |
b434e719 | 967 | int cpu; |
ac29c11d | 968 | |
b434e719 DM |
969 | for_each_possible_cpu(cpu) { |
970 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 971 | |
14a2ff6e DM |
972 | alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); |
973 | alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask); | |
974 | alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask); | |
975 | alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask); | |
976 | alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask); | |
977 | alloc_one_queue(&tb->nonresum_kernel_buf_pa, | |
978 | tb->nonresum_qmask); | |
43f58923 DM |
979 | } |
980 | } | |
981 | ||
982 | static void __init init_send_mondo_info(void) | |
983 | { | |
984 | int cpu; | |
985 | ||
986 | for_each_possible_cpu(cpu) { | |
987 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 988 | |
b434e719 | 989 | init_cpu_send_mondo_info(tb); |
72aff53f | 990 | } |
ac29c11d DM |
991 | } |
992 | ||
e18e2a00 DM |
993 | static struct irqaction timer_irq_action = { |
994 | .name = "timer", | |
995 | }; | |
996 | ||
1da177e4 LT |
997 | /* Only invoked on boot processor. */ |
998 | void __init init_IRQ(void) | |
999 | { | |
10397e40 DM |
1000 | unsigned long size; |
1001 | ||
1da177e4 LT |
1002 | map_prom_timers(); |
1003 | kill_prom_timer(); | |
1da177e4 | 1004 | |
10397e40 | 1005 | size = sizeof(struct ino_bucket) * NUM_IVECS; |
14a2ff6e | 1006 | ivector_table = kzalloc(size, GFP_KERNEL); |
10397e40 DM |
1007 | if (!ivector_table) { |
1008 | prom_printf("Fatal error, cannot allocate ivector_table\n"); | |
1009 | prom_halt(); | |
1010 | } | |
42d5f99b DM |
1011 | __flush_dcache_range((unsigned long) ivector_table, |
1012 | ((unsigned long) ivector_table) + size); | |
10397e40 DM |
1013 | |
1014 | ivector_table_pa = __pa(ivector_table); | |
eb2d8d60 | 1015 | |
ac29c11d | 1016 | if (tlb_type == hypervisor) |
b434e719 | 1017 | sun4v_init_mondo_queues(); |
ac29c11d | 1018 | |
43f58923 DM |
1019 | init_send_mondo_info(); |
1020 | ||
1021 | if (tlb_type == hypervisor) { | |
1022 | /* Load up the boot cpu's entries. */ | |
1023 | sun4v_register_mondo_queues(hard_smp_processor_id()); | |
1024 | } | |
1025 | ||
1da177e4 LT |
1026 | /* We need to clear any IRQ's pending in the soft interrupt |
1027 | * registers, a spurious one could be left around from the | |
1028 | * PROM timer which we just disabled. | |
1029 | */ | |
1030 | clear_softint(get_softint()); | |
1031 | ||
1032 | /* Now that ivector table is initialized, it is safe | |
1033 | * to receive IRQ vector traps. We will normally take | |
1034 | * one or two right now, in case some device PROM used | |
1035 | * to boot us wants to speak to us. We just ignore them. | |
1036 | */ | |
1037 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
1038 | "or %%g1, %0, %%g1\n\t" | |
1039 | "wrpr %%g1, 0x0, %%pstate" | |
1040 | : /* No outputs */ | |
1041 | : "i" (PSTATE_IE) | |
1042 | : "g1"); | |
1da177e4 | 1043 | |
e18e2a00 | 1044 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 1045 | } |