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5213a780 KE |
1 | /* |
2 | * Copyright (C) 2009 Daniel Hellstrom (daniel@gaisler.com) Aeroflex Gaisler AB | |
3 | * Copyright (C) 2009 Konrad Eisele (konrad@gaisler.com) Aeroflex Gaisler AB | |
4 | */ | |
5 | ||
6 | #include <linux/kernel.h> | |
5213a780 KE |
7 | #include <linux/errno.h> |
8 | #include <linux/mutex.h> | |
5213a780 KE |
9 | #include <linux/of.h> |
10 | #include <linux/of_platform.h> | |
11 | #include <linux/interrupt.h> | |
12 | #include <linux/of_device.h> | |
62f08283 TK |
13 | #include <linux/clocksource.h> |
14 | #include <linux/clockchips.h> | |
8401707f | 15 | |
5213a780 KE |
16 | #include <asm/oplib.h> |
17 | #include <asm/timer.h> | |
18 | #include <asm/prom.h> | |
19 | #include <asm/leon.h> | |
20 | #include <asm/leon_amba.h> | |
8401707f KE |
21 | #include <asm/traps.h> |
22 | #include <asm/cacheflush.h> | |
4c6773c3 | 23 | #include <asm/smp.h> |
01dae0f0 | 24 | #include <asm/setup.h> |
5213a780 | 25 | |
93bb32f6 | 26 | #include "kernel.h" |
5213a780 KE |
27 | #include "prom.h" |
28 | #include "irq.h" | |
29 | ||
53aea7ca DH |
30 | struct leon3_irqctrl_regs_map *leon3_irqctrl_regs; /* interrupt controller base address */ |
31 | struct leon3_gptimer_regs_map *leon3_gptimer_regs; /* timer controller base address */ | |
5213a780 KE |
32 | |
33 | int leondebug_irq_disable; | |
34 | int leon_debug_irqout; | |
35 | static int dummy_master_l10_counter; | |
7279b82c | 36 | unsigned long amba_system_id; |
d61a38b2 | 37 | static DEFINE_SPINLOCK(leon_irq_lock); |
5213a780 | 38 | |
53aea7ca | 39 | unsigned long leon3_gptimer_irq; /* interrupt controller irq number */ |
2791c1a4 | 40 | unsigned long leon3_gptimer_idx; /* Timer Index (0..6) within Timer Core */ |
2cf95304 | 41 | int leon3_ticker_irq; /* Timer ticker IRQ */ |
5213a780 | 42 | unsigned int sparc_leon_eirq; |
a481b5d0 | 43 | #define LEON_IMASK(cpu) (&leon3_irqctrl_regs->mask[cpu]) |
4c6773c3 DH |
44 | #define LEON_IACK (&leon3_irqctrl_regs->iclear) |
45 | #define LEON_DO_ACK_HW 1 | |
5213a780 | 46 | |
4c6773c3 DH |
47 | /* Return the last ACKed IRQ by the Extended IRQ controller. It has already |
48 | * been (automatically) ACKed when the CPU takes the trap. | |
49 | */ | |
50 | static inline unsigned int leon_eirq_get(int cpu) | |
5213a780 KE |
51 | { |
52 | return LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->intid[cpu]) & 0x1f; | |
53 | } | |
54 | ||
4c6773c3 DH |
55 | /* Handle one or multiple IRQs from the extended interrupt controller */ |
56 | static void leon_handle_ext_irq(unsigned int irq, struct irq_desc *desc) | |
5213a780 | 57 | { |
4c6773c3 | 58 | unsigned int eirq; |
01dae0f0 | 59 | int cpu = sparc_leon3_cpuid(); |
4c6773c3 DH |
60 | |
61 | eirq = leon_eirq_get(cpu); | |
62 | if ((eirq & 0x10) && irq_map[eirq]->irq) /* bit4 tells if IRQ happened */ | |
63 | generic_handle_irq(irq_map[eirq]->irq); | |
5213a780 KE |
64 | } |
65 | ||
66 | /* The extended IRQ controller has been found, this function registers it */ | |
4c6773c3 | 67 | void leon_eirq_setup(unsigned int eirq) |
5213a780 | 68 | { |
4c6773c3 DH |
69 | unsigned long mask, oldmask; |
70 | unsigned int veirq; | |
5213a780 | 71 | |
4c6773c3 DH |
72 | if (eirq < 1 || eirq > 0xf) { |
73 | printk(KERN_ERR "LEON EXT IRQ NUMBER BAD: %d\n", eirq); | |
74 | return; | |
5213a780 KE |
75 | } |
76 | ||
4c6773c3 DH |
77 | veirq = leon_build_device_irq(eirq, leon_handle_ext_irq, "extirq", 0); |
78 | ||
79 | /* | |
80 | * Unmask the Extended IRQ, the IRQs routed through the Ext-IRQ | |
81 | * controller have a mask-bit of their own, so this is safe. | |
82 | */ | |
83 | irq_link(veirq); | |
84 | mask = 1 << eirq; | |
01dae0f0 DH |
85 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(boot_cpu_id)); |
86 | LEON3_BYPASS_STORE_PA(LEON_IMASK(boot_cpu_id), (oldmask | mask)); | |
4c6773c3 | 87 | sparc_leon_eirq = eirq; |
5213a780 KE |
88 | } |
89 | ||
4ba22b16 | 90 | unsigned long leon_get_irqmask(unsigned int irq) |
5213a780 KE |
91 | { |
92 | unsigned long mask; | |
93 | ||
94 | if (!irq || ((irq > 0xf) && !sparc_leon_eirq) | |
95 | || ((irq > 0x1f) && sparc_leon_eirq)) { | |
96 | printk(KERN_ERR | |
97 | "leon_get_irqmask: false irq number: %d\n", irq); | |
98 | mask = 0; | |
99 | } else { | |
100 | mask = LEON_HARD_INT(irq); | |
101 | } | |
102 | return mask; | |
103 | } | |
104 | ||
5eb1f4fc DH |
105 | #ifdef CONFIG_SMP |
106 | static int irq_choose_cpu(const struct cpumask *affinity) | |
107 | { | |
108 | cpumask_t mask; | |
109 | ||
0b5f9c00 RR |
110 | cpumask_and(&mask, cpu_online_mask, affinity); |
111 | if (cpumask_equal(&mask, cpu_online_mask) || cpumask_empty(&mask)) | |
01dae0f0 | 112 | return boot_cpu_id; |
5eb1f4fc | 113 | else |
0b5f9c00 | 114 | return cpumask_first(&mask); |
5eb1f4fc DH |
115 | } |
116 | #else | |
01dae0f0 | 117 | #define irq_choose_cpu(affinity) boot_cpu_id |
5eb1f4fc DH |
118 | #endif |
119 | ||
120 | static int leon_set_affinity(struct irq_data *data, const struct cpumask *dest, | |
121 | bool force) | |
122 | { | |
123 | unsigned long mask, oldmask, flags; | |
124 | int oldcpu, newcpu; | |
125 | ||
126 | mask = (unsigned long)data->chip_data; | |
127 | oldcpu = irq_choose_cpu(data->affinity); | |
128 | newcpu = irq_choose_cpu(dest); | |
129 | ||
130 | if (oldcpu == newcpu) | |
131 | goto out; | |
132 | ||
133 | /* unmask on old CPU first before enabling on the selected CPU */ | |
134 | spin_lock_irqsave(&leon_irq_lock, flags); | |
135 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(oldcpu)); | |
136 | LEON3_BYPASS_STORE_PA(LEON_IMASK(oldcpu), (oldmask & ~mask)); | |
137 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(newcpu)); | |
138 | LEON3_BYPASS_STORE_PA(LEON_IMASK(newcpu), (oldmask | mask)); | |
139 | spin_unlock_irqrestore(&leon_irq_lock, flags); | |
140 | out: | |
141 | return IRQ_SET_MASK_OK; | |
142 | } | |
143 | ||
6baa9b20 | 144 | static void leon_unmask_irq(struct irq_data *data) |
5213a780 | 145 | { |
a481b5d0 | 146 | unsigned long mask, oldmask, flags; |
5eb1f4fc | 147 | int cpu; |
6baa9b20 SR |
148 | |
149 | mask = (unsigned long)data->chip_data; | |
5eb1f4fc | 150 | cpu = irq_choose_cpu(data->affinity); |
d61a38b2 | 151 | spin_lock_irqsave(&leon_irq_lock, flags); |
5eb1f4fc DH |
152 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(cpu)); |
153 | LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask | mask)); | |
d61a38b2 | 154 | spin_unlock_irqrestore(&leon_irq_lock, flags); |
5213a780 KE |
155 | } |
156 | ||
6baa9b20 | 157 | static void leon_mask_irq(struct irq_data *data) |
5213a780 | 158 | { |
a481b5d0 | 159 | unsigned long mask, oldmask, flags; |
5eb1f4fc | 160 | int cpu; |
6baa9b20 SR |
161 | |
162 | mask = (unsigned long)data->chip_data; | |
5eb1f4fc | 163 | cpu = irq_choose_cpu(data->affinity); |
d61a38b2 | 164 | spin_lock_irqsave(&leon_irq_lock, flags); |
5eb1f4fc DH |
165 | oldmask = LEON3_BYPASS_LOAD_PA(LEON_IMASK(cpu)); |
166 | LEON3_BYPASS_STORE_PA(LEON_IMASK(cpu), (oldmask & ~mask)); | |
d61a38b2 | 167 | spin_unlock_irqrestore(&leon_irq_lock, flags); |
5213a780 KE |
168 | } |
169 | ||
6baa9b20 SR |
170 | static unsigned int leon_startup_irq(struct irq_data *data) |
171 | { | |
172 | irq_link(data->irq); | |
173 | leon_unmask_irq(data); | |
174 | return 0; | |
175 | } | |
176 | ||
177 | static void leon_shutdown_irq(struct irq_data *data) | |
178 | { | |
179 | leon_mask_irq(data); | |
180 | irq_unlink(data->irq); | |
181 | } | |
182 | ||
4c6773c3 DH |
183 | /* Used by external level sensitive IRQ handlers on the LEON: ACK IRQ ctrl */ |
184 | static void leon_eoi_irq(struct irq_data *data) | |
185 | { | |
186 | unsigned long mask = (unsigned long)data->chip_data; | |
187 | ||
188 | if (mask & LEON_DO_ACK_HW) | |
189 | LEON3_BYPASS_STORE_PA(LEON_IACK, mask & ~LEON_DO_ACK_HW); | |
190 | } | |
191 | ||
6baa9b20 | 192 | static struct irq_chip leon_irq = { |
5eb1f4fc DH |
193 | .name = "leon", |
194 | .irq_startup = leon_startup_irq, | |
195 | .irq_shutdown = leon_shutdown_irq, | |
196 | .irq_mask = leon_mask_irq, | |
197 | .irq_unmask = leon_unmask_irq, | |
198 | .irq_eoi = leon_eoi_irq, | |
199 | .irq_set_affinity = leon_set_affinity, | |
6baa9b20 SR |
200 | }; |
201 | ||
4c6773c3 DH |
202 | /* |
203 | * Build a LEON IRQ for the edge triggered LEON IRQ controller: | |
204 | * Edge (normal) IRQ - handle_simple_irq, ack=DONT-CARE, never ack | |
205 | * Level IRQ (PCI|Level-GPIO) - handle_fasteoi_irq, ack=1, ack after ISR | |
206 | * Per-CPU Edge - handle_percpu_irq, ack=0 | |
207 | */ | |
208 | unsigned int leon_build_device_irq(unsigned int real_irq, | |
209 | irq_flow_handler_t flow_handler, | |
210 | const char *name, int do_ack) | |
6baa9b20 SR |
211 | { |
212 | unsigned int irq; | |
213 | unsigned long mask; | |
214 | ||
215 | irq = 0; | |
4ba22b16 | 216 | mask = leon_get_irqmask(real_irq); |
6baa9b20 SR |
217 | if (mask == 0) |
218 | goto out; | |
219 | ||
220 | irq = irq_alloc(real_irq, real_irq); | |
221 | if (irq == 0) | |
222 | goto out; | |
223 | ||
4c6773c3 DH |
224 | if (do_ack) |
225 | mask |= LEON_DO_ACK_HW; | |
226 | ||
6baa9b20 | 227 | irq_set_chip_and_handler_name(irq, &leon_irq, |
4c6773c3 | 228 | flow_handler, name); |
6baa9b20 SR |
229 | irq_set_chip_data(irq, (void *)mask); |
230 | ||
231 | out: | |
232 | return irq; | |
233 | } | |
234 | ||
4c6773c3 DH |
235 | static unsigned int _leon_build_device_irq(struct platform_device *op, |
236 | unsigned int real_irq) | |
237 | { | |
238 | return leon_build_device_irq(real_irq, handle_simple_irq, "edge", 0); | |
239 | } | |
240 | ||
5d07b786 DH |
241 | void leon_update_virq_handling(unsigned int virq, |
242 | irq_flow_handler_t flow_handler, | |
243 | const char *name, int do_ack) | |
244 | { | |
245 | unsigned long mask = (unsigned long)irq_get_chip_data(virq); | |
246 | ||
247 | mask &= ~LEON_DO_ACK_HW; | |
248 | if (do_ack) | |
249 | mask |= LEON_DO_ACK_HW; | |
250 | ||
251 | irq_set_chip_and_handler_name(virq, &leon_irq, | |
252 | flow_handler, name); | |
253 | irq_set_chip_data(virq, (void *)mask); | |
254 | } | |
255 | ||
62f08283 TK |
256 | static u32 leon_cycles_offset(void) |
257 | { | |
258 | u32 rld, val, off; | |
259 | rld = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].rld); | |
260 | val = LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val); | |
261 | off = rld - val; | |
262 | return rld - val; | |
263 | } | |
264 | ||
265 | #ifdef CONFIG_SMP | |
266 | ||
267 | /* smp clockevent irq */ | |
268 | irqreturn_t leon_percpu_timer_ce_interrupt(int irq, void *unused) | |
269 | { | |
270 | struct clock_event_device *ce; | |
271 | int cpu = smp_processor_id(); | |
272 | ||
273 | leon_clear_profile_irq(cpu); | |
274 | ||
275 | ce = &per_cpu(sparc32_clockevent, cpu); | |
276 | ||
277 | irq_enter(); | |
278 | if (ce->event_handler) | |
279 | ce->event_handler(ce); | |
280 | irq_exit(); | |
281 | ||
282 | return IRQ_HANDLED; | |
283 | } | |
284 | ||
285 | #endif /* CONFIG_SMP */ | |
286 | ||
287 | void __init leon_init_timers(void) | |
5213a780 | 288 | { |
4c6773c3 | 289 | int irq, eirq; |
2791c1a4 | 290 | struct device_node *rootnp, *np, *nnp; |
53aea7ca DH |
291 | struct property *pp; |
292 | int len; | |
01dae0f0 | 293 | int icsel; |
2791c1a4 | 294 | int ampopts; |
6baa9b20 | 295 | int err; |
5213a780 | 296 | |
62f08283 TK |
297 | sparc_config.get_cycles_offset = leon_cycles_offset; |
298 | sparc_config.cs_period = 1000000 / HZ; | |
299 | sparc_config.features |= FEAT_L10_CLOCKSOURCE; | |
300 | ||
301 | #ifndef CONFIG_SMP | |
302 | sparc_config.features |= FEAT_L10_CLOCKEVENT; | |
303 | #endif | |
304 | ||
5213a780 KE |
305 | leondebug_irq_disable = 0; |
306 | leon_debug_irqout = 0; | |
307 | master_l10_counter = (unsigned int *)&dummy_master_l10_counter; | |
308 | dummy_master_l10_counter = 0; | |
309 | ||
53aea7ca DH |
310 | rootnp = of_find_node_by_path("/ambapp0"); |
311 | if (!rootnp) | |
312 | goto bad; | |
7279b82c DH |
313 | |
314 | /* Find System ID: GRLIB build ID and optional CHIP ID */ | |
315 | pp = of_find_property(rootnp, "systemid", &len); | |
316 | if (pp) | |
317 | amba_system_id = *(unsigned long *)pp->value; | |
318 | ||
319 | /* Find IRQMP IRQ Controller Registers base adr otherwise bail out */ | |
53aea7ca | 320 | np = of_find_node_by_name(rootnp, "GAISLER_IRQMP"); |
9742e72c DH |
321 | if (!np) { |
322 | np = of_find_node_by_name(rootnp, "01_00d"); | |
323 | if (!np) | |
324 | goto bad; | |
325 | } | |
53aea7ca DH |
326 | pp = of_find_property(np, "reg", &len); |
327 | if (!pp) | |
328 | goto bad; | |
329 | leon3_irqctrl_regs = *(struct leon3_irqctrl_regs_map **)pp->value; | |
330 | ||
331 | /* Find GPTIMER Timer Registers base address otherwise bail out. */ | |
2791c1a4 DH |
332 | nnp = rootnp; |
333 | do { | |
334 | np = of_find_node_by_name(nnp, "GAISLER_GPTIMER"); | |
335 | if (!np) { | |
336 | np = of_find_node_by_name(nnp, "01_011"); | |
337 | if (!np) | |
338 | goto bad; | |
339 | } | |
340 | ||
341 | ampopts = 0; | |
342 | pp = of_find_property(np, "ampopts", &len); | |
343 | if (pp) { | |
344 | ampopts = *(int *)pp->value; | |
345 | if (ampopts == 0) { | |
346 | /* Skip this instance, resource already | |
347 | * allocated by other OS */ | |
348 | nnp = np; | |
349 | continue; | |
350 | } | |
351 | } | |
352 | ||
353 | /* Select Timer-Instance on Timer Core. Default is zero */ | |
354 | leon3_gptimer_idx = ampopts & 0x7; | |
355 | ||
356 | pp = of_find_property(np, "reg", &len); | |
357 | if (pp) | |
358 | leon3_gptimer_regs = *(struct leon3_gptimer_regs_map **) | |
359 | pp->value; | |
360 | pp = of_find_property(np, "interrupts", &len); | |
361 | if (pp) | |
362 | leon3_gptimer_irq = *(unsigned int *)pp->value; | |
363 | } while (0); | |
53aea7ca | 364 | |
a481b5d0 DH |
365 | if (!(leon3_gptimer_regs && leon3_irqctrl_regs && leon3_gptimer_irq)) |
366 | goto bad; | |
367 | ||
368 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].val, 0); | |
369 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].rld, | |
370 | (((1000000 / HZ) - 1))); | |
371 | LEON3_BYPASS_STORE_PA( | |
2791c1a4 | 372 | &leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, 0); |
5213a780 | 373 | |
8401707f | 374 | #ifdef CONFIG_SMP |
a481b5d0 | 375 | leon3_ticker_irq = leon3_gptimer_irq + 1 + leon3_gptimer_idx; |
8401707f | 376 | |
a481b5d0 DH |
377 | if (!(LEON3_BYPASS_LOAD_PA(&leon3_gptimer_regs->config) & |
378 | (1<<LEON3_GPTIMER_SEPIRQ))) { | |
379 | printk(KERN_ERR "timer not configured with separate irqs\n"); | |
380 | BUG(); | |
5213a780 KE |
381 | } |
382 | ||
a481b5d0 DH |
383 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx+1].val, |
384 | 0); | |
385 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx+1].rld, | |
386 | (((1000000/HZ) - 1))); | |
387 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx+1].ctrl, | |
388 | 0); | |
389 | #endif | |
390 | ||
391 | /* | |
392 | * The IRQ controller may (if implemented) consist of multiple | |
393 | * IRQ controllers, each mapped on a 4Kb boundary. | |
394 | * Each CPU may be routed to different IRQCTRLs, however | |
395 | * we assume that all CPUs (in SMP system) is routed to the | |
396 | * same IRQ Controller, and for non-SMP only one IRQCTRL is | |
397 | * accessed anyway. | |
398 | * In AMP systems, Linux must run on CPU0 for the time being. | |
399 | */ | |
01dae0f0 DH |
400 | icsel = LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->icsel[boot_cpu_id/8]); |
401 | icsel = (icsel >> ((7 - (boot_cpu_id&0x7)) * 4)) & 0xf; | |
a481b5d0 DH |
402 | leon3_irqctrl_regs += icsel; |
403 | ||
970def65 DH |
404 | /* Mask all IRQs on boot-cpu IRQ controller */ |
405 | LEON3_BYPASS_STORE_PA(&leon3_irqctrl_regs->mask[boot_cpu_id], 0); | |
406 | ||
a481b5d0 DH |
407 | /* Probe extended IRQ controller */ |
408 | eirq = (LEON3_BYPASS_LOAD_PA(&leon3_irqctrl_regs->mpstatus) | |
409 | >> 16) & 0xf; | |
410 | if (eirq != 0) | |
411 | leon_eirq_setup(eirq); | |
412 | ||
4c6773c3 | 413 | irq = _leon_build_device_irq(NULL, leon3_gptimer_irq+leon3_gptimer_idx); |
62f08283 | 414 | err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL); |
6baa9b20 | 415 | if (err) { |
a481b5d0 | 416 | printk(KERN_ERR "unable to attach timer IRQ%d\n", irq); |
5213a780 KE |
417 | prom_halt(); |
418 | } | |
419 | ||
10f0d07c DH |
420 | #ifdef CONFIG_SMP |
421 | { | |
422 | unsigned long flags; | |
423 | ||
424 | /* | |
425 | * In SMP, sun4m adds a IPI handler to IRQ trap handler that | |
426 | * LEON never must take, sun4d and LEON overwrites the branch | |
427 | * with a NOP. | |
428 | */ | |
429 | local_irq_save(flags); | |
430 | patchme_maybe_smp_msg[0] = 0x01000000; /* NOP out the branch */ | |
5d83d666 | 431 | local_ops->cache_all(); |
10f0d07c DH |
432 | local_irq_restore(flags); |
433 | } | |
434 | #endif | |
435 | ||
a481b5d0 DH |
436 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx].ctrl, |
437 | LEON3_GPTIMER_EN | | |
438 | LEON3_GPTIMER_RL | | |
439 | LEON3_GPTIMER_LD | | |
440 | LEON3_GPTIMER_IRQEN); | |
8401707f KE |
441 | |
442 | #ifdef CONFIG_SMP | |
a481b5d0 DH |
443 | /* Install per-cpu IRQ handler for broadcasted ticker */ |
444 | irq = leon_build_device_irq(leon3_ticker_irq, handle_percpu_irq, | |
445 | "per-cpu", 0); | |
62f08283 | 446 | err = request_irq(irq, leon_percpu_timer_ce_interrupt, |
a481b5d0 DH |
447 | IRQF_PERCPU | IRQF_TIMER, "ticker", |
448 | NULL); | |
449 | if (err) { | |
450 | printk(KERN_ERR "unable to attach ticker IRQ%d\n", irq); | |
451 | prom_halt(); | |
452 | } | |
2cf95304 | 453 | |
a481b5d0 DH |
454 | LEON3_BYPASS_STORE_PA(&leon3_gptimer_regs->e[leon3_gptimer_idx+1].ctrl, |
455 | LEON3_GPTIMER_EN | | |
456 | LEON3_GPTIMER_RL | | |
457 | LEON3_GPTIMER_LD | | |
458 | LEON3_GPTIMER_IRQEN); | |
8401707f | 459 | #endif |
53aea7ca DH |
460 | return; |
461 | bad: | |
462 | printk(KERN_ERR "No Timer/irqctrl found\n"); | |
463 | BUG(); | |
464 | return; | |
5213a780 KE |
465 | } |
466 | ||
08c9388f | 467 | static void leon_clear_clock_irq(void) |
5213a780 KE |
468 | { |
469 | } | |
470 | ||
08c9388f | 471 | static void leon_load_profile_irq(int cpu, unsigned int limit) |
5213a780 | 472 | { |
5213a780 KE |
473 | } |
474 | ||
5213a780 KE |
475 | void __init leon_trans_init(struct device_node *dp) |
476 | { | |
477 | if (strcmp(dp->type, "cpu") == 0 && strcmp(dp->name, "<NULL>") == 0) { | |
478 | struct property *p; | |
479 | p = of_find_property(dp, "mid", (void *)0); | |
480 | if (p) { | |
481 | int mid; | |
482 | dp->name = prom_early_alloc(5 + 1); | |
483 | memcpy(&mid, p->value, p->length); | |
484 | sprintf((char *)dp->name, "cpu%.2d", mid); | |
485 | } | |
486 | } | |
487 | } | |
488 | ||
8401707f | 489 | #ifdef CONFIG_SMP |
8401707f KE |
490 | void leon_clear_profile_irq(int cpu) |
491 | { | |
492 | } | |
493 | ||
494 | void leon_enable_irq_cpu(unsigned int irq_nr, unsigned int cpu) | |
495 | { | |
496 | unsigned long mask, flags, *addr; | |
4ba22b16 | 497 | mask = leon_get_irqmask(irq_nr); |
d61a38b2 | 498 | spin_lock_irqsave(&leon_irq_lock, flags); |
a481b5d0 DH |
499 | addr = (unsigned long *)LEON_IMASK(cpu); |
500 | LEON3_BYPASS_STORE_PA(addr, (LEON3_BYPASS_LOAD_PA(addr) | mask)); | |
d61a38b2 | 501 | spin_unlock_irqrestore(&leon_irq_lock, flags); |
8401707f KE |
502 | } |
503 | ||
504 | #endif | |
505 | ||
5213a780 KE |
506 | void __init leon_init_IRQ(void) |
507 | { | |
472bc4f2 SR |
508 | sparc_config.init_timers = leon_init_timers; |
509 | sparc_config.build_device_irq = _leon_build_device_irq; | |
08c9388f SR |
510 | sparc_config.clock_rate = 1000000; |
511 | sparc_config.clear_clock_irq = leon_clear_clock_irq; | |
512 | sparc_config.load_profile_irq = leon_load_profile_irq; | |
5213a780 | 513 | } |