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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
9fd8b647 | 2 | /* pci_impl.h: Helper definitions for PCI controller support. |
1da177e4 | 3 | * |
9fd8b647 | 4 | * Copyright (C) 1999, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
5 | */ |
6 | ||
7 | #ifndef PCI_IMPL_H | |
8 | #define PCI_IMPL_H | |
9 | ||
10 | #include <linux/types.h> | |
11 | #include <linux/spinlock.h> | |
c57c2ffb DM |
12 | #include <linux/pci.h> |
13 | #include <linux/msi.h> | |
22fecbae | 14 | #include <linux/of_device.h> |
1da177e4 | 15 | #include <asm/io.h> |
de8d28b1 | 16 | #include <asm/prom.h> |
c57c2ffb DM |
17 | #include <asm/iommu.h> |
18 | ||
19 | /* The abstraction used here is that there are PCI controllers, | |
20 | * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules | |
21 | * underneath. Each PCI bus module uses an IOMMU (shared by both | |
22 | * PBMs of a controller, or per-PBM), and if a streaming buffer | |
23 | * is present, each PCI bus module has it's own. (ie. the IOMMU | |
24 | * might be shared between PBMs, the STC is never shared) | |
25 | * Furthermore, each PCI bus module controls it's own autonomous | |
26 | * PCI bus. | |
27 | */ | |
28 | ||
29 | #define PCI_STC_FLUSHFLAG_INIT(STC) \ | |
30 | (*((STC)->strbuf_flushflag) = 0UL) | |
31 | #define PCI_STC_FLUSHFLAG_SET(STC) \ | |
32 | (*((STC)->strbuf_flushflag) != 0UL) | |
33 | ||
759f89e0 DM |
34 | #ifdef CONFIG_PCI_MSI |
35 | struct pci_pbm_info; | |
36 | struct sparc64_msiq_ops { | |
37 | int (*get_head)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
38 | unsigned long *head); | |
39 | int (*dequeue_msi)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
40 | unsigned long *head, unsigned long *msi); | |
41 | int (*set_head)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
42 | unsigned long head); | |
43 | int (*msi_setup)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
44 | unsigned long msi, int is_msi64); | |
45 | int (*msi_teardown)(struct pci_pbm_info *pbm, unsigned long msi); | |
46 | int (*msiq_alloc)(struct pci_pbm_info *pbm); | |
47 | void (*msiq_free)(struct pci_pbm_info *pbm); | |
48 | int (*msiq_build_irq)(struct pci_pbm_info *pbm, unsigned long msiqid, | |
49 | unsigned long devino); | |
50 | }; | |
51 | ||
2e74a74f SR |
52 | void sparc64_pbm_msi_init(struct pci_pbm_info *pbm, |
53 | const struct sparc64_msiq_ops *ops); | |
759f89e0 DM |
54 | |
55 | struct sparc64_msiq_cookie { | |
56 | struct pci_pbm_info *pbm; | |
57 | unsigned long msiqid; | |
58 | }; | |
59 | #endif | |
60 | ||
c57c2ffb DM |
61 | struct pci_pbm_info { |
62 | struct pci_pbm_info *next; | |
d3ae4b5b | 63 | struct pci_pbm_info *sibling; |
c57c2ffb DM |
64 | int index; |
65 | ||
c57c2ffb DM |
66 | /* Physical address base of controller registers. */ |
67 | unsigned long controller_regs; | |
68 | ||
69 | /* Physical address base of PBM registers. */ | |
70 | unsigned long pbm_regs; | |
71 | ||
72 | /* Physical address of DMA sync register, if any. */ | |
73 | unsigned long sync_reg; | |
74 | ||
75 | /* Opaque 32-bit system bus Port ID. */ | |
76 | u32 portid; | |
77 | ||
78 | /* Opaque 32-bit handle used for hypervisor calls. */ | |
79 | u32 devhandle; | |
80 | ||
81 | /* Chipset version information. */ | |
82 | int chip_type; | |
83 | #define PBM_CHIP_TYPE_SABRE 1 | |
84 | #define PBM_CHIP_TYPE_PSYCHO 2 | |
85 | #define PBM_CHIP_TYPE_SCHIZO 3 | |
86 | #define PBM_CHIP_TYPE_SCHIZO_PLUS 4 | |
87 | #define PBM_CHIP_TYPE_TOMATILLO 5 | |
88 | int chip_version; | |
89 | int chip_revision; | |
90 | ||
91 | /* Name used for top-level resources. */ | |
c22618a1 | 92 | const char *name; |
c57c2ffb DM |
93 | |
94 | /* OBP specific information. */ | |
cd4cd730 | 95 | struct platform_device *op; |
c57c2ffb DM |
96 | u64 ino_bitmap; |
97 | ||
98 | /* PBM I/O and Memory space resources. */ | |
99 | struct resource io_space; | |
100 | struct resource mem_space; | |
af86fa40 | 101 | struct resource mem64_space; |
3f1b540d | 102 | struct resource busn; |
c57c2ffb DM |
103 | |
104 | /* Base of PCI Config space, can be per-PBM or shared. */ | |
105 | unsigned long config_space; | |
106 | ||
ca3dd88e DM |
107 | /* This will be 12 on PCI-E controllers, 8 elsewhere. */ |
108 | unsigned long config_space_reg_bits; | |
109 | ||
d3ae4b5b DM |
110 | unsigned long pci_afsr; |
111 | unsigned long pci_afar; | |
112 | unsigned long pci_csr; | |
113 | ||
c57c2ffb DM |
114 | /* State of 66MHz capabilities on this PBM. */ |
115 | int is_66mhz_capable; | |
116 | int all_devs_66mhz; | |
117 | ||
118 | #ifdef CONFIG_PCI_MSI | |
119 | /* MSI info. */ | |
120 | u32 msiq_num; | |
121 | u32 msiq_ent_count; | |
122 | u32 msiq_first; | |
123 | u32 msiq_first_devino; | |
759f89e0 DM |
124 | u32 msiq_rotor; |
125 | struct sparc64_msiq_cookie *msiq_irq_cookies; | |
c57c2ffb DM |
126 | u32 msi_num; |
127 | u32 msi_first; | |
128 | u32 msi_data_mask; | |
129 | u32 msix_data_width; | |
130 | u64 msi32_start; | |
131 | u64 msi64_start; | |
132 | u32 msi32_len; | |
133 | u32 msi64_len; | |
134 | void *msi_queues; | |
135 | unsigned long *msi_bitmap; | |
759f89e0 | 136 | unsigned int *msi_irq_table; |
44ed3c0c | 137 | int (*setup_msi_irq)(unsigned int *irq_p, struct pci_dev *pdev, |
c57c2ffb | 138 | struct msi_desc *entry); |
44ed3c0c | 139 | void (*teardown_msi_irq)(unsigned int irq, struct pci_dev *pdev); |
759f89e0 | 140 | const struct sparc64_msiq_ops *msi_ops; |
c57c2ffb DM |
141 | #endif /* !(CONFIG_PCI_MSI) */ |
142 | ||
143 | /* This PBM's streaming buffer. */ | |
144 | struct strbuf stc; | |
145 | ||
146 | /* IOMMU state, potentially shared by both PBM segments. */ | |
147 | struct iommu *iommu; | |
148 | ||
149 | /* Now things for the actual PCI bus probes. */ | |
150 | unsigned int pci_first_busno; | |
151 | unsigned int pci_last_busno; | |
152 | struct pci_bus *pci_bus; | |
c57c2ffb | 153 | struct pci_ops *pci_ops; |
c1b1a5f1 DM |
154 | |
155 | int numa_node; | |
c57c2ffb DM |
156 | }; |
157 | ||
34768bc8 | 158 | extern struct pci_pbm_info *pci_pbm_root; |
1da177e4 | 159 | |
6c108f12 | 160 | extern int pci_num_pbms; |
1da177e4 LT |
161 | |
162 | /* PCI bus scanning and fixup support. */ | |
2e74a74f SR |
163 | void pci_get_pbm_props(struct pci_pbm_info *pbm); |
164 | struct pci_bus *pci_scan_one_pbm(struct pci_pbm_info *pbm, | |
165 | struct device *parent); | |
166 | void pci_determine_mem_io_space(struct pci_pbm_info *pbm); | |
1da177e4 LT |
167 | |
168 | /* Error reporting support. */ | |
2e74a74f SR |
169 | void pci_scan_for_target_abort(struct pci_pbm_info *, struct pci_bus *); |
170 | void pci_scan_for_master_abort(struct pci_pbm_info *, struct pci_bus *); | |
171 | void pci_scan_for_parity_error(struct pci_pbm_info *, struct pci_bus *); | |
1da177e4 LT |
172 | |
173 | /* Configuration space access. */ | |
2e74a74f SR |
174 | void pci_config_read8(u8 *addr, u8 *ret); |
175 | void pci_config_read16(u16 *addr, u16 *ret); | |
176 | void pci_config_read32(u32 *addr, u32 *ret); | |
177 | void pci_config_write8(u8 *addr, u8 val); | |
178 | void pci_config_write16(u16 *addr, u16 val); | |
179 | void pci_config_write32(u32 *addr, u32 val); | |
1da177e4 | 180 | |
ca3dd88e DM |
181 | extern struct pci_ops sun4u_pci_ops; |
182 | extern struct pci_ops sun4v_pci_ops; | |
183 | ||
77d10d0e DM |
184 | extern volatile int pci_poke_in_progress; |
185 | extern volatile int pci_poke_cpu; | |
186 | extern volatile int pci_poke_faulted; | |
187 | ||
1da177e4 | 188 | #endif /* !(PCI_IMPL_H) */ |