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cdd6c482 | 1 | /* Performance event support for sparc64. |
59abbd1e | 2 | * |
4f6dbe4a | 3 | * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net> |
59abbd1e | 4 | * |
cdd6c482 | 5 | * This code is based almost entirely upon the x86 perf event |
59abbd1e DM |
6 | * code, which is: |
7 | * | |
8 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
9 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
10 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
11 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
12 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
59abbd1e | 16 | #include <linux/kprobes.h> |
667f0cee | 17 | #include <linux/ftrace.h> |
59abbd1e DM |
18 | #include <linux/kernel.h> |
19 | #include <linux/kdebug.h> | |
20 | #include <linux/mutex.h> | |
21 | ||
4f6dbe4a | 22 | #include <asm/stacktrace.h> |
59abbd1e | 23 | #include <asm/cpudata.h> |
4f6dbe4a | 24 | #include <asm/uaccess.h> |
60063497 | 25 | #include <linux/atomic.h> |
59abbd1e DM |
26 | #include <asm/nmi.h> |
27 | #include <asm/pcr.h> | |
d550bbd4 | 28 | #include <asm/cacheflush.h> |
59abbd1e | 29 | |
cb1b8209 | 30 | #include "kernel.h" |
4f6dbe4a DM |
31 | #include "kstack.h" |
32 | ||
59abbd1e DM |
33 | /* Sparc64 chips have two performance counters, 32-bits each, with |
34 | * overflow interrupts generated on transition from 0xffffffff to 0. | |
35 | * The counters are accessed in one go using a 64-bit register. | |
36 | * | |
37 | * Both counters are controlled using a single control register. The | |
38 | * only way to stop all sampling is to clear all of the context (user, | |
39 | * supervisor, hypervisor) sampling enable bits. But these bits apply | |
40 | * to both counters, thus the two counters can't be enabled/disabled | |
41 | * individually. | |
42 | * | |
43 | * The control register has two event fields, one for each of the two | |
44 | * counters. It's thus nearly impossible to have one counter going | |
45 | * while keeping the other one stopped. Therefore it is possible to | |
46 | * get overflow interrupts for counters not currently "in use" and | |
47 | * that condition must be checked in the overflow interrupt handler. | |
48 | * | |
49 | * So we use a hack, in that we program inactive counters with the | |
50 | * "sw_count0" and "sw_count1" events. These count how many times | |
51 | * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an | |
52 | * unusual way to encode a NOP and therefore will not trigger in | |
53 | * normal code. | |
54 | */ | |
55 | ||
cdd6c482 | 56 | #define MAX_HWEVENTS 2 |
59abbd1e DM |
57 | #define MAX_PERIOD ((1UL << 32) - 1) |
58 | ||
59 | #define PIC_UPPER_INDEX 0 | |
60 | #define PIC_LOWER_INDEX 1 | |
e7bef6b0 | 61 | #define PIC_NO_INDEX -1 |
59abbd1e | 62 | |
cdd6c482 | 63 | struct cpu_hw_events { |
e7bef6b0 DM |
64 | /* Number of events currently scheduled onto this cpu. |
65 | * This tells how many entries in the arrays below | |
66 | * are valid. | |
67 | */ | |
68 | int n_events; | |
69 | ||
70 | /* Number of new events added since the last hw_perf_disable(). | |
71 | * This works because the perf event layer always adds new | |
72 | * events inside of a perf_{disable,enable}() sequence. | |
73 | */ | |
74 | int n_added; | |
75 | ||
76 | /* Array of events current scheduled on this cpu. */ | |
77 | struct perf_event *event[MAX_HWEVENTS]; | |
78 | ||
79 | /* Array of encoded longs, specifying the %pcr register | |
80 | * encoding and the mask of PIC counters this even can | |
81 | * be scheduled on. See perf_event_encode() et al. | |
82 | */ | |
83 | unsigned long events[MAX_HWEVENTS]; | |
84 | ||
85 | /* The current counter index assigned to an event. When the | |
86 | * event hasn't been programmed into the cpu yet, this will | |
87 | * hold PIC_NO_INDEX. The event->hw.idx value tells us where | |
88 | * we ought to schedule the event. | |
89 | */ | |
90 | int current_idx[MAX_HWEVENTS]; | |
91 | ||
92 | /* Software copy of %pcr register on this cpu. */ | |
d1751388 | 93 | u64 pcr; |
e7bef6b0 DM |
94 | |
95 | /* Enabled/disable state. */ | |
d1751388 | 96 | int enabled; |
a13c3afd LM |
97 | |
98 | unsigned int group_flag; | |
59abbd1e | 99 | }; |
cdd6c482 | 100 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, }; |
59abbd1e | 101 | |
e7bef6b0 DM |
102 | /* An event map describes the characteristics of a performance |
103 | * counter event. In particular it gives the encoding as well as | |
104 | * a mask telling which counters the event can be measured on. | |
105 | */ | |
59abbd1e DM |
106 | struct perf_event_map { |
107 | u16 encoding; | |
108 | u8 pic_mask; | |
109 | #define PIC_NONE 0x00 | |
110 | #define PIC_UPPER 0x01 | |
111 | #define PIC_LOWER 0x02 | |
112 | }; | |
113 | ||
e7bef6b0 | 114 | /* Encode a perf_event_map entry into a long. */ |
a72a8a5f DM |
115 | static unsigned long perf_event_encode(const struct perf_event_map *pmap) |
116 | { | |
117 | return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask; | |
118 | } | |
119 | ||
e7bef6b0 DM |
120 | static u8 perf_event_get_msk(unsigned long val) |
121 | { | |
122 | return val & 0xff; | |
123 | } | |
124 | ||
125 | static u64 perf_event_get_enc(unsigned long val) | |
a72a8a5f | 126 | { |
e7bef6b0 | 127 | return val >> 16; |
a72a8a5f DM |
128 | } |
129 | ||
2ce4da2e DM |
130 | #define C(x) PERF_COUNT_HW_CACHE_##x |
131 | ||
132 | #define CACHE_OP_UNSUPPORTED 0xfffe | |
133 | #define CACHE_OP_NONSENSE 0xffff | |
134 | ||
135 | typedef struct perf_event_map cache_map_t | |
136 | [PERF_COUNT_HW_CACHE_MAX] | |
137 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
138 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
139 | ||
59abbd1e DM |
140 | struct sparc_pmu { |
141 | const struct perf_event_map *(*event_map)(int); | |
2ce4da2e | 142 | const cache_map_t *cache_map; |
59abbd1e DM |
143 | int max_events; |
144 | int upper_shift; | |
145 | int lower_shift; | |
146 | int event_mask; | |
91b9286d | 147 | int hv_bit; |
496c07e3 | 148 | int irq_bit; |
660d1376 DM |
149 | int upper_nop; |
150 | int lower_nop; | |
b38e99f5 DM |
151 | unsigned int flags; |
152 | #define SPARC_PMU_ALL_EXCLUDES_SAME 0x00000001 | |
153 | #define SPARC_PMU_HAS_CONFLICTS 0x00000002 | |
59abbd1e DM |
154 | }; |
155 | ||
28e8f9be | 156 | static const struct perf_event_map ultra3_perfmon_event_map[] = { |
59abbd1e DM |
157 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER }, |
158 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER }, | |
159 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER }, | |
160 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER }, | |
161 | }; | |
162 | ||
28e8f9be | 163 | static const struct perf_event_map *ultra3_event_map(int event_id) |
59abbd1e | 164 | { |
28e8f9be | 165 | return &ultra3_perfmon_event_map[event_id]; |
59abbd1e DM |
166 | } |
167 | ||
28e8f9be | 168 | static const cache_map_t ultra3_cache_map = { |
2ce4da2e DM |
169 | [C(L1D)] = { |
170 | [C(OP_READ)] = { | |
171 | [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, | |
172 | [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, | |
173 | }, | |
174 | [C(OP_WRITE)] = { | |
175 | [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER }, | |
176 | [C(RESULT_MISS)] = { 0x0a, PIC_UPPER }, | |
177 | }, | |
178 | [C(OP_PREFETCH)] = { | |
179 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
180 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
181 | }, | |
182 | }, | |
183 | [C(L1I)] = { | |
184 | [C(OP_READ)] = { | |
185 | [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, | |
186 | [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, | |
187 | }, | |
188 | [ C(OP_WRITE) ] = { | |
189 | [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, | |
190 | [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, | |
191 | }, | |
192 | [ C(OP_PREFETCH) ] = { | |
193 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
194 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
195 | }, | |
196 | }, | |
197 | [C(LL)] = { | |
198 | [C(OP_READ)] = { | |
199 | [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, }, | |
200 | [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, }, | |
201 | }, | |
202 | [C(OP_WRITE)] = { | |
203 | [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER }, | |
204 | [C(RESULT_MISS)] = { 0x0c, PIC_UPPER }, | |
205 | }, | |
206 | [C(OP_PREFETCH)] = { | |
207 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
208 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
209 | }, | |
210 | }, | |
211 | [C(DTLB)] = { | |
212 | [C(OP_READ)] = { | |
213 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
214 | [C(RESULT_MISS)] = { 0x12, PIC_UPPER, }, | |
215 | }, | |
216 | [ C(OP_WRITE) ] = { | |
217 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
218 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
219 | }, | |
220 | [ C(OP_PREFETCH) ] = { | |
221 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
222 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
223 | }, | |
224 | }, | |
225 | [C(ITLB)] = { | |
226 | [C(OP_READ)] = { | |
227 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
228 | [C(RESULT_MISS)] = { 0x11, PIC_UPPER, }, | |
229 | }, | |
230 | [ C(OP_WRITE) ] = { | |
231 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
232 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
233 | }, | |
234 | [ C(OP_PREFETCH) ] = { | |
235 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
236 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
237 | }, | |
238 | }, | |
239 | [C(BPU)] = { | |
240 | [C(OP_READ)] = { | |
241 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
242 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
243 | }, | |
244 | [ C(OP_WRITE) ] = { | |
245 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
246 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
247 | }, | |
248 | [ C(OP_PREFETCH) ] = { | |
249 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
250 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
251 | }, | |
252 | }, | |
89d6c0b5 PZ |
253 | [C(NODE)] = { |
254 | [C(OP_READ)] = { | |
255 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
256 | [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
257 | }, | |
258 | [ C(OP_WRITE) ] = { | |
259 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
260 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
261 | }, | |
262 | [ C(OP_PREFETCH) ] = { | |
263 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
264 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
265 | }, | |
266 | }, | |
2ce4da2e DM |
267 | }; |
268 | ||
28e8f9be DM |
269 | static const struct sparc_pmu ultra3_pmu = { |
270 | .event_map = ultra3_event_map, | |
271 | .cache_map = &ultra3_cache_map, | |
272 | .max_events = ARRAY_SIZE(ultra3_perfmon_event_map), | |
59abbd1e DM |
273 | .upper_shift = 11, |
274 | .lower_shift = 4, | |
275 | .event_mask = 0x3f, | |
660d1376 DM |
276 | .upper_nop = 0x1c, |
277 | .lower_nop = 0x14, | |
b38e99f5 DM |
278 | .flags = (SPARC_PMU_ALL_EXCLUDES_SAME | |
279 | SPARC_PMU_HAS_CONFLICTS), | |
59abbd1e DM |
280 | }; |
281 | ||
7eebda60 DM |
282 | /* Niagara1 is very limited. The upper PIC is hard-locked to count |
283 | * only instructions, so it is free running which creates all kinds of | |
6e804251 | 284 | * problems. Some hardware designs make one wonder if the creator |
7eebda60 DM |
285 | * even looked at how this stuff gets used by software. |
286 | */ | |
287 | static const struct perf_event_map niagara1_perfmon_event_map[] = { | |
288 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER }, | |
289 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER }, | |
290 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE }, | |
291 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER }, | |
292 | }; | |
293 | ||
294 | static const struct perf_event_map *niagara1_event_map(int event_id) | |
295 | { | |
296 | return &niagara1_perfmon_event_map[event_id]; | |
297 | } | |
298 | ||
299 | static const cache_map_t niagara1_cache_map = { | |
300 | [C(L1D)] = { | |
301 | [C(OP_READ)] = { | |
302 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
303 | [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, | |
304 | }, | |
305 | [C(OP_WRITE)] = { | |
306 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
307 | [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, | |
308 | }, | |
309 | [C(OP_PREFETCH)] = { | |
310 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
311 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
312 | }, | |
313 | }, | |
314 | [C(L1I)] = { | |
315 | [C(OP_READ)] = { | |
316 | [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER }, | |
317 | [C(RESULT_MISS)] = { 0x02, PIC_LOWER, }, | |
318 | }, | |
319 | [ C(OP_WRITE) ] = { | |
320 | [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, | |
321 | [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, | |
322 | }, | |
323 | [ C(OP_PREFETCH) ] = { | |
324 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
325 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
326 | }, | |
327 | }, | |
328 | [C(LL)] = { | |
329 | [C(OP_READ)] = { | |
330 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
331 | [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, | |
332 | }, | |
333 | [C(OP_WRITE)] = { | |
334 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
335 | [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, | |
336 | }, | |
337 | [C(OP_PREFETCH)] = { | |
338 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
339 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
340 | }, | |
341 | }, | |
342 | [C(DTLB)] = { | |
343 | [C(OP_READ)] = { | |
344 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
345 | [C(RESULT_MISS)] = { 0x05, PIC_LOWER, }, | |
346 | }, | |
347 | [ C(OP_WRITE) ] = { | |
348 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
349 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
350 | }, | |
351 | [ C(OP_PREFETCH) ] = { | |
352 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
353 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
354 | }, | |
355 | }, | |
356 | [C(ITLB)] = { | |
357 | [C(OP_READ)] = { | |
358 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
359 | [C(RESULT_MISS)] = { 0x04, PIC_LOWER, }, | |
360 | }, | |
361 | [ C(OP_WRITE) ] = { | |
362 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
363 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
364 | }, | |
365 | [ C(OP_PREFETCH) ] = { | |
366 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
367 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
368 | }, | |
369 | }, | |
370 | [C(BPU)] = { | |
371 | [C(OP_READ)] = { | |
372 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
373 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
374 | }, | |
375 | [ C(OP_WRITE) ] = { | |
376 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
377 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
378 | }, | |
379 | [ C(OP_PREFETCH) ] = { | |
380 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
381 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
382 | }, | |
383 | }, | |
89d6c0b5 PZ |
384 | [C(NODE)] = { |
385 | [C(OP_READ)] = { | |
386 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
387 | [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
388 | }, | |
389 | [ C(OP_WRITE) ] = { | |
390 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
391 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
392 | }, | |
393 | [ C(OP_PREFETCH) ] = { | |
394 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
395 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
396 | }, | |
397 | }, | |
7eebda60 DM |
398 | }; |
399 | ||
400 | static const struct sparc_pmu niagara1_pmu = { | |
401 | .event_map = niagara1_event_map, | |
402 | .cache_map = &niagara1_cache_map, | |
403 | .max_events = ARRAY_SIZE(niagara1_perfmon_event_map), | |
404 | .upper_shift = 0, | |
405 | .lower_shift = 4, | |
406 | .event_mask = 0x7, | |
407 | .upper_nop = 0x0, | |
408 | .lower_nop = 0x0, | |
b38e99f5 DM |
409 | .flags = (SPARC_PMU_ALL_EXCLUDES_SAME | |
410 | SPARC_PMU_HAS_CONFLICTS), | |
7eebda60 DM |
411 | }; |
412 | ||
b73d8847 DM |
413 | static const struct perf_event_map niagara2_perfmon_event_map[] = { |
414 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER }, | |
415 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER }, | |
416 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER }, | |
417 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER }, | |
418 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER }, | |
419 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER }, | |
420 | }; | |
421 | ||
cdd6c482 | 422 | static const struct perf_event_map *niagara2_event_map(int event_id) |
b73d8847 | 423 | { |
cdd6c482 | 424 | return &niagara2_perfmon_event_map[event_id]; |
b73d8847 DM |
425 | } |
426 | ||
d0b86480 DM |
427 | static const cache_map_t niagara2_cache_map = { |
428 | [C(L1D)] = { | |
429 | [C(OP_READ)] = { | |
430 | [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, | |
431 | [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, | |
432 | }, | |
433 | [C(OP_WRITE)] = { | |
434 | [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, | |
435 | [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, | |
436 | }, | |
437 | [C(OP_PREFETCH)] = { | |
438 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
439 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
440 | }, | |
441 | }, | |
442 | [C(L1I)] = { | |
443 | [C(OP_READ)] = { | |
444 | [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, }, | |
445 | [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, }, | |
446 | }, | |
447 | [ C(OP_WRITE) ] = { | |
448 | [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, | |
449 | [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, | |
450 | }, | |
451 | [ C(OP_PREFETCH) ] = { | |
452 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
453 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
454 | }, | |
455 | }, | |
456 | [C(LL)] = { | |
457 | [C(OP_READ)] = { | |
458 | [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, | |
459 | [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, }, | |
460 | }, | |
461 | [C(OP_WRITE)] = { | |
462 | [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, | |
463 | [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, }, | |
464 | }, | |
465 | [C(OP_PREFETCH)] = { | |
466 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
467 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
468 | }, | |
469 | }, | |
470 | [C(DTLB)] = { | |
471 | [C(OP_READ)] = { | |
472 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
473 | [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, }, | |
474 | }, | |
475 | [ C(OP_WRITE) ] = { | |
476 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
477 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
478 | }, | |
479 | [ C(OP_PREFETCH) ] = { | |
480 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
481 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
482 | }, | |
483 | }, | |
484 | [C(ITLB)] = { | |
485 | [C(OP_READ)] = { | |
486 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
487 | [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, }, | |
488 | }, | |
489 | [ C(OP_WRITE) ] = { | |
490 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
491 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
492 | }, | |
493 | [ C(OP_PREFETCH) ] = { | |
494 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
495 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
496 | }, | |
497 | }, | |
498 | [C(BPU)] = { | |
499 | [C(OP_READ)] = { | |
500 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
501 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
502 | }, | |
503 | [ C(OP_WRITE) ] = { | |
504 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
89d6c0b5 PZ |
505 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, |
506 | }, | |
507 | [ C(OP_PREFETCH) ] = { | |
508 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
509 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
510 | }, | |
511 | }, | |
512 | [C(NODE)] = { | |
513 | [C(OP_READ)] = { | |
514 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
515 | [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
516 | }, | |
517 | [ C(OP_WRITE) ] = { | |
518 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
d0b86480 DM |
519 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, |
520 | }, | |
521 | [ C(OP_PREFETCH) ] = { | |
522 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
523 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
524 | }, | |
525 | }, | |
526 | }; | |
527 | ||
b73d8847 DM |
528 | static const struct sparc_pmu niagara2_pmu = { |
529 | .event_map = niagara2_event_map, | |
d0b86480 | 530 | .cache_map = &niagara2_cache_map, |
b73d8847 DM |
531 | .max_events = ARRAY_SIZE(niagara2_perfmon_event_map), |
532 | .upper_shift = 19, | |
533 | .lower_shift = 6, | |
534 | .event_mask = 0xfff, | |
535 | .hv_bit = 0x8, | |
de23cf3c | 536 | .irq_bit = 0x30, |
b73d8847 DM |
537 | .upper_nop = 0x220, |
538 | .lower_nop = 0x220, | |
b38e99f5 DM |
539 | .flags = (SPARC_PMU_ALL_EXCLUDES_SAME | |
540 | SPARC_PMU_HAS_CONFLICTS), | |
b73d8847 DM |
541 | }; |
542 | ||
59abbd1e DM |
543 | static const struct sparc_pmu *sparc_pmu __read_mostly; |
544 | ||
cdd6c482 | 545 | static u64 event_encoding(u64 event_id, int idx) |
59abbd1e DM |
546 | { |
547 | if (idx == PIC_UPPER_INDEX) | |
cdd6c482 | 548 | event_id <<= sparc_pmu->upper_shift; |
59abbd1e | 549 | else |
cdd6c482 IM |
550 | event_id <<= sparc_pmu->lower_shift; |
551 | return event_id; | |
59abbd1e DM |
552 | } |
553 | ||
554 | static u64 mask_for_index(int idx) | |
555 | { | |
556 | return event_encoding(sparc_pmu->event_mask, idx); | |
557 | } | |
558 | ||
559 | static u64 nop_for_index(int idx) | |
560 | { | |
561 | return event_encoding(idx == PIC_UPPER_INDEX ? | |
660d1376 DM |
562 | sparc_pmu->upper_nop : |
563 | sparc_pmu->lower_nop, idx); | |
59abbd1e DM |
564 | } |
565 | ||
d1751388 | 566 | static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) |
59abbd1e DM |
567 | { |
568 | u64 val, mask = mask_for_index(idx); | |
569 | ||
d1751388 DM |
570 | val = cpuc->pcr; |
571 | val &= ~mask; | |
572 | val |= hwc->config; | |
573 | cpuc->pcr = val; | |
574 | ||
09d053c7 | 575 | pcr_ops->write_pcr(0, cpuc->pcr); |
59abbd1e DM |
576 | } |
577 | ||
d1751388 | 578 | static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) |
59abbd1e DM |
579 | { |
580 | u64 mask = mask_for_index(idx); | |
581 | u64 nop = nop_for_index(idx); | |
d1751388 | 582 | u64 val; |
59abbd1e | 583 | |
d1751388 DM |
584 | val = cpuc->pcr; |
585 | val &= ~mask; | |
586 | val |= nop; | |
587 | cpuc->pcr = val; | |
588 | ||
09d053c7 | 589 | pcr_ops->write_pcr(0, cpuc->pcr); |
59abbd1e DM |
590 | } |
591 | ||
59abbd1e DM |
592 | static u32 read_pmc(int idx) |
593 | { | |
594 | u64 val; | |
595 | ||
09d053c7 | 596 | val = pcr_ops->read_pic(0); |
59abbd1e DM |
597 | if (idx == PIC_UPPER_INDEX) |
598 | val >>= 32; | |
599 | ||
600 | return val & 0xffffffff; | |
601 | } | |
602 | ||
603 | static void write_pmc(int idx, u64 val) | |
604 | { | |
605 | u64 shift, mask, pic; | |
606 | ||
607 | shift = 0; | |
608 | if (idx == PIC_UPPER_INDEX) | |
609 | shift = 32; | |
610 | ||
611 | mask = ((u64) 0xffffffff) << shift; | |
612 | val <<= shift; | |
613 | ||
09d053c7 | 614 | pic = pcr_ops->read_pic(0); |
59abbd1e DM |
615 | pic &= ~mask; |
616 | pic |= val; | |
09d053c7 | 617 | pcr_ops->write_pic(0, pic); |
59abbd1e DM |
618 | } |
619 | ||
e7bef6b0 DM |
620 | static u64 sparc_perf_event_update(struct perf_event *event, |
621 | struct hw_perf_event *hwc, int idx) | |
622 | { | |
623 | int shift = 64 - 32; | |
624 | u64 prev_raw_count, new_raw_count; | |
625 | s64 delta; | |
626 | ||
627 | again: | |
e7850595 | 628 | prev_raw_count = local64_read(&hwc->prev_count); |
e7bef6b0 DM |
629 | new_raw_count = read_pmc(idx); |
630 | ||
e7850595 | 631 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
e7bef6b0 DM |
632 | new_raw_count) != prev_raw_count) |
633 | goto again; | |
634 | ||
635 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | |
636 | delta >>= shift; | |
637 | ||
e7850595 PZ |
638 | local64_add(delta, &event->count); |
639 | local64_sub(delta, &hwc->period_left); | |
e7bef6b0 DM |
640 | |
641 | return new_raw_count; | |
642 | } | |
643 | ||
cdd6c482 | 644 | static int sparc_perf_event_set_period(struct perf_event *event, |
d29862f0 | 645 | struct hw_perf_event *hwc, int idx) |
59abbd1e | 646 | { |
e7850595 | 647 | s64 left = local64_read(&hwc->period_left); |
59abbd1e DM |
648 | s64 period = hwc->sample_period; |
649 | int ret = 0; | |
650 | ||
651 | if (unlikely(left <= -period)) { | |
652 | left = period; | |
e7850595 | 653 | local64_set(&hwc->period_left, left); |
59abbd1e DM |
654 | hwc->last_period = period; |
655 | ret = 1; | |
656 | } | |
657 | ||
658 | if (unlikely(left <= 0)) { | |
659 | left += period; | |
e7850595 | 660 | local64_set(&hwc->period_left, left); |
59abbd1e DM |
661 | hwc->last_period = period; |
662 | ret = 1; | |
663 | } | |
664 | if (left > MAX_PERIOD) | |
665 | left = MAX_PERIOD; | |
666 | ||
e7850595 | 667 | local64_set(&hwc->prev_count, (u64)-left); |
59abbd1e DM |
668 | |
669 | write_pmc(idx, (u64)(-left) & 0xffffffff); | |
670 | ||
cdd6c482 | 671 | perf_event_update_userpage(event); |
59abbd1e DM |
672 | |
673 | return ret; | |
674 | } | |
675 | ||
e7bef6b0 DM |
676 | /* If performance event entries have been added, move existing |
677 | * events around (if necessary) and then assign new entries to | |
678 | * counters. | |
679 | */ | |
680 | static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr) | |
59abbd1e | 681 | { |
e7bef6b0 | 682 | int i; |
59abbd1e | 683 | |
e7bef6b0 DM |
684 | if (!cpuc->n_added) |
685 | goto out; | |
59abbd1e | 686 | |
e7bef6b0 DM |
687 | /* Read in the counters which are moving. */ |
688 | for (i = 0; i < cpuc->n_events; i++) { | |
689 | struct perf_event *cp = cpuc->event[i]; | |
59abbd1e | 690 | |
e7bef6b0 DM |
691 | if (cpuc->current_idx[i] != PIC_NO_INDEX && |
692 | cpuc->current_idx[i] != cp->hw.idx) { | |
693 | sparc_perf_event_update(cp, &cp->hw, | |
694 | cpuc->current_idx[i]); | |
695 | cpuc->current_idx[i] = PIC_NO_INDEX; | |
696 | } | |
697 | } | |
59abbd1e | 698 | |
e7bef6b0 DM |
699 | /* Assign to counters all unassigned events. */ |
700 | for (i = 0; i < cpuc->n_events; i++) { | |
701 | struct perf_event *cp = cpuc->event[i]; | |
702 | struct hw_perf_event *hwc = &cp->hw; | |
703 | int idx = hwc->idx; | |
704 | u64 enc; | |
705 | ||
706 | if (cpuc->current_idx[i] != PIC_NO_INDEX) | |
707 | continue; | |
708 | ||
709 | sparc_perf_event_set_period(cp, hwc, idx); | |
710 | cpuc->current_idx[i] = idx; | |
711 | ||
712 | enc = perf_event_get_enc(cpuc->events[i]); | |
b7d45c3f | 713 | pcr &= ~mask_for_index(idx); |
a4eaf7f1 PZ |
714 | if (hwc->state & PERF_HES_STOPPED) |
715 | pcr |= nop_for_index(idx); | |
716 | else | |
717 | pcr |= event_encoding(enc, idx); | |
e7bef6b0 DM |
718 | } |
719 | out: | |
720 | return pcr; | |
59abbd1e DM |
721 | } |
722 | ||
a4eaf7f1 | 723 | static void sparc_pmu_enable(struct pmu *pmu) |
59abbd1e | 724 | { |
e7bef6b0 DM |
725 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
726 | u64 pcr; | |
59abbd1e | 727 | |
e7bef6b0 DM |
728 | if (cpuc->enabled) |
729 | return; | |
59abbd1e | 730 | |
e7bef6b0 DM |
731 | cpuc->enabled = 1; |
732 | barrier(); | |
59abbd1e | 733 | |
e7bef6b0 DM |
734 | pcr = cpuc->pcr; |
735 | if (!cpuc->n_events) { | |
736 | pcr = 0; | |
737 | } else { | |
738 | pcr = maybe_change_configuration(cpuc, pcr); | |
59abbd1e | 739 | |
e7bef6b0 DM |
740 | /* We require that all of the events have the same |
741 | * configuration, so just fetch the settings from the | |
742 | * first entry. | |
743 | */ | |
744 | cpuc->pcr = pcr | cpuc->event[0]->hw.config_base; | |
745 | } | |
59abbd1e | 746 | |
09d053c7 | 747 | pcr_ops->write_pcr(0, cpuc->pcr); |
e7bef6b0 DM |
748 | } |
749 | ||
a4eaf7f1 | 750 | static void sparc_pmu_disable(struct pmu *pmu) |
e7bef6b0 DM |
751 | { |
752 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
753 | u64 val; | |
754 | ||
755 | if (!cpuc->enabled) | |
756 | return; | |
757 | ||
758 | cpuc->enabled = 0; | |
759 | cpuc->n_added = 0; | |
760 | ||
761 | val = cpuc->pcr; | |
762 | val &= ~(PCR_UTRACE | PCR_STRACE | | |
763 | sparc_pmu->hv_bit | sparc_pmu->irq_bit); | |
764 | cpuc->pcr = val; | |
765 | ||
09d053c7 | 766 | pcr_ops->write_pcr(0, cpuc->pcr); |
59abbd1e DM |
767 | } |
768 | ||
a4eaf7f1 PZ |
769 | static int active_event_index(struct cpu_hw_events *cpuc, |
770 | struct perf_event *event) | |
771 | { | |
772 | int i; | |
773 | ||
774 | for (i = 0; i < cpuc->n_events; i++) { | |
775 | if (cpuc->event[i] == event) | |
776 | break; | |
777 | } | |
778 | BUG_ON(i == cpuc->n_events); | |
779 | return cpuc->current_idx[i]; | |
780 | } | |
781 | ||
782 | static void sparc_pmu_start(struct perf_event *event, int flags) | |
783 | { | |
784 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
785 | int idx = active_event_index(cpuc, event); | |
786 | ||
787 | if (flags & PERF_EF_RELOAD) { | |
788 | WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE)); | |
789 | sparc_perf_event_set_period(event, &event->hw, idx); | |
790 | } | |
791 | ||
792 | event->hw.state = 0; | |
793 | ||
794 | sparc_pmu_enable_event(cpuc, &event->hw, idx); | |
795 | } | |
796 | ||
797 | static void sparc_pmu_stop(struct perf_event *event, int flags) | |
798 | { | |
799 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
800 | int idx = active_event_index(cpuc, event); | |
801 | ||
802 | if (!(event->hw.state & PERF_HES_STOPPED)) { | |
803 | sparc_pmu_disable_event(cpuc, &event->hw, idx); | |
804 | event->hw.state |= PERF_HES_STOPPED; | |
805 | } | |
806 | ||
807 | if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) { | |
808 | sparc_perf_event_update(event, &event->hw, idx); | |
809 | event->hw.state |= PERF_HES_UPTODATE; | |
810 | } | |
811 | } | |
812 | ||
813 | static void sparc_pmu_del(struct perf_event *event, int _flags) | |
59abbd1e | 814 | { |
cdd6c482 | 815 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
e7bef6b0 DM |
816 | unsigned long flags; |
817 | int i; | |
59abbd1e | 818 | |
e7bef6b0 | 819 | local_irq_save(flags); |
33696fc0 | 820 | perf_pmu_disable(event->pmu); |
e7bef6b0 DM |
821 | |
822 | for (i = 0; i < cpuc->n_events; i++) { | |
823 | if (event == cpuc->event[i]) { | |
a4eaf7f1 PZ |
824 | /* Absorb the final count and turn off the |
825 | * event. | |
826 | */ | |
827 | sparc_pmu_stop(event, PERF_EF_UPDATE); | |
e7bef6b0 DM |
828 | |
829 | /* Shift remaining entries down into | |
830 | * the existing slot. | |
831 | */ | |
832 | while (++i < cpuc->n_events) { | |
833 | cpuc->event[i - 1] = cpuc->event[i]; | |
834 | cpuc->events[i - 1] = cpuc->events[i]; | |
835 | cpuc->current_idx[i - 1] = | |
836 | cpuc->current_idx[i]; | |
837 | } | |
838 | ||
e7bef6b0 | 839 | perf_event_update_userpage(event); |
59abbd1e | 840 | |
e7bef6b0 DM |
841 | cpuc->n_events--; |
842 | break; | |
843 | } | |
844 | } | |
59abbd1e | 845 | |
33696fc0 | 846 | perf_pmu_enable(event->pmu); |
e7bef6b0 DM |
847 | local_irq_restore(flags); |
848 | } | |
849 | ||
cdd6c482 | 850 | static void sparc_pmu_read(struct perf_event *event) |
59abbd1e | 851 | { |
e7bef6b0 DM |
852 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
853 | int idx = active_event_index(cpuc, event); | |
cdd6c482 | 854 | struct hw_perf_event *hwc = &event->hw; |
d1751388 | 855 | |
e7bef6b0 | 856 | sparc_perf_event_update(event, hwc, idx); |
59abbd1e DM |
857 | } |
858 | ||
cdd6c482 | 859 | static atomic_t active_events = ATOMIC_INIT(0); |
59abbd1e DM |
860 | static DEFINE_MUTEX(pmc_grab_mutex); |
861 | ||
d1751388 DM |
862 | static void perf_stop_nmi_watchdog(void *unused) |
863 | { | |
864 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
865 | ||
866 | stop_nmi_watchdog(NULL); | |
09d053c7 | 867 | cpuc->pcr = pcr_ops->read_pcr(0); |
d1751388 DM |
868 | } |
869 | ||
cdd6c482 | 870 | void perf_event_grab_pmc(void) |
59abbd1e | 871 | { |
cdd6c482 | 872 | if (atomic_inc_not_zero(&active_events)) |
59abbd1e DM |
873 | return; |
874 | ||
875 | mutex_lock(&pmc_grab_mutex); | |
cdd6c482 | 876 | if (atomic_read(&active_events) == 0) { |
59abbd1e | 877 | if (atomic_read(&nmi_active) > 0) { |
d1751388 | 878 | on_each_cpu(perf_stop_nmi_watchdog, NULL, 1); |
59abbd1e DM |
879 | BUG_ON(atomic_read(&nmi_active) != 0); |
880 | } | |
cdd6c482 | 881 | atomic_inc(&active_events); |
59abbd1e DM |
882 | } |
883 | mutex_unlock(&pmc_grab_mutex); | |
884 | } | |
885 | ||
cdd6c482 | 886 | void perf_event_release_pmc(void) |
59abbd1e | 887 | { |
cdd6c482 | 888 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) { |
59abbd1e DM |
889 | if (atomic_read(&nmi_active) == 0) |
890 | on_each_cpu(start_nmi_watchdog, NULL, 1); | |
891 | mutex_unlock(&pmc_grab_mutex); | |
892 | } | |
893 | } | |
894 | ||
2ce4da2e DM |
895 | static const struct perf_event_map *sparc_map_cache_event(u64 config) |
896 | { | |
897 | unsigned int cache_type, cache_op, cache_result; | |
898 | const struct perf_event_map *pmap; | |
899 | ||
900 | if (!sparc_pmu->cache_map) | |
901 | return ERR_PTR(-ENOENT); | |
902 | ||
903 | cache_type = (config >> 0) & 0xff; | |
904 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
905 | return ERR_PTR(-EINVAL); | |
906 | ||
907 | cache_op = (config >> 8) & 0xff; | |
908 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
909 | return ERR_PTR(-EINVAL); | |
910 | ||
911 | cache_result = (config >> 16) & 0xff; | |
912 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
913 | return ERR_PTR(-EINVAL); | |
914 | ||
915 | pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]); | |
916 | ||
917 | if (pmap->encoding == CACHE_OP_UNSUPPORTED) | |
918 | return ERR_PTR(-ENOENT); | |
919 | ||
920 | if (pmap->encoding == CACHE_OP_NONSENSE) | |
921 | return ERR_PTR(-EINVAL); | |
922 | ||
923 | return pmap; | |
924 | } | |
925 | ||
cdd6c482 | 926 | static void hw_perf_event_destroy(struct perf_event *event) |
59abbd1e | 927 | { |
cdd6c482 | 928 | perf_event_release_pmc(); |
59abbd1e DM |
929 | } |
930 | ||
a72a8a5f DM |
931 | /* Make sure all events can be scheduled into the hardware at |
932 | * the same time. This is simplified by the fact that we only | |
933 | * need to support 2 simultaneous HW events. | |
e7bef6b0 DM |
934 | * |
935 | * As a side effect, the evts[]->hw.idx values will be assigned | |
936 | * on success. These are pending indexes. When the events are | |
937 | * actually programmed into the chip, these values will propagate | |
938 | * to the per-cpu cpuc->current_idx[] slots, see the code in | |
939 | * maybe_change_configuration() for details. | |
a72a8a5f | 940 | */ |
e7bef6b0 DM |
941 | static int sparc_check_constraints(struct perf_event **evts, |
942 | unsigned long *events, int n_ev) | |
a72a8a5f | 943 | { |
e7bef6b0 DM |
944 | u8 msk0 = 0, msk1 = 0; |
945 | int idx0 = 0; | |
946 | ||
947 | /* This case is possible when we are invoked from | |
948 | * hw_perf_group_sched_in(). | |
949 | */ | |
950 | if (!n_ev) | |
951 | return 0; | |
952 | ||
15ac9a39 | 953 | if (n_ev > MAX_HWEVENTS) |
e7bef6b0 DM |
954 | return -1; |
955 | ||
b38e99f5 DM |
956 | if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) { |
957 | int i; | |
958 | ||
959 | for (i = 0; i < n_ev; i++) | |
960 | evts[i]->hw.idx = i; | |
961 | return 0; | |
962 | } | |
963 | ||
e7bef6b0 DM |
964 | msk0 = perf_event_get_msk(events[0]); |
965 | if (n_ev == 1) { | |
966 | if (msk0 & PIC_LOWER) | |
967 | idx0 = 1; | |
968 | goto success; | |
969 | } | |
970 | BUG_ON(n_ev != 2); | |
971 | msk1 = perf_event_get_msk(events[1]); | |
972 | ||
973 | /* If both events can go on any counter, OK. */ | |
974 | if (msk0 == (PIC_UPPER | PIC_LOWER) && | |
975 | msk1 == (PIC_UPPER | PIC_LOWER)) | |
976 | goto success; | |
977 | ||
978 | /* If one event is limited to a specific counter, | |
979 | * and the other can go on both, OK. | |
980 | */ | |
981 | if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) && | |
982 | msk1 == (PIC_UPPER | PIC_LOWER)) { | |
983 | if (msk0 & PIC_LOWER) | |
984 | idx0 = 1; | |
985 | goto success; | |
a72a8a5f DM |
986 | } |
987 | ||
e7bef6b0 DM |
988 | if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) && |
989 | msk0 == (PIC_UPPER | PIC_LOWER)) { | |
990 | if (msk1 & PIC_UPPER) | |
991 | idx0 = 1; | |
992 | goto success; | |
993 | } | |
994 | ||
995 | /* If the events are fixed to different counters, OK. */ | |
996 | if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) || | |
997 | (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) { | |
998 | if (msk0 & PIC_LOWER) | |
999 | idx0 = 1; | |
1000 | goto success; | |
1001 | } | |
1002 | ||
1003 | /* Otherwise, there is a conflict. */ | |
a72a8a5f | 1004 | return -1; |
e7bef6b0 DM |
1005 | |
1006 | success: | |
1007 | evts[0]->hw.idx = idx0; | |
1008 | if (n_ev == 2) | |
1009 | evts[1]->hw.idx = idx0 ^ 1; | |
1010 | return 0; | |
a72a8a5f DM |
1011 | } |
1012 | ||
01552f76 DM |
1013 | static int check_excludes(struct perf_event **evts, int n_prev, int n_new) |
1014 | { | |
1015 | int eu = 0, ek = 0, eh = 0; | |
1016 | struct perf_event *event; | |
1017 | int i, n, first; | |
1018 | ||
b38e99f5 DM |
1019 | if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME)) |
1020 | return 0; | |
1021 | ||
01552f76 DM |
1022 | n = n_prev + n_new; |
1023 | if (n <= 1) | |
1024 | return 0; | |
1025 | ||
1026 | first = 1; | |
1027 | for (i = 0; i < n; i++) { | |
1028 | event = evts[i]; | |
1029 | if (first) { | |
1030 | eu = event->attr.exclude_user; | |
1031 | ek = event->attr.exclude_kernel; | |
1032 | eh = event->attr.exclude_hv; | |
1033 | first = 0; | |
1034 | } else if (event->attr.exclude_user != eu || | |
1035 | event->attr.exclude_kernel != ek || | |
1036 | event->attr.exclude_hv != eh) { | |
1037 | return -EAGAIN; | |
1038 | } | |
1039 | } | |
1040 | ||
1041 | return 0; | |
1042 | } | |
1043 | ||
1044 | static int collect_events(struct perf_event *group, int max_count, | |
e7bef6b0 DM |
1045 | struct perf_event *evts[], unsigned long *events, |
1046 | int *current_idx) | |
01552f76 DM |
1047 | { |
1048 | struct perf_event *event; | |
1049 | int n = 0; | |
1050 | ||
1051 | if (!is_software_event(group)) { | |
1052 | if (n >= max_count) | |
1053 | return -1; | |
1054 | evts[n] = group; | |
e7bef6b0 DM |
1055 | events[n] = group->hw.event_base; |
1056 | current_idx[n++] = PIC_NO_INDEX; | |
01552f76 DM |
1057 | } |
1058 | list_for_each_entry(event, &group->sibling_list, group_entry) { | |
1059 | if (!is_software_event(event) && | |
1060 | event->state != PERF_EVENT_STATE_OFF) { | |
1061 | if (n >= max_count) | |
1062 | return -1; | |
1063 | evts[n] = event; | |
e7bef6b0 DM |
1064 | events[n] = event->hw.event_base; |
1065 | current_idx[n++] = PIC_NO_INDEX; | |
01552f76 DM |
1066 | } |
1067 | } | |
1068 | return n; | |
1069 | } | |
1070 | ||
a4eaf7f1 | 1071 | static int sparc_pmu_add(struct perf_event *event, int ef_flags) |
e7bef6b0 DM |
1072 | { |
1073 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1074 | int n0, ret = -EAGAIN; | |
1075 | unsigned long flags; | |
1076 | ||
1077 | local_irq_save(flags); | |
33696fc0 | 1078 | perf_pmu_disable(event->pmu); |
e7bef6b0 DM |
1079 | |
1080 | n0 = cpuc->n_events; | |
15ac9a39 | 1081 | if (n0 >= MAX_HWEVENTS) |
e7bef6b0 DM |
1082 | goto out; |
1083 | ||
1084 | cpuc->event[n0] = event; | |
1085 | cpuc->events[n0] = event->hw.event_base; | |
1086 | cpuc->current_idx[n0] = PIC_NO_INDEX; | |
1087 | ||
a4eaf7f1 PZ |
1088 | event->hw.state = PERF_HES_UPTODATE; |
1089 | if (!(ef_flags & PERF_EF_START)) | |
1090 | event->hw.state |= PERF_HES_STOPPED; | |
1091 | ||
a13c3afd LM |
1092 | /* |
1093 | * If group events scheduling transaction was started, | |
25985edc | 1094 | * skip the schedulability test here, it will be performed |
a13c3afd LM |
1095 | * at commit time(->commit_txn) as a whole |
1096 | */ | |
8d2cacbb | 1097 | if (cpuc->group_flag & PERF_EVENT_TXN) |
a13c3afd LM |
1098 | goto nocheck; |
1099 | ||
e7bef6b0 DM |
1100 | if (check_excludes(cpuc->event, n0, 1)) |
1101 | goto out; | |
1102 | if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1)) | |
1103 | goto out; | |
1104 | ||
a13c3afd | 1105 | nocheck: |
e7bef6b0 DM |
1106 | cpuc->n_events++; |
1107 | cpuc->n_added++; | |
1108 | ||
1109 | ret = 0; | |
1110 | out: | |
33696fc0 | 1111 | perf_pmu_enable(event->pmu); |
e7bef6b0 DM |
1112 | local_irq_restore(flags); |
1113 | return ret; | |
1114 | } | |
1115 | ||
b0a873eb | 1116 | static int sparc_pmu_event_init(struct perf_event *event) |
59abbd1e | 1117 | { |
cdd6c482 | 1118 | struct perf_event_attr *attr = &event->attr; |
01552f76 | 1119 | struct perf_event *evts[MAX_HWEVENTS]; |
cdd6c482 | 1120 | struct hw_perf_event *hwc = &event->hw; |
a72a8a5f | 1121 | unsigned long events[MAX_HWEVENTS]; |
e7bef6b0 | 1122 | int current_idx_dmy[MAX_HWEVENTS]; |
59abbd1e | 1123 | const struct perf_event_map *pmap; |
01552f76 | 1124 | int n; |
59abbd1e DM |
1125 | |
1126 | if (atomic_read(&nmi_active) < 0) | |
1127 | return -ENODEV; | |
1128 | ||
2481c5fa SE |
1129 | /* does not support taken branch sampling */ |
1130 | if (has_branch_stack(event)) | |
1131 | return -EOPNOTSUPP; | |
1132 | ||
b0a873eb PZ |
1133 | switch (attr->type) { |
1134 | case PERF_TYPE_HARDWARE: | |
2ce4da2e DM |
1135 | if (attr->config >= sparc_pmu->max_events) |
1136 | return -EINVAL; | |
1137 | pmap = sparc_pmu->event_map(attr->config); | |
b0a873eb PZ |
1138 | break; |
1139 | ||
1140 | case PERF_TYPE_HW_CACHE: | |
2ce4da2e DM |
1141 | pmap = sparc_map_cache_event(attr->config); |
1142 | if (IS_ERR(pmap)) | |
1143 | return PTR_ERR(pmap); | |
b0a873eb PZ |
1144 | break; |
1145 | ||
1146 | case PERF_TYPE_RAW: | |
d0303d71 IM |
1147 | pmap = NULL; |
1148 | break; | |
59abbd1e | 1149 | |
b0a873eb PZ |
1150 | default: |
1151 | return -ENOENT; | |
1152 | ||
1153 | } | |
1154 | ||
b343ae51 DM |
1155 | if (pmap) { |
1156 | hwc->event_base = perf_event_encode(pmap); | |
1157 | } else { | |
d0303d71 IM |
1158 | /* |
1159 | * User gives us "(encoding << 16) | pic_mask" for | |
b343ae51 DM |
1160 | * PERF_TYPE_RAW events. |
1161 | */ | |
1162 | hwc->event_base = attr->config; | |
1163 | } | |
1164 | ||
e7bef6b0 | 1165 | /* We save the enable bits in the config_base. */ |
496c07e3 | 1166 | hwc->config_base = sparc_pmu->irq_bit; |
59abbd1e DM |
1167 | if (!attr->exclude_user) |
1168 | hwc->config_base |= PCR_UTRACE; | |
1169 | if (!attr->exclude_kernel) | |
1170 | hwc->config_base |= PCR_STRACE; | |
91b9286d DM |
1171 | if (!attr->exclude_hv) |
1172 | hwc->config_base |= sparc_pmu->hv_bit; | |
59abbd1e | 1173 | |
01552f76 DM |
1174 | n = 0; |
1175 | if (event->group_leader != event) { | |
1176 | n = collect_events(event->group_leader, | |
15ac9a39 | 1177 | MAX_HWEVENTS - 1, |
e7bef6b0 | 1178 | evts, events, current_idx_dmy); |
01552f76 DM |
1179 | if (n < 0) |
1180 | return -EINVAL; | |
1181 | } | |
a72a8a5f | 1182 | events[n] = hwc->event_base; |
01552f76 DM |
1183 | evts[n] = event; |
1184 | ||
1185 | if (check_excludes(evts, n, 1)) | |
1186 | return -EINVAL; | |
1187 | ||
e7bef6b0 | 1188 | if (sparc_check_constraints(evts, events, n + 1)) |
a72a8a5f DM |
1189 | return -EINVAL; |
1190 | ||
e7bef6b0 DM |
1191 | hwc->idx = PIC_NO_INDEX; |
1192 | ||
01552f76 DM |
1193 | /* Try to do all error checking before this point, as unwinding |
1194 | * state after grabbing the PMC is difficult. | |
1195 | */ | |
1196 | perf_event_grab_pmc(); | |
1197 | event->destroy = hw_perf_event_destroy; | |
1198 | ||
59abbd1e DM |
1199 | if (!hwc->sample_period) { |
1200 | hwc->sample_period = MAX_PERIOD; | |
1201 | hwc->last_period = hwc->sample_period; | |
e7850595 | 1202 | local64_set(&hwc->period_left, hwc->sample_period); |
59abbd1e DM |
1203 | } |
1204 | ||
59abbd1e DM |
1205 | return 0; |
1206 | } | |
1207 | ||
a13c3afd LM |
1208 | /* |
1209 | * Start group events scheduling transaction | |
1210 | * Set the flag to make pmu::enable() not perform the | |
1211 | * schedulability test, it will be performed at commit time | |
1212 | */ | |
51b0fe39 | 1213 | static void sparc_pmu_start_txn(struct pmu *pmu) |
a13c3afd LM |
1214 | { |
1215 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1216 | ||
33696fc0 | 1217 | perf_pmu_disable(pmu); |
8d2cacbb | 1218 | cpuhw->group_flag |= PERF_EVENT_TXN; |
a13c3afd LM |
1219 | } |
1220 | ||
1221 | /* | |
1222 | * Stop group events scheduling transaction | |
1223 | * Clear the flag and pmu::enable() will perform the | |
1224 | * schedulability test. | |
1225 | */ | |
51b0fe39 | 1226 | static void sparc_pmu_cancel_txn(struct pmu *pmu) |
a13c3afd LM |
1227 | { |
1228 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1229 | ||
8d2cacbb | 1230 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1231 | perf_pmu_enable(pmu); |
a13c3afd LM |
1232 | } |
1233 | ||
1234 | /* | |
1235 | * Commit group events scheduling transaction | |
1236 | * Perform the group schedulability test as a whole | |
1237 | * Return 0 if success | |
1238 | */ | |
51b0fe39 | 1239 | static int sparc_pmu_commit_txn(struct pmu *pmu) |
a13c3afd LM |
1240 | { |
1241 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1242 | int n; | |
1243 | ||
1244 | if (!sparc_pmu) | |
1245 | return -EINVAL; | |
1246 | ||
1247 | cpuc = &__get_cpu_var(cpu_hw_events); | |
1248 | n = cpuc->n_events; | |
1249 | if (check_excludes(cpuc->event, 0, n)) | |
1250 | return -EINVAL; | |
1251 | if (sparc_check_constraints(cpuc->event, cpuc->events, n)) | |
1252 | return -EAGAIN; | |
1253 | ||
8d2cacbb | 1254 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
33696fc0 | 1255 | perf_pmu_enable(pmu); |
a13c3afd LM |
1256 | return 0; |
1257 | } | |
1258 | ||
51b0fe39 | 1259 | static struct pmu pmu = { |
a4eaf7f1 PZ |
1260 | .pmu_enable = sparc_pmu_enable, |
1261 | .pmu_disable = sparc_pmu_disable, | |
b0a873eb | 1262 | .event_init = sparc_pmu_event_init, |
a4eaf7f1 PZ |
1263 | .add = sparc_pmu_add, |
1264 | .del = sparc_pmu_del, | |
1265 | .start = sparc_pmu_start, | |
1266 | .stop = sparc_pmu_stop, | |
59abbd1e | 1267 | .read = sparc_pmu_read, |
a13c3afd LM |
1268 | .start_txn = sparc_pmu_start_txn, |
1269 | .cancel_txn = sparc_pmu_cancel_txn, | |
1270 | .commit_txn = sparc_pmu_commit_txn, | |
59abbd1e DM |
1271 | }; |
1272 | ||
cdd6c482 | 1273 | void perf_event_print_debug(void) |
59abbd1e DM |
1274 | { |
1275 | unsigned long flags; | |
1276 | u64 pcr, pic; | |
1277 | int cpu; | |
1278 | ||
1279 | if (!sparc_pmu) | |
1280 | return; | |
1281 | ||
1282 | local_irq_save(flags); | |
1283 | ||
1284 | cpu = smp_processor_id(); | |
1285 | ||
09d053c7 DM |
1286 | pcr = pcr_ops->read_pcr(0); |
1287 | pic = pcr_ops->read_pic(0); | |
59abbd1e DM |
1288 | |
1289 | pr_info("\n"); | |
1290 | pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n", | |
1291 | cpu, pcr, pic); | |
1292 | ||
1293 | local_irq_restore(flags); | |
1294 | } | |
1295 | ||
cdd6c482 | 1296 | static int __kprobes perf_event_nmi_handler(struct notifier_block *self, |
d29862f0 | 1297 | unsigned long cmd, void *__args) |
59abbd1e DM |
1298 | { |
1299 | struct die_args *args = __args; | |
1300 | struct perf_sample_data data; | |
cdd6c482 | 1301 | struct cpu_hw_events *cpuc; |
59abbd1e | 1302 | struct pt_regs *regs; |
e7bef6b0 | 1303 | int i; |
59abbd1e | 1304 | |
cdd6c482 | 1305 | if (!atomic_read(&active_events)) |
59abbd1e DM |
1306 | return NOTIFY_DONE; |
1307 | ||
1308 | switch (cmd) { | |
1309 | case DIE_NMI: | |
1310 | break; | |
1311 | ||
1312 | default: | |
1313 | return NOTIFY_DONE; | |
1314 | } | |
1315 | ||
1316 | regs = args->regs; | |
1317 | ||
cdd6c482 | 1318 | cpuc = &__get_cpu_var(cpu_hw_events); |
e04ed38d DM |
1319 | |
1320 | /* If the PMU has the TOE IRQ enable bits, we need to do a | |
1321 | * dummy write to the %pcr to clear the overflow bits and thus | |
1322 | * the interrupt. | |
1323 | * | |
1324 | * Do this before we peek at the counters to determine | |
1325 | * overflow so we don't lose any events. | |
1326 | */ | |
1327 | if (sparc_pmu->irq_bit) | |
09d053c7 | 1328 | pcr_ops->write_pcr(0, cpuc->pcr); |
e04ed38d | 1329 | |
e7bef6b0 DM |
1330 | for (i = 0; i < cpuc->n_events; i++) { |
1331 | struct perf_event *event = cpuc->event[i]; | |
1332 | int idx = cpuc->current_idx[i]; | |
cdd6c482 | 1333 | struct hw_perf_event *hwc; |
59abbd1e DM |
1334 | u64 val; |
1335 | ||
cdd6c482 IM |
1336 | hwc = &event->hw; |
1337 | val = sparc_perf_event_update(event, hwc, idx); | |
59abbd1e DM |
1338 | if (val & (1ULL << 31)) |
1339 | continue; | |
1340 | ||
fd0d000b | 1341 | perf_sample_data_init(&data, 0, hwc->last_period); |
cdd6c482 | 1342 | if (!sparc_perf_event_set_period(event, hwc, idx)) |
59abbd1e DM |
1343 | continue; |
1344 | ||
a8b0ca17 | 1345 | if (perf_event_overflow(event, &data, regs)) |
a4eaf7f1 | 1346 | sparc_pmu_stop(event, 0); |
59abbd1e DM |
1347 | } |
1348 | ||
1349 | return NOTIFY_STOP; | |
1350 | } | |
1351 | ||
cdd6c482 IM |
1352 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1353 | .notifier_call = perf_event_nmi_handler, | |
59abbd1e DM |
1354 | }; |
1355 | ||
1356 | static bool __init supported_pmu(void) | |
1357 | { | |
28e8f9be DM |
1358 | if (!strcmp(sparc_pmu_type, "ultra3") || |
1359 | !strcmp(sparc_pmu_type, "ultra3+") || | |
1360 | !strcmp(sparc_pmu_type, "ultra3i") || | |
1361 | !strcmp(sparc_pmu_type, "ultra4+")) { | |
1362 | sparc_pmu = &ultra3_pmu; | |
59abbd1e DM |
1363 | return true; |
1364 | } | |
7eebda60 DM |
1365 | if (!strcmp(sparc_pmu_type, "niagara")) { |
1366 | sparc_pmu = &niagara1_pmu; | |
1367 | return true; | |
1368 | } | |
4ba991d3 DM |
1369 | if (!strcmp(sparc_pmu_type, "niagara2") || |
1370 | !strcmp(sparc_pmu_type, "niagara3")) { | |
b73d8847 DM |
1371 | sparc_pmu = &niagara2_pmu; |
1372 | return true; | |
1373 | } | |
59abbd1e DM |
1374 | return false; |
1375 | } | |
1376 | ||
004417a6 | 1377 | int __init init_hw_perf_events(void) |
59abbd1e | 1378 | { |
cdd6c482 | 1379 | pr_info("Performance events: "); |
59abbd1e DM |
1380 | |
1381 | if (!supported_pmu()) { | |
1382 | pr_cont("No support for PMU type '%s'\n", sparc_pmu_type); | |
004417a6 | 1383 | return 0; |
59abbd1e DM |
1384 | } |
1385 | ||
1386 | pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type); | |
1387 | ||
2e80a82a | 1388 | perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); |
cdd6c482 | 1389 | register_die_notifier(&perf_event_nmi_notifier); |
004417a6 PZ |
1390 | |
1391 | return 0; | |
59abbd1e | 1392 | } |
efc70d24 | 1393 | early_initcall(init_hw_perf_events); |
4f6dbe4a | 1394 | |
56962b44 FW |
1395 | void perf_callchain_kernel(struct perf_callchain_entry *entry, |
1396 | struct pt_regs *regs) | |
4f6dbe4a DM |
1397 | { |
1398 | unsigned long ksp, fp; | |
667f0cee DM |
1399 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1400 | int graph = 0; | |
1401 | #endif | |
4f6dbe4a | 1402 | |
56962b44 FW |
1403 | stack_trace_flush(); |
1404 | ||
70791ce9 | 1405 | perf_callchain_store(entry, regs->tpc); |
4f6dbe4a DM |
1406 | |
1407 | ksp = regs->u_regs[UREG_I6]; | |
1408 | fp = ksp + STACK_BIAS; | |
1409 | do { | |
1410 | struct sparc_stackf *sf; | |
1411 | struct pt_regs *regs; | |
1412 | unsigned long pc; | |
1413 | ||
1414 | if (!kstack_valid(current_thread_info(), fp)) | |
1415 | break; | |
1416 | ||
1417 | sf = (struct sparc_stackf *) fp; | |
1418 | regs = (struct pt_regs *) (sf + 1); | |
1419 | ||
1420 | if (kstack_is_trap_frame(current_thread_info(), regs)) { | |
1421 | if (user_mode(regs)) | |
1422 | break; | |
1423 | pc = regs->tpc; | |
1424 | fp = regs->u_regs[UREG_I6] + STACK_BIAS; | |
1425 | } else { | |
1426 | pc = sf->callers_pc; | |
1427 | fp = (unsigned long)sf->fp + STACK_BIAS; | |
1428 | } | |
70791ce9 | 1429 | perf_callchain_store(entry, pc); |
667f0cee DM |
1430 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1431 | if ((pc + 8UL) == (unsigned long) &return_to_handler) { | |
1432 | int index = current->curr_ret_stack; | |
1433 | if (current->ret_stack && index >= graph) { | |
1434 | pc = current->ret_stack[index - graph].ret; | |
70791ce9 | 1435 | perf_callchain_store(entry, pc); |
667f0cee DM |
1436 | graph++; |
1437 | } | |
1438 | } | |
1439 | #endif | |
4f6dbe4a DM |
1440 | } while (entry->nr < PERF_MAX_STACK_DEPTH); |
1441 | } | |
1442 | ||
56962b44 FW |
1443 | static void perf_callchain_user_64(struct perf_callchain_entry *entry, |
1444 | struct pt_regs *regs) | |
4f6dbe4a DM |
1445 | { |
1446 | unsigned long ufp; | |
1447 | ||
70791ce9 | 1448 | perf_callchain_store(entry, regs->tpc); |
4f6dbe4a DM |
1449 | |
1450 | ufp = regs->u_regs[UREG_I6] + STACK_BIAS; | |
1451 | do { | |
1452 | struct sparc_stackf *usf, sf; | |
1453 | unsigned long pc; | |
1454 | ||
1455 | usf = (struct sparc_stackf *) ufp; | |
1456 | if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) | |
1457 | break; | |
1458 | ||
1459 | pc = sf.callers_pc; | |
1460 | ufp = (unsigned long)sf.fp + STACK_BIAS; | |
70791ce9 | 1461 | perf_callchain_store(entry, pc); |
4f6dbe4a DM |
1462 | } while (entry->nr < PERF_MAX_STACK_DEPTH); |
1463 | } | |
1464 | ||
56962b44 FW |
1465 | static void perf_callchain_user_32(struct perf_callchain_entry *entry, |
1466 | struct pt_regs *regs) | |
4f6dbe4a DM |
1467 | { |
1468 | unsigned long ufp; | |
1469 | ||
70791ce9 | 1470 | perf_callchain_store(entry, regs->tpc); |
4f6dbe4a | 1471 | |
9e8307ec | 1472 | ufp = regs->u_regs[UREG_I6] & 0xffffffffUL; |
4f6dbe4a DM |
1473 | do { |
1474 | struct sparc_stackf32 *usf, sf; | |
1475 | unsigned long pc; | |
1476 | ||
1477 | usf = (struct sparc_stackf32 *) ufp; | |
1478 | if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) | |
1479 | break; | |
1480 | ||
1481 | pc = sf.callers_pc; | |
1482 | ufp = (unsigned long)sf.fp; | |
70791ce9 | 1483 | perf_callchain_store(entry, pc); |
4f6dbe4a DM |
1484 | } while (entry->nr < PERF_MAX_STACK_DEPTH); |
1485 | } | |
1486 | ||
56962b44 FW |
1487 | void |
1488 | perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs) | |
4f6dbe4a | 1489 | { |
56962b44 FW |
1490 | flushw_user(); |
1491 | if (test_thread_flag(TIF_32BIT)) | |
1492 | perf_callchain_user_32(entry, regs); | |
1493 | else | |
1494 | perf_callchain_user_64(entry, regs); | |
4f6dbe4a | 1495 | } |