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cdd6c482 | 1 | /* Performance event support for sparc64. |
59abbd1e | 2 | * |
4f6dbe4a | 3 | * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net> |
59abbd1e | 4 | * |
cdd6c482 | 5 | * This code is based almost entirely upon the x86 perf event |
59abbd1e DM |
6 | * code, which is: |
7 | * | |
8 | * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de> | |
9 | * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar | |
10 | * Copyright (C) 2009 Jaswinder Singh Rajput | |
11 | * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter | |
12 | * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com> | |
13 | */ | |
14 | ||
cdd6c482 | 15 | #include <linux/perf_event.h> |
59abbd1e | 16 | #include <linux/kprobes.h> |
667f0cee | 17 | #include <linux/ftrace.h> |
59abbd1e DM |
18 | #include <linux/kernel.h> |
19 | #include <linux/kdebug.h> | |
20 | #include <linux/mutex.h> | |
21 | ||
4f6dbe4a | 22 | #include <asm/stacktrace.h> |
59abbd1e | 23 | #include <asm/cpudata.h> |
4f6dbe4a | 24 | #include <asm/uaccess.h> |
59abbd1e DM |
25 | #include <asm/atomic.h> |
26 | #include <asm/nmi.h> | |
27 | #include <asm/pcr.h> | |
28 | ||
4f6dbe4a DM |
29 | #include "kstack.h" |
30 | ||
59abbd1e DM |
31 | /* Sparc64 chips have two performance counters, 32-bits each, with |
32 | * overflow interrupts generated on transition from 0xffffffff to 0. | |
33 | * The counters are accessed in one go using a 64-bit register. | |
34 | * | |
35 | * Both counters are controlled using a single control register. The | |
36 | * only way to stop all sampling is to clear all of the context (user, | |
37 | * supervisor, hypervisor) sampling enable bits. But these bits apply | |
38 | * to both counters, thus the two counters can't be enabled/disabled | |
39 | * individually. | |
40 | * | |
41 | * The control register has two event fields, one for each of the two | |
42 | * counters. It's thus nearly impossible to have one counter going | |
43 | * while keeping the other one stopped. Therefore it is possible to | |
44 | * get overflow interrupts for counters not currently "in use" and | |
45 | * that condition must be checked in the overflow interrupt handler. | |
46 | * | |
47 | * So we use a hack, in that we program inactive counters with the | |
48 | * "sw_count0" and "sw_count1" events. These count how many times | |
49 | * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an | |
50 | * unusual way to encode a NOP and therefore will not trigger in | |
51 | * normal code. | |
52 | */ | |
53 | ||
cdd6c482 | 54 | #define MAX_HWEVENTS 2 |
59abbd1e DM |
55 | #define MAX_PERIOD ((1UL << 32) - 1) |
56 | ||
57 | #define PIC_UPPER_INDEX 0 | |
58 | #define PIC_LOWER_INDEX 1 | |
e7bef6b0 | 59 | #define PIC_NO_INDEX -1 |
59abbd1e | 60 | |
cdd6c482 | 61 | struct cpu_hw_events { |
e7bef6b0 DM |
62 | /* Number of events currently scheduled onto this cpu. |
63 | * This tells how many entries in the arrays below | |
64 | * are valid. | |
65 | */ | |
66 | int n_events; | |
67 | ||
68 | /* Number of new events added since the last hw_perf_disable(). | |
69 | * This works because the perf event layer always adds new | |
70 | * events inside of a perf_{disable,enable}() sequence. | |
71 | */ | |
72 | int n_added; | |
73 | ||
74 | /* Array of events current scheduled on this cpu. */ | |
75 | struct perf_event *event[MAX_HWEVENTS]; | |
76 | ||
77 | /* Array of encoded longs, specifying the %pcr register | |
78 | * encoding and the mask of PIC counters this even can | |
79 | * be scheduled on. See perf_event_encode() et al. | |
80 | */ | |
81 | unsigned long events[MAX_HWEVENTS]; | |
82 | ||
83 | /* The current counter index assigned to an event. When the | |
84 | * event hasn't been programmed into the cpu yet, this will | |
85 | * hold PIC_NO_INDEX. The event->hw.idx value tells us where | |
86 | * we ought to schedule the event. | |
87 | */ | |
88 | int current_idx[MAX_HWEVENTS]; | |
89 | ||
90 | /* Software copy of %pcr register on this cpu. */ | |
d1751388 | 91 | u64 pcr; |
e7bef6b0 DM |
92 | |
93 | /* Enabled/disable state. */ | |
d1751388 | 94 | int enabled; |
a13c3afd LM |
95 | |
96 | unsigned int group_flag; | |
59abbd1e | 97 | }; |
cdd6c482 | 98 | DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, }; |
59abbd1e | 99 | |
e7bef6b0 DM |
100 | /* An event map describes the characteristics of a performance |
101 | * counter event. In particular it gives the encoding as well as | |
102 | * a mask telling which counters the event can be measured on. | |
103 | */ | |
59abbd1e DM |
104 | struct perf_event_map { |
105 | u16 encoding; | |
106 | u8 pic_mask; | |
107 | #define PIC_NONE 0x00 | |
108 | #define PIC_UPPER 0x01 | |
109 | #define PIC_LOWER 0x02 | |
110 | }; | |
111 | ||
e7bef6b0 | 112 | /* Encode a perf_event_map entry into a long. */ |
a72a8a5f DM |
113 | static unsigned long perf_event_encode(const struct perf_event_map *pmap) |
114 | { | |
115 | return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask; | |
116 | } | |
117 | ||
e7bef6b0 DM |
118 | static u8 perf_event_get_msk(unsigned long val) |
119 | { | |
120 | return val & 0xff; | |
121 | } | |
122 | ||
123 | static u64 perf_event_get_enc(unsigned long val) | |
a72a8a5f | 124 | { |
e7bef6b0 | 125 | return val >> 16; |
a72a8a5f DM |
126 | } |
127 | ||
2ce4da2e DM |
128 | #define C(x) PERF_COUNT_HW_CACHE_##x |
129 | ||
130 | #define CACHE_OP_UNSUPPORTED 0xfffe | |
131 | #define CACHE_OP_NONSENSE 0xffff | |
132 | ||
133 | typedef struct perf_event_map cache_map_t | |
134 | [PERF_COUNT_HW_CACHE_MAX] | |
135 | [PERF_COUNT_HW_CACHE_OP_MAX] | |
136 | [PERF_COUNT_HW_CACHE_RESULT_MAX]; | |
137 | ||
59abbd1e DM |
138 | struct sparc_pmu { |
139 | const struct perf_event_map *(*event_map)(int); | |
2ce4da2e | 140 | const cache_map_t *cache_map; |
59abbd1e DM |
141 | int max_events; |
142 | int upper_shift; | |
143 | int lower_shift; | |
144 | int event_mask; | |
91b9286d | 145 | int hv_bit; |
496c07e3 | 146 | int irq_bit; |
660d1376 DM |
147 | int upper_nop; |
148 | int lower_nop; | |
59abbd1e DM |
149 | }; |
150 | ||
28e8f9be | 151 | static const struct perf_event_map ultra3_perfmon_event_map[] = { |
59abbd1e DM |
152 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER }, |
153 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER }, | |
154 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER }, | |
155 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER }, | |
156 | }; | |
157 | ||
28e8f9be | 158 | static const struct perf_event_map *ultra3_event_map(int event_id) |
59abbd1e | 159 | { |
28e8f9be | 160 | return &ultra3_perfmon_event_map[event_id]; |
59abbd1e DM |
161 | } |
162 | ||
28e8f9be | 163 | static const cache_map_t ultra3_cache_map = { |
2ce4da2e DM |
164 | [C(L1D)] = { |
165 | [C(OP_READ)] = { | |
166 | [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, | |
167 | [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, | |
168 | }, | |
169 | [C(OP_WRITE)] = { | |
170 | [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER }, | |
171 | [C(RESULT_MISS)] = { 0x0a, PIC_UPPER }, | |
172 | }, | |
173 | [C(OP_PREFETCH)] = { | |
174 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
175 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
176 | }, | |
177 | }, | |
178 | [C(L1I)] = { | |
179 | [C(OP_READ)] = { | |
180 | [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, }, | |
181 | [C(RESULT_MISS)] = { 0x09, PIC_UPPER, }, | |
182 | }, | |
183 | [ C(OP_WRITE) ] = { | |
184 | [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, | |
185 | [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, | |
186 | }, | |
187 | [ C(OP_PREFETCH) ] = { | |
188 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
189 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
190 | }, | |
191 | }, | |
192 | [C(LL)] = { | |
193 | [C(OP_READ)] = { | |
194 | [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, }, | |
195 | [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, }, | |
196 | }, | |
197 | [C(OP_WRITE)] = { | |
198 | [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER }, | |
199 | [C(RESULT_MISS)] = { 0x0c, PIC_UPPER }, | |
200 | }, | |
201 | [C(OP_PREFETCH)] = { | |
202 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
203 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
204 | }, | |
205 | }, | |
206 | [C(DTLB)] = { | |
207 | [C(OP_READ)] = { | |
208 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
209 | [C(RESULT_MISS)] = { 0x12, PIC_UPPER, }, | |
210 | }, | |
211 | [ C(OP_WRITE) ] = { | |
212 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
213 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
214 | }, | |
215 | [ C(OP_PREFETCH) ] = { | |
216 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
217 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
218 | }, | |
219 | }, | |
220 | [C(ITLB)] = { | |
221 | [C(OP_READ)] = { | |
222 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
223 | [C(RESULT_MISS)] = { 0x11, PIC_UPPER, }, | |
224 | }, | |
225 | [ C(OP_WRITE) ] = { | |
226 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
227 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
228 | }, | |
229 | [ C(OP_PREFETCH) ] = { | |
230 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
231 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
232 | }, | |
233 | }, | |
234 | [C(BPU)] = { | |
235 | [C(OP_READ)] = { | |
236 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
237 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
238 | }, | |
239 | [ C(OP_WRITE) ] = { | |
240 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
241 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
242 | }, | |
243 | [ C(OP_PREFETCH) ] = { | |
244 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
245 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
246 | }, | |
247 | }, | |
248 | }; | |
249 | ||
28e8f9be DM |
250 | static const struct sparc_pmu ultra3_pmu = { |
251 | .event_map = ultra3_event_map, | |
252 | .cache_map = &ultra3_cache_map, | |
253 | .max_events = ARRAY_SIZE(ultra3_perfmon_event_map), | |
59abbd1e DM |
254 | .upper_shift = 11, |
255 | .lower_shift = 4, | |
256 | .event_mask = 0x3f, | |
660d1376 DM |
257 | .upper_nop = 0x1c, |
258 | .lower_nop = 0x14, | |
59abbd1e DM |
259 | }; |
260 | ||
7eebda60 DM |
261 | /* Niagara1 is very limited. The upper PIC is hard-locked to count |
262 | * only instructions, so it is free running which creates all kinds of | |
6e804251 | 263 | * problems. Some hardware designs make one wonder if the creator |
7eebda60 DM |
264 | * even looked at how this stuff gets used by software. |
265 | */ | |
266 | static const struct perf_event_map niagara1_perfmon_event_map[] = { | |
267 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER }, | |
268 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER }, | |
269 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE }, | |
270 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER }, | |
271 | }; | |
272 | ||
273 | static const struct perf_event_map *niagara1_event_map(int event_id) | |
274 | { | |
275 | return &niagara1_perfmon_event_map[event_id]; | |
276 | } | |
277 | ||
278 | static const cache_map_t niagara1_cache_map = { | |
279 | [C(L1D)] = { | |
280 | [C(OP_READ)] = { | |
281 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
282 | [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, | |
283 | }, | |
284 | [C(OP_WRITE)] = { | |
285 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
286 | [C(RESULT_MISS)] = { 0x03, PIC_LOWER, }, | |
287 | }, | |
288 | [C(OP_PREFETCH)] = { | |
289 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
290 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
291 | }, | |
292 | }, | |
293 | [C(L1I)] = { | |
294 | [C(OP_READ)] = { | |
295 | [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER }, | |
296 | [C(RESULT_MISS)] = { 0x02, PIC_LOWER, }, | |
297 | }, | |
298 | [ C(OP_WRITE) ] = { | |
299 | [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, | |
300 | [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, | |
301 | }, | |
302 | [ C(OP_PREFETCH) ] = { | |
303 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
304 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
305 | }, | |
306 | }, | |
307 | [C(LL)] = { | |
308 | [C(OP_READ)] = { | |
309 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
310 | [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, | |
311 | }, | |
312 | [C(OP_WRITE)] = { | |
313 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
314 | [C(RESULT_MISS)] = { 0x07, PIC_LOWER, }, | |
315 | }, | |
316 | [C(OP_PREFETCH)] = { | |
317 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
318 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
319 | }, | |
320 | }, | |
321 | [C(DTLB)] = { | |
322 | [C(OP_READ)] = { | |
323 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
324 | [C(RESULT_MISS)] = { 0x05, PIC_LOWER, }, | |
325 | }, | |
326 | [ C(OP_WRITE) ] = { | |
327 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
328 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
329 | }, | |
330 | [ C(OP_PREFETCH) ] = { | |
331 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
332 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
333 | }, | |
334 | }, | |
335 | [C(ITLB)] = { | |
336 | [C(OP_READ)] = { | |
337 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
338 | [C(RESULT_MISS)] = { 0x04, PIC_LOWER, }, | |
339 | }, | |
340 | [ C(OP_WRITE) ] = { | |
341 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
342 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
343 | }, | |
344 | [ C(OP_PREFETCH) ] = { | |
345 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
346 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
347 | }, | |
348 | }, | |
349 | [C(BPU)] = { | |
350 | [C(OP_READ)] = { | |
351 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
352 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
353 | }, | |
354 | [ C(OP_WRITE) ] = { | |
355 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
356 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
357 | }, | |
358 | [ C(OP_PREFETCH) ] = { | |
359 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
360 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
361 | }, | |
362 | }, | |
363 | }; | |
364 | ||
365 | static const struct sparc_pmu niagara1_pmu = { | |
366 | .event_map = niagara1_event_map, | |
367 | .cache_map = &niagara1_cache_map, | |
368 | .max_events = ARRAY_SIZE(niagara1_perfmon_event_map), | |
369 | .upper_shift = 0, | |
370 | .lower_shift = 4, | |
371 | .event_mask = 0x7, | |
372 | .upper_nop = 0x0, | |
373 | .lower_nop = 0x0, | |
374 | }; | |
375 | ||
b73d8847 DM |
376 | static const struct perf_event_map niagara2_perfmon_event_map[] = { |
377 | [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER }, | |
378 | [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER }, | |
379 | [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER }, | |
380 | [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER }, | |
381 | [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER }, | |
382 | [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER }, | |
383 | }; | |
384 | ||
cdd6c482 | 385 | static const struct perf_event_map *niagara2_event_map(int event_id) |
b73d8847 | 386 | { |
cdd6c482 | 387 | return &niagara2_perfmon_event_map[event_id]; |
b73d8847 DM |
388 | } |
389 | ||
d0b86480 DM |
390 | static const cache_map_t niagara2_cache_map = { |
391 | [C(L1D)] = { | |
392 | [C(OP_READ)] = { | |
393 | [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, | |
394 | [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, | |
395 | }, | |
396 | [C(OP_WRITE)] = { | |
397 | [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, | |
398 | [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, }, | |
399 | }, | |
400 | [C(OP_PREFETCH)] = { | |
401 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
402 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
403 | }, | |
404 | }, | |
405 | [C(L1I)] = { | |
406 | [C(OP_READ)] = { | |
407 | [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, }, | |
408 | [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, }, | |
409 | }, | |
410 | [ C(OP_WRITE) ] = { | |
411 | [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE }, | |
412 | [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE }, | |
413 | }, | |
414 | [ C(OP_PREFETCH) ] = { | |
415 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
416 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
417 | }, | |
418 | }, | |
419 | [C(LL)] = { | |
420 | [C(OP_READ)] = { | |
421 | [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, }, | |
422 | [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, }, | |
423 | }, | |
424 | [C(OP_WRITE)] = { | |
425 | [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, }, | |
426 | [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, }, | |
427 | }, | |
428 | [C(OP_PREFETCH)] = { | |
429 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
430 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
431 | }, | |
432 | }, | |
433 | [C(DTLB)] = { | |
434 | [C(OP_READ)] = { | |
435 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
436 | [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, }, | |
437 | }, | |
438 | [ C(OP_WRITE) ] = { | |
439 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
440 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
441 | }, | |
442 | [ C(OP_PREFETCH) ] = { | |
443 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
444 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
445 | }, | |
446 | }, | |
447 | [C(ITLB)] = { | |
448 | [C(OP_READ)] = { | |
449 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
450 | [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, }, | |
451 | }, | |
452 | [ C(OP_WRITE) ] = { | |
453 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
454 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
455 | }, | |
456 | [ C(OP_PREFETCH) ] = { | |
457 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
458 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
459 | }, | |
460 | }, | |
461 | [C(BPU)] = { | |
462 | [C(OP_READ)] = { | |
463 | [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED }, | |
464 | [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED }, | |
465 | }, | |
466 | [ C(OP_WRITE) ] = { | |
467 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
468 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
469 | }, | |
470 | [ C(OP_PREFETCH) ] = { | |
471 | [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED }, | |
472 | [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED }, | |
473 | }, | |
474 | }, | |
475 | }; | |
476 | ||
b73d8847 DM |
477 | static const struct sparc_pmu niagara2_pmu = { |
478 | .event_map = niagara2_event_map, | |
d0b86480 | 479 | .cache_map = &niagara2_cache_map, |
b73d8847 DM |
480 | .max_events = ARRAY_SIZE(niagara2_perfmon_event_map), |
481 | .upper_shift = 19, | |
482 | .lower_shift = 6, | |
483 | .event_mask = 0xfff, | |
484 | .hv_bit = 0x8, | |
de23cf3c | 485 | .irq_bit = 0x30, |
b73d8847 DM |
486 | .upper_nop = 0x220, |
487 | .lower_nop = 0x220, | |
488 | }; | |
489 | ||
59abbd1e DM |
490 | static const struct sparc_pmu *sparc_pmu __read_mostly; |
491 | ||
cdd6c482 | 492 | static u64 event_encoding(u64 event_id, int idx) |
59abbd1e DM |
493 | { |
494 | if (idx == PIC_UPPER_INDEX) | |
cdd6c482 | 495 | event_id <<= sparc_pmu->upper_shift; |
59abbd1e | 496 | else |
cdd6c482 IM |
497 | event_id <<= sparc_pmu->lower_shift; |
498 | return event_id; | |
59abbd1e DM |
499 | } |
500 | ||
501 | static u64 mask_for_index(int idx) | |
502 | { | |
503 | return event_encoding(sparc_pmu->event_mask, idx); | |
504 | } | |
505 | ||
506 | static u64 nop_for_index(int idx) | |
507 | { | |
508 | return event_encoding(idx == PIC_UPPER_INDEX ? | |
660d1376 DM |
509 | sparc_pmu->upper_nop : |
510 | sparc_pmu->lower_nop, idx); | |
59abbd1e DM |
511 | } |
512 | ||
d1751388 | 513 | static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) |
59abbd1e DM |
514 | { |
515 | u64 val, mask = mask_for_index(idx); | |
516 | ||
d1751388 DM |
517 | val = cpuc->pcr; |
518 | val &= ~mask; | |
519 | val |= hwc->config; | |
520 | cpuc->pcr = val; | |
521 | ||
522 | pcr_ops->write(cpuc->pcr); | |
59abbd1e DM |
523 | } |
524 | ||
d1751388 | 525 | static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) |
59abbd1e DM |
526 | { |
527 | u64 mask = mask_for_index(idx); | |
528 | u64 nop = nop_for_index(idx); | |
d1751388 | 529 | u64 val; |
59abbd1e | 530 | |
d1751388 DM |
531 | val = cpuc->pcr; |
532 | val &= ~mask; | |
533 | val |= nop; | |
534 | cpuc->pcr = val; | |
535 | ||
536 | pcr_ops->write(cpuc->pcr); | |
59abbd1e DM |
537 | } |
538 | ||
59abbd1e DM |
539 | static u32 read_pmc(int idx) |
540 | { | |
541 | u64 val; | |
542 | ||
543 | read_pic(val); | |
544 | if (idx == PIC_UPPER_INDEX) | |
545 | val >>= 32; | |
546 | ||
547 | return val & 0xffffffff; | |
548 | } | |
549 | ||
550 | static void write_pmc(int idx, u64 val) | |
551 | { | |
552 | u64 shift, mask, pic; | |
553 | ||
554 | shift = 0; | |
555 | if (idx == PIC_UPPER_INDEX) | |
556 | shift = 32; | |
557 | ||
558 | mask = ((u64) 0xffffffff) << shift; | |
559 | val <<= shift; | |
560 | ||
561 | read_pic(pic); | |
562 | pic &= ~mask; | |
563 | pic |= val; | |
564 | write_pic(pic); | |
565 | } | |
566 | ||
e7bef6b0 DM |
567 | static u64 sparc_perf_event_update(struct perf_event *event, |
568 | struct hw_perf_event *hwc, int idx) | |
569 | { | |
570 | int shift = 64 - 32; | |
571 | u64 prev_raw_count, new_raw_count; | |
572 | s64 delta; | |
573 | ||
574 | again: | |
e7850595 | 575 | prev_raw_count = local64_read(&hwc->prev_count); |
e7bef6b0 DM |
576 | new_raw_count = read_pmc(idx); |
577 | ||
e7850595 | 578 | if (local64_cmpxchg(&hwc->prev_count, prev_raw_count, |
e7bef6b0 DM |
579 | new_raw_count) != prev_raw_count) |
580 | goto again; | |
581 | ||
582 | delta = (new_raw_count << shift) - (prev_raw_count << shift); | |
583 | delta >>= shift; | |
584 | ||
e7850595 PZ |
585 | local64_add(delta, &event->count); |
586 | local64_sub(delta, &hwc->period_left); | |
e7bef6b0 DM |
587 | |
588 | return new_raw_count; | |
589 | } | |
590 | ||
cdd6c482 | 591 | static int sparc_perf_event_set_period(struct perf_event *event, |
d29862f0 | 592 | struct hw_perf_event *hwc, int idx) |
59abbd1e | 593 | { |
e7850595 | 594 | s64 left = local64_read(&hwc->period_left); |
59abbd1e DM |
595 | s64 period = hwc->sample_period; |
596 | int ret = 0; | |
597 | ||
598 | if (unlikely(left <= -period)) { | |
599 | left = period; | |
e7850595 | 600 | local64_set(&hwc->period_left, left); |
59abbd1e DM |
601 | hwc->last_period = period; |
602 | ret = 1; | |
603 | } | |
604 | ||
605 | if (unlikely(left <= 0)) { | |
606 | left += period; | |
e7850595 | 607 | local64_set(&hwc->period_left, left); |
59abbd1e DM |
608 | hwc->last_period = period; |
609 | ret = 1; | |
610 | } | |
611 | if (left > MAX_PERIOD) | |
612 | left = MAX_PERIOD; | |
613 | ||
e7850595 | 614 | local64_set(&hwc->prev_count, (u64)-left); |
59abbd1e DM |
615 | |
616 | write_pmc(idx, (u64)(-left) & 0xffffffff); | |
617 | ||
cdd6c482 | 618 | perf_event_update_userpage(event); |
59abbd1e DM |
619 | |
620 | return ret; | |
621 | } | |
622 | ||
e7bef6b0 DM |
623 | /* If performance event entries have been added, move existing |
624 | * events around (if necessary) and then assign new entries to | |
625 | * counters. | |
626 | */ | |
627 | static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr) | |
59abbd1e | 628 | { |
e7bef6b0 | 629 | int i; |
59abbd1e | 630 | |
e7bef6b0 DM |
631 | if (!cpuc->n_added) |
632 | goto out; | |
59abbd1e | 633 | |
e7bef6b0 DM |
634 | /* Read in the counters which are moving. */ |
635 | for (i = 0; i < cpuc->n_events; i++) { | |
636 | struct perf_event *cp = cpuc->event[i]; | |
59abbd1e | 637 | |
e7bef6b0 DM |
638 | if (cpuc->current_idx[i] != PIC_NO_INDEX && |
639 | cpuc->current_idx[i] != cp->hw.idx) { | |
640 | sparc_perf_event_update(cp, &cp->hw, | |
641 | cpuc->current_idx[i]); | |
642 | cpuc->current_idx[i] = PIC_NO_INDEX; | |
643 | } | |
644 | } | |
59abbd1e | 645 | |
e7bef6b0 DM |
646 | /* Assign to counters all unassigned events. */ |
647 | for (i = 0; i < cpuc->n_events; i++) { | |
648 | struct perf_event *cp = cpuc->event[i]; | |
649 | struct hw_perf_event *hwc = &cp->hw; | |
650 | int idx = hwc->idx; | |
651 | u64 enc; | |
652 | ||
653 | if (cpuc->current_idx[i] != PIC_NO_INDEX) | |
654 | continue; | |
655 | ||
656 | sparc_perf_event_set_period(cp, hwc, idx); | |
657 | cpuc->current_idx[i] = idx; | |
658 | ||
659 | enc = perf_event_get_enc(cpuc->events[i]); | |
b7d45c3f | 660 | pcr &= ~mask_for_index(idx); |
e7bef6b0 DM |
661 | pcr |= event_encoding(enc, idx); |
662 | } | |
663 | out: | |
664 | return pcr; | |
59abbd1e DM |
665 | } |
666 | ||
e7bef6b0 | 667 | void hw_perf_enable(void) |
59abbd1e | 668 | { |
e7bef6b0 DM |
669 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
670 | u64 pcr; | |
59abbd1e | 671 | |
e7bef6b0 DM |
672 | if (cpuc->enabled) |
673 | return; | |
59abbd1e | 674 | |
e7bef6b0 DM |
675 | cpuc->enabled = 1; |
676 | barrier(); | |
59abbd1e | 677 | |
e7bef6b0 DM |
678 | pcr = cpuc->pcr; |
679 | if (!cpuc->n_events) { | |
680 | pcr = 0; | |
681 | } else { | |
682 | pcr = maybe_change_configuration(cpuc, pcr); | |
59abbd1e | 683 | |
e7bef6b0 DM |
684 | /* We require that all of the events have the same |
685 | * configuration, so just fetch the settings from the | |
686 | * first entry. | |
687 | */ | |
688 | cpuc->pcr = pcr | cpuc->event[0]->hw.config_base; | |
689 | } | |
59abbd1e | 690 | |
e7bef6b0 DM |
691 | pcr_ops->write(cpuc->pcr); |
692 | } | |
693 | ||
694 | void hw_perf_disable(void) | |
695 | { | |
696 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
697 | u64 val; | |
698 | ||
699 | if (!cpuc->enabled) | |
700 | return; | |
701 | ||
702 | cpuc->enabled = 0; | |
703 | cpuc->n_added = 0; | |
704 | ||
705 | val = cpuc->pcr; | |
706 | val &= ~(PCR_UTRACE | PCR_STRACE | | |
707 | sparc_pmu->hv_bit | sparc_pmu->irq_bit); | |
708 | cpuc->pcr = val; | |
709 | ||
710 | pcr_ops->write(cpuc->pcr); | |
59abbd1e DM |
711 | } |
712 | ||
cdd6c482 | 713 | static void sparc_pmu_disable(struct perf_event *event) |
59abbd1e | 714 | { |
cdd6c482 IM |
715 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
716 | struct hw_perf_event *hwc = &event->hw; | |
e7bef6b0 DM |
717 | unsigned long flags; |
718 | int i; | |
59abbd1e | 719 | |
e7bef6b0 DM |
720 | local_irq_save(flags); |
721 | perf_disable(); | |
722 | ||
723 | for (i = 0; i < cpuc->n_events; i++) { | |
724 | if (event == cpuc->event[i]) { | |
725 | int idx = cpuc->current_idx[i]; | |
726 | ||
727 | /* Shift remaining entries down into | |
728 | * the existing slot. | |
729 | */ | |
730 | while (++i < cpuc->n_events) { | |
731 | cpuc->event[i - 1] = cpuc->event[i]; | |
732 | cpuc->events[i - 1] = cpuc->events[i]; | |
733 | cpuc->current_idx[i - 1] = | |
734 | cpuc->current_idx[i]; | |
735 | } | |
736 | ||
737 | /* Absorb the final count and turn off the | |
738 | * event. | |
739 | */ | |
740 | sparc_pmu_disable_event(cpuc, hwc, idx); | |
741 | barrier(); | |
742 | sparc_perf_event_update(event, hwc, idx); | |
59abbd1e | 743 | |
e7bef6b0 | 744 | perf_event_update_userpage(event); |
59abbd1e | 745 | |
e7bef6b0 DM |
746 | cpuc->n_events--; |
747 | break; | |
748 | } | |
749 | } | |
59abbd1e | 750 | |
e7bef6b0 DM |
751 | perf_enable(); |
752 | local_irq_restore(flags); | |
753 | } | |
754 | ||
755 | static int active_event_index(struct cpu_hw_events *cpuc, | |
756 | struct perf_event *event) | |
757 | { | |
758 | int i; | |
759 | ||
760 | for (i = 0; i < cpuc->n_events; i++) { | |
761 | if (cpuc->event[i] == event) | |
762 | break; | |
763 | } | |
764 | BUG_ON(i == cpuc->n_events); | |
765 | return cpuc->current_idx[i]; | |
59abbd1e DM |
766 | } |
767 | ||
cdd6c482 | 768 | static void sparc_pmu_read(struct perf_event *event) |
59abbd1e | 769 | { |
e7bef6b0 DM |
770 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
771 | int idx = active_event_index(cpuc, event); | |
cdd6c482 | 772 | struct hw_perf_event *hwc = &event->hw; |
d1751388 | 773 | |
e7bef6b0 | 774 | sparc_perf_event_update(event, hwc, idx); |
59abbd1e DM |
775 | } |
776 | ||
cdd6c482 | 777 | static void sparc_pmu_unthrottle(struct perf_event *event) |
59abbd1e | 778 | { |
d1751388 | 779 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); |
e7bef6b0 | 780 | int idx = active_event_index(cpuc, event); |
cdd6c482 | 781 | struct hw_perf_event *hwc = &event->hw; |
d1751388 | 782 | |
e7bef6b0 | 783 | sparc_pmu_enable_event(cpuc, hwc, idx); |
59abbd1e DM |
784 | } |
785 | ||
cdd6c482 | 786 | static atomic_t active_events = ATOMIC_INIT(0); |
59abbd1e DM |
787 | static DEFINE_MUTEX(pmc_grab_mutex); |
788 | ||
d1751388 DM |
789 | static void perf_stop_nmi_watchdog(void *unused) |
790 | { | |
791 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
792 | ||
793 | stop_nmi_watchdog(NULL); | |
794 | cpuc->pcr = pcr_ops->read(); | |
795 | } | |
796 | ||
cdd6c482 | 797 | void perf_event_grab_pmc(void) |
59abbd1e | 798 | { |
cdd6c482 | 799 | if (atomic_inc_not_zero(&active_events)) |
59abbd1e DM |
800 | return; |
801 | ||
802 | mutex_lock(&pmc_grab_mutex); | |
cdd6c482 | 803 | if (atomic_read(&active_events) == 0) { |
59abbd1e | 804 | if (atomic_read(&nmi_active) > 0) { |
d1751388 | 805 | on_each_cpu(perf_stop_nmi_watchdog, NULL, 1); |
59abbd1e DM |
806 | BUG_ON(atomic_read(&nmi_active) != 0); |
807 | } | |
cdd6c482 | 808 | atomic_inc(&active_events); |
59abbd1e DM |
809 | } |
810 | mutex_unlock(&pmc_grab_mutex); | |
811 | } | |
812 | ||
cdd6c482 | 813 | void perf_event_release_pmc(void) |
59abbd1e | 814 | { |
cdd6c482 | 815 | if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) { |
59abbd1e DM |
816 | if (atomic_read(&nmi_active) == 0) |
817 | on_each_cpu(start_nmi_watchdog, NULL, 1); | |
818 | mutex_unlock(&pmc_grab_mutex); | |
819 | } | |
820 | } | |
821 | ||
2ce4da2e DM |
822 | static const struct perf_event_map *sparc_map_cache_event(u64 config) |
823 | { | |
824 | unsigned int cache_type, cache_op, cache_result; | |
825 | const struct perf_event_map *pmap; | |
826 | ||
827 | if (!sparc_pmu->cache_map) | |
828 | return ERR_PTR(-ENOENT); | |
829 | ||
830 | cache_type = (config >> 0) & 0xff; | |
831 | if (cache_type >= PERF_COUNT_HW_CACHE_MAX) | |
832 | return ERR_PTR(-EINVAL); | |
833 | ||
834 | cache_op = (config >> 8) & 0xff; | |
835 | if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) | |
836 | return ERR_PTR(-EINVAL); | |
837 | ||
838 | cache_result = (config >> 16) & 0xff; | |
839 | if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) | |
840 | return ERR_PTR(-EINVAL); | |
841 | ||
842 | pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]); | |
843 | ||
844 | if (pmap->encoding == CACHE_OP_UNSUPPORTED) | |
845 | return ERR_PTR(-ENOENT); | |
846 | ||
847 | if (pmap->encoding == CACHE_OP_NONSENSE) | |
848 | return ERR_PTR(-EINVAL); | |
849 | ||
850 | return pmap; | |
851 | } | |
852 | ||
cdd6c482 | 853 | static void hw_perf_event_destroy(struct perf_event *event) |
59abbd1e | 854 | { |
cdd6c482 | 855 | perf_event_release_pmc(); |
59abbd1e DM |
856 | } |
857 | ||
a72a8a5f DM |
858 | /* Make sure all events can be scheduled into the hardware at |
859 | * the same time. This is simplified by the fact that we only | |
860 | * need to support 2 simultaneous HW events. | |
e7bef6b0 DM |
861 | * |
862 | * As a side effect, the evts[]->hw.idx values will be assigned | |
863 | * on success. These are pending indexes. When the events are | |
864 | * actually programmed into the chip, these values will propagate | |
865 | * to the per-cpu cpuc->current_idx[] slots, see the code in | |
866 | * maybe_change_configuration() for details. | |
a72a8a5f | 867 | */ |
e7bef6b0 DM |
868 | static int sparc_check_constraints(struct perf_event **evts, |
869 | unsigned long *events, int n_ev) | |
a72a8a5f | 870 | { |
e7bef6b0 DM |
871 | u8 msk0 = 0, msk1 = 0; |
872 | int idx0 = 0; | |
873 | ||
874 | /* This case is possible when we are invoked from | |
875 | * hw_perf_group_sched_in(). | |
876 | */ | |
877 | if (!n_ev) | |
878 | return 0; | |
879 | ||
880 | if (n_ev > perf_max_events) | |
881 | return -1; | |
882 | ||
883 | msk0 = perf_event_get_msk(events[0]); | |
884 | if (n_ev == 1) { | |
885 | if (msk0 & PIC_LOWER) | |
886 | idx0 = 1; | |
887 | goto success; | |
888 | } | |
889 | BUG_ON(n_ev != 2); | |
890 | msk1 = perf_event_get_msk(events[1]); | |
891 | ||
892 | /* If both events can go on any counter, OK. */ | |
893 | if (msk0 == (PIC_UPPER | PIC_LOWER) && | |
894 | msk1 == (PIC_UPPER | PIC_LOWER)) | |
895 | goto success; | |
896 | ||
897 | /* If one event is limited to a specific counter, | |
898 | * and the other can go on both, OK. | |
899 | */ | |
900 | if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) && | |
901 | msk1 == (PIC_UPPER | PIC_LOWER)) { | |
902 | if (msk0 & PIC_LOWER) | |
903 | idx0 = 1; | |
904 | goto success; | |
a72a8a5f DM |
905 | } |
906 | ||
e7bef6b0 DM |
907 | if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) && |
908 | msk0 == (PIC_UPPER | PIC_LOWER)) { | |
909 | if (msk1 & PIC_UPPER) | |
910 | idx0 = 1; | |
911 | goto success; | |
912 | } | |
913 | ||
914 | /* If the events are fixed to different counters, OK. */ | |
915 | if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) || | |
916 | (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) { | |
917 | if (msk0 & PIC_LOWER) | |
918 | idx0 = 1; | |
919 | goto success; | |
920 | } | |
921 | ||
922 | /* Otherwise, there is a conflict. */ | |
a72a8a5f | 923 | return -1; |
e7bef6b0 DM |
924 | |
925 | success: | |
926 | evts[0]->hw.idx = idx0; | |
927 | if (n_ev == 2) | |
928 | evts[1]->hw.idx = idx0 ^ 1; | |
929 | return 0; | |
a72a8a5f DM |
930 | } |
931 | ||
01552f76 DM |
932 | static int check_excludes(struct perf_event **evts, int n_prev, int n_new) |
933 | { | |
934 | int eu = 0, ek = 0, eh = 0; | |
935 | struct perf_event *event; | |
936 | int i, n, first; | |
937 | ||
938 | n = n_prev + n_new; | |
939 | if (n <= 1) | |
940 | return 0; | |
941 | ||
942 | first = 1; | |
943 | for (i = 0; i < n; i++) { | |
944 | event = evts[i]; | |
945 | if (first) { | |
946 | eu = event->attr.exclude_user; | |
947 | ek = event->attr.exclude_kernel; | |
948 | eh = event->attr.exclude_hv; | |
949 | first = 0; | |
950 | } else if (event->attr.exclude_user != eu || | |
951 | event->attr.exclude_kernel != ek || | |
952 | event->attr.exclude_hv != eh) { | |
953 | return -EAGAIN; | |
954 | } | |
955 | } | |
956 | ||
957 | return 0; | |
958 | } | |
959 | ||
960 | static int collect_events(struct perf_event *group, int max_count, | |
e7bef6b0 DM |
961 | struct perf_event *evts[], unsigned long *events, |
962 | int *current_idx) | |
01552f76 DM |
963 | { |
964 | struct perf_event *event; | |
965 | int n = 0; | |
966 | ||
967 | if (!is_software_event(group)) { | |
968 | if (n >= max_count) | |
969 | return -1; | |
970 | evts[n] = group; | |
e7bef6b0 DM |
971 | events[n] = group->hw.event_base; |
972 | current_idx[n++] = PIC_NO_INDEX; | |
01552f76 DM |
973 | } |
974 | list_for_each_entry(event, &group->sibling_list, group_entry) { | |
975 | if (!is_software_event(event) && | |
976 | event->state != PERF_EVENT_STATE_OFF) { | |
977 | if (n >= max_count) | |
978 | return -1; | |
979 | evts[n] = event; | |
e7bef6b0 DM |
980 | events[n] = event->hw.event_base; |
981 | current_idx[n++] = PIC_NO_INDEX; | |
01552f76 DM |
982 | } |
983 | } | |
984 | return n; | |
985 | } | |
986 | ||
e7bef6b0 DM |
987 | static int sparc_pmu_enable(struct perf_event *event) |
988 | { | |
989 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
990 | int n0, ret = -EAGAIN; | |
991 | unsigned long flags; | |
992 | ||
993 | local_irq_save(flags); | |
994 | perf_disable(); | |
995 | ||
996 | n0 = cpuc->n_events; | |
997 | if (n0 >= perf_max_events) | |
998 | goto out; | |
999 | ||
1000 | cpuc->event[n0] = event; | |
1001 | cpuc->events[n0] = event->hw.event_base; | |
1002 | cpuc->current_idx[n0] = PIC_NO_INDEX; | |
1003 | ||
a13c3afd LM |
1004 | /* |
1005 | * If group events scheduling transaction was started, | |
1006 | * skip the schedulability test here, it will be peformed | |
1007 | * at commit time(->commit_txn) as a whole | |
1008 | */ | |
8d2cacbb | 1009 | if (cpuc->group_flag & PERF_EVENT_TXN) |
a13c3afd LM |
1010 | goto nocheck; |
1011 | ||
e7bef6b0 DM |
1012 | if (check_excludes(cpuc->event, n0, 1)) |
1013 | goto out; | |
1014 | if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1)) | |
1015 | goto out; | |
1016 | ||
a13c3afd | 1017 | nocheck: |
e7bef6b0 DM |
1018 | cpuc->n_events++; |
1019 | cpuc->n_added++; | |
1020 | ||
1021 | ret = 0; | |
1022 | out: | |
1023 | perf_enable(); | |
1024 | local_irq_restore(flags); | |
1025 | return ret; | |
1026 | } | |
1027 | ||
cdd6c482 | 1028 | static int __hw_perf_event_init(struct perf_event *event) |
59abbd1e | 1029 | { |
cdd6c482 | 1030 | struct perf_event_attr *attr = &event->attr; |
01552f76 | 1031 | struct perf_event *evts[MAX_HWEVENTS]; |
cdd6c482 | 1032 | struct hw_perf_event *hwc = &event->hw; |
a72a8a5f | 1033 | unsigned long events[MAX_HWEVENTS]; |
e7bef6b0 | 1034 | int current_idx_dmy[MAX_HWEVENTS]; |
59abbd1e | 1035 | const struct perf_event_map *pmap; |
01552f76 | 1036 | int n; |
59abbd1e DM |
1037 | |
1038 | if (atomic_read(&nmi_active) < 0) | |
1039 | return -ENODEV; | |
1040 | ||
2ce4da2e DM |
1041 | if (attr->type == PERF_TYPE_HARDWARE) { |
1042 | if (attr->config >= sparc_pmu->max_events) | |
1043 | return -EINVAL; | |
1044 | pmap = sparc_pmu->event_map(attr->config); | |
1045 | } else if (attr->type == PERF_TYPE_HW_CACHE) { | |
1046 | pmap = sparc_map_cache_event(attr->config); | |
1047 | if (IS_ERR(pmap)) | |
1048 | return PTR_ERR(pmap); | |
1049 | } else | |
59abbd1e DM |
1050 | return -EOPNOTSUPP; |
1051 | ||
e7bef6b0 | 1052 | /* We save the enable bits in the config_base. */ |
496c07e3 | 1053 | hwc->config_base = sparc_pmu->irq_bit; |
59abbd1e DM |
1054 | if (!attr->exclude_user) |
1055 | hwc->config_base |= PCR_UTRACE; | |
1056 | if (!attr->exclude_kernel) | |
1057 | hwc->config_base |= PCR_STRACE; | |
91b9286d DM |
1058 | if (!attr->exclude_hv) |
1059 | hwc->config_base |= sparc_pmu->hv_bit; | |
59abbd1e | 1060 | |
a72a8a5f DM |
1061 | hwc->event_base = perf_event_encode(pmap); |
1062 | ||
01552f76 DM |
1063 | n = 0; |
1064 | if (event->group_leader != event) { | |
1065 | n = collect_events(event->group_leader, | |
1066 | perf_max_events - 1, | |
e7bef6b0 | 1067 | evts, events, current_idx_dmy); |
01552f76 DM |
1068 | if (n < 0) |
1069 | return -EINVAL; | |
1070 | } | |
a72a8a5f | 1071 | events[n] = hwc->event_base; |
01552f76 DM |
1072 | evts[n] = event; |
1073 | ||
1074 | if (check_excludes(evts, n, 1)) | |
1075 | return -EINVAL; | |
1076 | ||
e7bef6b0 | 1077 | if (sparc_check_constraints(evts, events, n + 1)) |
a72a8a5f DM |
1078 | return -EINVAL; |
1079 | ||
e7bef6b0 DM |
1080 | hwc->idx = PIC_NO_INDEX; |
1081 | ||
01552f76 DM |
1082 | /* Try to do all error checking before this point, as unwinding |
1083 | * state after grabbing the PMC is difficult. | |
1084 | */ | |
1085 | perf_event_grab_pmc(); | |
1086 | event->destroy = hw_perf_event_destroy; | |
1087 | ||
59abbd1e DM |
1088 | if (!hwc->sample_period) { |
1089 | hwc->sample_period = MAX_PERIOD; | |
1090 | hwc->last_period = hwc->sample_period; | |
e7850595 | 1091 | local64_set(&hwc->period_left, hwc->sample_period); |
59abbd1e DM |
1092 | } |
1093 | ||
59abbd1e DM |
1094 | return 0; |
1095 | } | |
1096 | ||
a13c3afd LM |
1097 | /* |
1098 | * Start group events scheduling transaction | |
1099 | * Set the flag to make pmu::enable() not perform the | |
1100 | * schedulability test, it will be performed at commit time | |
1101 | */ | |
1102 | static void sparc_pmu_start_txn(const struct pmu *pmu) | |
1103 | { | |
1104 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1105 | ||
8d2cacbb | 1106 | cpuhw->group_flag |= PERF_EVENT_TXN; |
a13c3afd LM |
1107 | } |
1108 | ||
1109 | /* | |
1110 | * Stop group events scheduling transaction | |
1111 | * Clear the flag and pmu::enable() will perform the | |
1112 | * schedulability test. | |
1113 | */ | |
1114 | static void sparc_pmu_cancel_txn(const struct pmu *pmu) | |
1115 | { | |
1116 | struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events); | |
1117 | ||
8d2cacbb | 1118 | cpuhw->group_flag &= ~PERF_EVENT_TXN; |
a13c3afd LM |
1119 | } |
1120 | ||
1121 | /* | |
1122 | * Commit group events scheduling transaction | |
1123 | * Perform the group schedulability test as a whole | |
1124 | * Return 0 if success | |
1125 | */ | |
1126 | static int sparc_pmu_commit_txn(const struct pmu *pmu) | |
1127 | { | |
1128 | struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); | |
1129 | int n; | |
1130 | ||
1131 | if (!sparc_pmu) | |
1132 | return -EINVAL; | |
1133 | ||
1134 | cpuc = &__get_cpu_var(cpu_hw_events); | |
1135 | n = cpuc->n_events; | |
1136 | if (check_excludes(cpuc->event, 0, n)) | |
1137 | return -EINVAL; | |
1138 | if (sparc_check_constraints(cpuc->event, cpuc->events, n)) | |
1139 | return -EAGAIN; | |
1140 | ||
8d2cacbb | 1141 | cpuc->group_flag &= ~PERF_EVENT_TXN; |
a13c3afd LM |
1142 | return 0; |
1143 | } | |
1144 | ||
59abbd1e DM |
1145 | static const struct pmu pmu = { |
1146 | .enable = sparc_pmu_enable, | |
1147 | .disable = sparc_pmu_disable, | |
1148 | .read = sparc_pmu_read, | |
1149 | .unthrottle = sparc_pmu_unthrottle, | |
a13c3afd LM |
1150 | .start_txn = sparc_pmu_start_txn, |
1151 | .cancel_txn = sparc_pmu_cancel_txn, | |
1152 | .commit_txn = sparc_pmu_commit_txn, | |
59abbd1e DM |
1153 | }; |
1154 | ||
cdd6c482 | 1155 | const struct pmu *hw_perf_event_init(struct perf_event *event) |
59abbd1e | 1156 | { |
cdd6c482 | 1157 | int err = __hw_perf_event_init(event); |
59abbd1e DM |
1158 | |
1159 | if (err) | |
1160 | return ERR_PTR(err); | |
1161 | return &pmu; | |
1162 | } | |
1163 | ||
cdd6c482 | 1164 | void perf_event_print_debug(void) |
59abbd1e DM |
1165 | { |
1166 | unsigned long flags; | |
1167 | u64 pcr, pic; | |
1168 | int cpu; | |
1169 | ||
1170 | if (!sparc_pmu) | |
1171 | return; | |
1172 | ||
1173 | local_irq_save(flags); | |
1174 | ||
1175 | cpu = smp_processor_id(); | |
1176 | ||
1177 | pcr = pcr_ops->read(); | |
1178 | read_pic(pic); | |
1179 | ||
1180 | pr_info("\n"); | |
1181 | pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n", | |
1182 | cpu, pcr, pic); | |
1183 | ||
1184 | local_irq_restore(flags); | |
1185 | } | |
1186 | ||
cdd6c482 | 1187 | static int __kprobes perf_event_nmi_handler(struct notifier_block *self, |
d29862f0 | 1188 | unsigned long cmd, void *__args) |
59abbd1e DM |
1189 | { |
1190 | struct die_args *args = __args; | |
1191 | struct perf_sample_data data; | |
cdd6c482 | 1192 | struct cpu_hw_events *cpuc; |
59abbd1e | 1193 | struct pt_regs *regs; |
e7bef6b0 | 1194 | int i; |
59abbd1e | 1195 | |
cdd6c482 | 1196 | if (!atomic_read(&active_events)) |
59abbd1e DM |
1197 | return NOTIFY_DONE; |
1198 | ||
1199 | switch (cmd) { | |
1200 | case DIE_NMI: | |
1201 | break; | |
1202 | ||
1203 | default: | |
1204 | return NOTIFY_DONE; | |
1205 | } | |
1206 | ||
1207 | regs = args->regs; | |
1208 | ||
dc1d628a | 1209 | perf_sample_data_init(&data, 0); |
59abbd1e | 1210 | |
cdd6c482 | 1211 | cpuc = &__get_cpu_var(cpu_hw_events); |
e04ed38d DM |
1212 | |
1213 | /* If the PMU has the TOE IRQ enable bits, we need to do a | |
1214 | * dummy write to the %pcr to clear the overflow bits and thus | |
1215 | * the interrupt. | |
1216 | * | |
1217 | * Do this before we peek at the counters to determine | |
1218 | * overflow so we don't lose any events. | |
1219 | */ | |
1220 | if (sparc_pmu->irq_bit) | |
1221 | pcr_ops->write(cpuc->pcr); | |
1222 | ||
e7bef6b0 DM |
1223 | for (i = 0; i < cpuc->n_events; i++) { |
1224 | struct perf_event *event = cpuc->event[i]; | |
1225 | int idx = cpuc->current_idx[i]; | |
cdd6c482 | 1226 | struct hw_perf_event *hwc; |
59abbd1e DM |
1227 | u64 val; |
1228 | ||
cdd6c482 IM |
1229 | hwc = &event->hw; |
1230 | val = sparc_perf_event_update(event, hwc, idx); | |
59abbd1e DM |
1231 | if (val & (1ULL << 31)) |
1232 | continue; | |
1233 | ||
cdd6c482 IM |
1234 | data.period = event->hw.last_period; |
1235 | if (!sparc_perf_event_set_period(event, hwc, idx)) | |
59abbd1e DM |
1236 | continue; |
1237 | ||
cdd6c482 | 1238 | if (perf_event_overflow(event, 1, &data, regs)) |
d1751388 | 1239 | sparc_pmu_disable_event(cpuc, hwc, idx); |
59abbd1e DM |
1240 | } |
1241 | ||
1242 | return NOTIFY_STOP; | |
1243 | } | |
1244 | ||
cdd6c482 IM |
1245 | static __read_mostly struct notifier_block perf_event_nmi_notifier = { |
1246 | .notifier_call = perf_event_nmi_handler, | |
59abbd1e DM |
1247 | }; |
1248 | ||
1249 | static bool __init supported_pmu(void) | |
1250 | { | |
28e8f9be DM |
1251 | if (!strcmp(sparc_pmu_type, "ultra3") || |
1252 | !strcmp(sparc_pmu_type, "ultra3+") || | |
1253 | !strcmp(sparc_pmu_type, "ultra3i") || | |
1254 | !strcmp(sparc_pmu_type, "ultra4+")) { | |
1255 | sparc_pmu = &ultra3_pmu; | |
59abbd1e DM |
1256 | return true; |
1257 | } | |
7eebda60 DM |
1258 | if (!strcmp(sparc_pmu_type, "niagara")) { |
1259 | sparc_pmu = &niagara1_pmu; | |
1260 | return true; | |
1261 | } | |
b73d8847 DM |
1262 | if (!strcmp(sparc_pmu_type, "niagara2")) { |
1263 | sparc_pmu = &niagara2_pmu; | |
1264 | return true; | |
1265 | } | |
59abbd1e DM |
1266 | return false; |
1267 | } | |
1268 | ||
cdd6c482 | 1269 | void __init init_hw_perf_events(void) |
59abbd1e | 1270 | { |
cdd6c482 | 1271 | pr_info("Performance events: "); |
59abbd1e DM |
1272 | |
1273 | if (!supported_pmu()) { | |
1274 | pr_cont("No support for PMU type '%s'\n", sparc_pmu_type); | |
1275 | return; | |
1276 | } | |
1277 | ||
1278 | pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type); | |
1279 | ||
e7bef6b0 DM |
1280 | /* All sparc64 PMUs currently have 2 events. */ |
1281 | perf_max_events = 2; | |
59abbd1e | 1282 | |
cdd6c482 | 1283 | register_die_notifier(&perf_event_nmi_notifier); |
59abbd1e | 1284 | } |
4f6dbe4a DM |
1285 | |
1286 | static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip) | |
1287 | { | |
1288 | if (entry->nr < PERF_MAX_STACK_DEPTH) | |
1289 | entry->ip[entry->nr++] = ip; | |
1290 | } | |
1291 | ||
1292 | static void perf_callchain_kernel(struct pt_regs *regs, | |
1293 | struct perf_callchain_entry *entry) | |
1294 | { | |
1295 | unsigned long ksp, fp; | |
667f0cee DM |
1296 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1297 | int graph = 0; | |
1298 | #endif | |
4f6dbe4a DM |
1299 | |
1300 | callchain_store(entry, PERF_CONTEXT_KERNEL); | |
1301 | callchain_store(entry, regs->tpc); | |
1302 | ||
1303 | ksp = regs->u_regs[UREG_I6]; | |
1304 | fp = ksp + STACK_BIAS; | |
1305 | do { | |
1306 | struct sparc_stackf *sf; | |
1307 | struct pt_regs *regs; | |
1308 | unsigned long pc; | |
1309 | ||
1310 | if (!kstack_valid(current_thread_info(), fp)) | |
1311 | break; | |
1312 | ||
1313 | sf = (struct sparc_stackf *) fp; | |
1314 | regs = (struct pt_regs *) (sf + 1); | |
1315 | ||
1316 | if (kstack_is_trap_frame(current_thread_info(), regs)) { | |
1317 | if (user_mode(regs)) | |
1318 | break; | |
1319 | pc = regs->tpc; | |
1320 | fp = regs->u_regs[UREG_I6] + STACK_BIAS; | |
1321 | } else { | |
1322 | pc = sf->callers_pc; | |
1323 | fp = (unsigned long)sf->fp + STACK_BIAS; | |
1324 | } | |
1325 | callchain_store(entry, pc); | |
667f0cee DM |
1326 | #ifdef CONFIG_FUNCTION_GRAPH_TRACER |
1327 | if ((pc + 8UL) == (unsigned long) &return_to_handler) { | |
1328 | int index = current->curr_ret_stack; | |
1329 | if (current->ret_stack && index >= graph) { | |
1330 | pc = current->ret_stack[index - graph].ret; | |
1331 | callchain_store(entry, pc); | |
1332 | graph++; | |
1333 | } | |
1334 | } | |
1335 | #endif | |
4f6dbe4a DM |
1336 | } while (entry->nr < PERF_MAX_STACK_DEPTH); |
1337 | } | |
1338 | ||
1339 | static void perf_callchain_user_64(struct pt_regs *regs, | |
1340 | struct perf_callchain_entry *entry) | |
1341 | { | |
1342 | unsigned long ufp; | |
1343 | ||
1344 | callchain_store(entry, PERF_CONTEXT_USER); | |
1345 | callchain_store(entry, regs->tpc); | |
1346 | ||
1347 | ufp = regs->u_regs[UREG_I6] + STACK_BIAS; | |
1348 | do { | |
1349 | struct sparc_stackf *usf, sf; | |
1350 | unsigned long pc; | |
1351 | ||
1352 | usf = (struct sparc_stackf *) ufp; | |
1353 | if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) | |
1354 | break; | |
1355 | ||
1356 | pc = sf.callers_pc; | |
1357 | ufp = (unsigned long)sf.fp + STACK_BIAS; | |
1358 | callchain_store(entry, pc); | |
1359 | } while (entry->nr < PERF_MAX_STACK_DEPTH); | |
1360 | } | |
1361 | ||
1362 | static void perf_callchain_user_32(struct pt_regs *regs, | |
1363 | struct perf_callchain_entry *entry) | |
1364 | { | |
1365 | unsigned long ufp; | |
1366 | ||
1367 | callchain_store(entry, PERF_CONTEXT_USER); | |
1368 | callchain_store(entry, regs->tpc); | |
1369 | ||
9e8307ec | 1370 | ufp = regs->u_regs[UREG_I6] & 0xffffffffUL; |
4f6dbe4a DM |
1371 | do { |
1372 | struct sparc_stackf32 *usf, sf; | |
1373 | unsigned long pc; | |
1374 | ||
1375 | usf = (struct sparc_stackf32 *) ufp; | |
1376 | if (__copy_from_user_inatomic(&sf, usf, sizeof(sf))) | |
1377 | break; | |
1378 | ||
1379 | pc = sf.callers_pc; | |
1380 | ufp = (unsigned long)sf.fp; | |
1381 | callchain_store(entry, pc); | |
1382 | } while (entry->nr < PERF_MAX_STACK_DEPTH); | |
1383 | } | |
1384 | ||
1385 | /* Like powerpc we can't get PMU interrupts within the PMU handler, | |
3ad2f3fb | 1386 | * so no need for separate NMI and IRQ chains as on x86. |
4f6dbe4a DM |
1387 | */ |
1388 | static DEFINE_PER_CPU(struct perf_callchain_entry, callchain); | |
1389 | ||
1390 | struct perf_callchain_entry *perf_callchain(struct pt_regs *regs) | |
1391 | { | |
1392 | struct perf_callchain_entry *entry = &__get_cpu_var(callchain); | |
1393 | ||
1394 | entry->nr = 0; | |
1395 | if (!user_mode(regs)) { | |
1396 | stack_trace_flush(); | |
1397 | perf_callchain_kernel(regs, entry); | |
1398 | if (current->mm) | |
1399 | regs = task_pt_regs(current); | |
1400 | else | |
1401 | regs = NULL; | |
1402 | } | |
1403 | if (regs) { | |
1404 | flushw_user(); | |
1405 | if (test_thread_flag(TIF_32BIT)) | |
1406 | perf_callchain_user_32(regs, entry); | |
1407 | else | |
1408 | perf_callchain_user_64(regs, entry); | |
1409 | } | |
1410 | return entry; | |
1411 | } |