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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
b00dc837 2/*
1da177e4
LT
3 * rtrap.S: Preparing for return from trap on Sparc V9.
4 *
5 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
7 */
8
1da177e4
LT
9
10#include <asm/asi.h>
11#include <asm/pstate.h>
12#include <asm/ptrace.h>
13#include <asm/spitfire.h>
14#include <asm/head.h>
15#include <asm/visasm.h>
16#include <asm/processor.h>
17
812cb83a
KT
18#ifdef CONFIG_CONTEXT_TRACKING
19# define SCHEDULE_USER schedule_user
20#else
21# define SCHEDULE_USER schedule
22#endif
23
1da177e4
LT
24 .text
25 .align 32
1da177e4 26__handle_preemption:
812cb83a 27 call SCHEDULE_USER
74a04967
KA
28661: wrpr %g0, RTRAP_PSTATE, %pstate
29 /* If userspace is using ADI, it could potentially pass
30 * a pointer with version tag embedded in it. To maintain
31 * the ADI security, we must re-enable PSTATE.mcde before
32 * we continue execution in the kernel for another thread.
33 */
34 .section .sun_m7_1insn_patch, "ax"
35 .word 661b
36 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
37 .previous
1da177e4
LT
38 ba,pt %xcc, __handle_preemption_continue
39 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
40
41__handle_user_windows:
5b4fc388 42 add %sp, PTREGS_OFF, %o0
1da177e4 43 call fault_in_user_windows
74a04967
KA
44661: wrpr %g0, RTRAP_PSTATE, %pstate
45 /* If userspace is using ADI, it could potentially pass
46 * a pointer with version tag embedded in it. To maintain
47 * the ADI security, we must re-enable PSTATE.mcde before
48 * we continue execution in the kernel for another thread.
49 */
50 .section .sun_m7_1insn_patch, "ax"
51 .word 661b
52 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
53 .previous
caebf910
AV
54 ba,pt %xcc, __handle_preemption_continue
55 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4 56
1da177e4
LT
57__handle_userfpu:
58 rd %fprs, %l5
59 andcc %l5, FPRS_FEF, %g0
60 sethi %hi(TSTATE_PEF), %o0
61 be,a,pn %icc, __handle_userfpu_continue
62 andn %l1, %o0, %l1
63 ba,a,pt %xcc, __handle_userfpu_continue
64
65__handle_signal:
2d7d5f05 66 mov %l5, %o1
2d7d5f05 67 add %sp, PTREGS_OFF, %o0
7697daaa 68 mov %l0, %o2
1da177e4 69 call do_notify_resume
74a04967
KA
70661: wrpr %g0, RTRAP_PSTATE, %pstate
71 /* If userspace is using ADI, it could potentially pass
72 * a pointer with version tag embedded in it. To maintain
73 * the ADI security, we must re-enable PSTATE.mcde before
74 * we continue execution in the kernel for another thread.
75 */
76 .section .sun_m7_1insn_patch, "ax"
77 .word 661b
78 wrpr %g0, RTRAP_PSTATE|PSTATE_MCDE, %pstate
79 .previous
1da177e4 80 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4
LT
81
82 /* Signal delivery can modify pt_regs tstate, so we must
83 * reload it.
84 */
85 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
86 sethi %hi(0xf << 20), %l4
87 and %l1, %l4, %l4
d1f1f98c 88 andn %l1, %l4, %l1
caebf910 89 ba,pt %xcc, __handle_preemption_continue
d1f1f98c 90 srl %l4, 20, %l4
1da177e4 91
5565736e
DM
92 /* When returning from a NMI (%pil==15) interrupt we want to
93 * avoid running softirqs, doing IRQ tracing, preempting, etc.
94 */
95 .globl rtrap_nmi
96rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
97 sethi %hi(0xf << 20), %l4
98 and %l1, %l4, %l4
99 andn %l1, %l4, %l1
100 srl %l4, 20, %l4
101 ba,pt %xcc, rtrap_no_irq_enable
1ca04a4c
RG
102 nop
103 /* Do not actually set the %pil here. We will do that
104 * below after we clear PSTATE_IE in the %pstate register.
105 * If we re-enable interrupts here, we can recurse down
106 * the hardirq stack potentially endlessly, causing a
107 * stack overflow.
108 */
5565736e 109
1da177e4 110 .align 64
7697daaa 111 .globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
1da177e4 112rtrap_irq:
1da177e4 113rtrap:
1da177e4 114 /* mm/ultra.S:xcall_report_regs KNOWS about this load. */
78b7e3d0 115 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
1da177e4
LT
116rtrap_xcall:
117 sethi %hi(0xf << 20), %l4
1da177e4 118 and %l1, %l4, %l4
10e26723
DM
119 andn %l1, %l4, %l1
120 srl %l4, 20, %l4
121#ifdef CONFIG_TRACE_IRQFLAGS
122 brnz,pn %l4, rtrap_no_irq_enable
123 nop
124 call trace_hardirqs_on
125 nop
28a1f533
DM
126 /* Do not actually set the %pil here. We will do that
127 * below after we clear PSTATE_IE in the %pstate register.
128 * If we re-enable interrupts here, we can recurse down
129 * the hardirq stack potentially endlessly, causing a
130 * stack overflow.
131 *
132 * It is tempting to put this test and trace_hardirqs_on
133 * call at the 'rt_continue' label, but that will not work
134 * as that path hits unconditionally and we do not want to
135 * execute this in NMI return paths, for example.
136 */
10e26723 137#endif
5565736e 138rtrap_no_irq_enable:
10e26723 139 andcc %l1, TSTATE_PRIV, %l3
1da177e4 140 bne,pn %icc, to_kernel
10e26723 141 nop
1da177e4
LT
142
143 /* We must hold IRQs off and atomically test schedule+signal
144 * state, then hold them off all the way back to userspace.
10e26723
DM
145 * If we are returning to kernel, none of this matters. Note
146 * that we are disabling interrupts via PSTATE_IE, not using
147 * %pil.
1da177e4
LT
148 *
149 * If we do not do this, there is a window where we would do
150 * the tests, later the signal/resched event arrives but we do
151 * not process it since we are still in kernel mode. It would
152 * take until the next local IRQ before the signal/resched
153 * event would be handled.
154 *
c7d5a005
DM
155 * This also means that if we have to deal with user
156 * windows, we have to redo all of these sched+signal checks
157 * with IRQs disabled.
1da177e4
LT
158 */
159to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
160 wrpr 0, %pil
161__handle_preemption_continue:
162 ldx [%g6 + TI_FLAGS], %l0
163 sethi %hi(_TIF_USER_WORK_MASK), %o0
164 or %o0, %lo(_TIF_USER_WORK_MASK), %o0
165 andcc %l0, %o0, %g0
166 sethi %hi(TSTATE_PEF), %o0
167 be,pt %xcc, user_nowork
168 andcc %l1, %o0, %g0
169 andcc %l0, _TIF_NEED_RESCHED, %g0
170 bne,pn %xcc, __handle_preemption
e35a8925 171 andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
1da177e4 172 bne,pn %xcc, __handle_signal
1da177e4
LT
173 ldub [%g6 + TI_WSAVED], %o2
174 brnz,pn %o2, __handle_user_windows
175 nop
1da177e4 176 sethi %hi(TSTATE_PEF), %o0
c7d5a005 177 andcc %l1, %o0, %g0
1da177e4
LT
178
179 /* This fpdepth clear is necessary for non-syscall rtraps only */
180user_nowork:
181 bne,pn %xcc, __handle_userfpu
182 stb %g0, [%g6 + TI_FPDEPTH]
183__handle_userfpu_continue:
184
185rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
186 ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
187
188 ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
189 ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
190 ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
56fb4df6 191 brz,pt %l3, 1f
314981ac
DM
192 mov %g6, %l2
193
56fb4df6 194 /* Must do this before thread reg is clobbered below. */
ffe483d5 195 LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
74bf4312
DM
1961:
197 ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
1da177e4 198 ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
936f482a
DM
199
200 /* Normal globals are restored, go to trap globals. */
201661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
af02bec6
DM
202 nop
203 .section .sun4v_2insn_patch, "ax"
936f482a 204 .word 661b
af02bec6 205 wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
936f482a
DM
206 SET_GL(1)
207 .previous
208
314981ac
DM
209 mov %l2, %g6
210
1da177e4
LT
211 ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
212 ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
213
214 ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
215 ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
216 ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
217 ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
218 ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
219 ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
220 ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
221 ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
222
223 ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
224 wr %o3, %g0, %y
1da177e4
LT
225 wrpr %l4, 0x0, %pil
226 wrpr %g0, 0x1, %tl
28e61036 227 andn %l1, TSTATE_SYSCALL, %l1
1da177e4
LT
228 wrpr %l1, %g0, %tstate
229 wrpr %l2, %g0, %tpc
230 wrpr %o2, %g0, %tnpc
231
232 brnz,pn %l3, kern_rtt
233 mov PRIMARY_CONTEXT, %l7
8b11bd12
DM
234
235661: ldxa [%l7 + %l7] ASI_DMMU, %l0
236 .section .sun4v_1insn_patch, "ax"
237 .word 661b
238 ldxa [%l7 + %l7] ASI_MMU, %l0
239 .previous
240
0835ae0f
DM
241 sethi %hi(sparc64_kern_pri_nuc_bits), %l1
242 ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
1da177e4 243 or %l0, %l1, %l0
8b11bd12
DM
244
245661: stxa %l0, [%l7] ASI_DMMU
246 .section .sun4v_1insn_patch, "ax"
247 .word 661b
248 stxa %l0, [%l7] ASI_MMU
249 .previous
250
4da808c3
DM
251 sethi %hi(KERNBASE), %l7
252 flush %l7
1da177e4
LT
253 rdpr %wstate, %l1
254 rdpr %otherwin, %l2
255 srl %l1, 3, %l1
256
a7159a87
AY
257661: wrpr %l2, %g0, %canrestore
258 .section .fast_win_ctrl_1insn_patch, "ax"
259 .word 661b
260 .word 0x89880000 ! normalw
261 .previous
262
1da177e4 263 wrpr %l1, %g0, %wstate
314ef685 264 brnz,pt %l2, user_rtt_restore
a7159a87
AY
265661: wrpr %g0, %g0, %otherwin
266 .section .fast_win_ctrl_1insn_patch, "ax"
267 .word 661b
268 nop
269 .previous
314ef685
DM
270
271 ldx [%g6 + TI_FLAGS], %g3
272 wr %g0, ASI_AIUP, %asi
273 rdpr %cwp, %g1
274 andcc %g3, _TIF_32BIT, %g0
275 sub %g1, 1, %g1
276 bne,pt %xcc, user_rtt_fill_32bit
277 wrpr %g1, %cwp
278 ba,a,pt %xcc, user_rtt_fill_64bit
0ae2d26f 279 nop
314ef685 280
7cafc0b8
DM
281user_rtt_fill_fixup_dax:
282 ba,pt %xcc, user_rtt_fill_fixup_common
283 mov 1, %g3
314ef685 284
7cafc0b8
DM
285user_rtt_fill_fixup_mna:
286 ba,pt %xcc, user_rtt_fill_fixup_common
287 mov 2, %g3
314ef685 288
7cafc0b8
DM
289user_rtt_fill_fixup:
290 ba,pt %xcc, user_rtt_fill_fixup_common
291 clr %g3
314ef685
DM
292
293user_rtt_pre_restore:
294 add %g1, 1, %g1
295 wrpr %g1, 0x0, %cwp
296
297user_rtt_restore:
1da177e4
LT
298 restore
299 rdpr %canrestore, %g1
300 wrpr %g1, 0x0, %cleanwin
301 retry
302 nop
303
314ef685
DM
304kern_rtt: rdpr %canrestore, %g1
305 brz,pn %g1, kern_rtt_fill
306 nop
307kern_rtt_restore:
ada44a04 308 stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
314ef685 309 restore
1da177e4 310 retry
314ef685 311
1da177e4
LT
312to_kernel:
313#ifdef CONFIG_PREEMPT
314 ldsw [%g6 + TI_PRE_COUNT], %l5
315 brnz %l5, kern_fpucheck
316 ldx [%g6 + TI_FLAGS], %l5
317 andcc %l5, _TIF_NEED_RESCHED, %g0
318 be,pt %xcc, kern_fpucheck
10e26723
DM
319 nop
320 cmp %l4, 0
1da177e4 321 bne,pn %xcc, kern_fpucheck
9385d949
TG
322 nop
323 call preempt_schedule_irq
1da177e4
LT
324 nop
325 ba,pt %xcc, rtrap
1da177e4
LT
326#endif
327kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
328 brz,pt %l5, rt_continue
329 srl %l5, 1, %o0
330 add %g6, TI_FPSAVED, %l6
331 ldub [%l6 + %o0], %l2
332 sub %l5, 2, %l5
333
334 add %g6, TI_GSR, %o1
335 andcc %l2, (FPRS_FEF|FPRS_DU), %g0
336 be,pt %icc, 2f
337 and %l2, FPRS_DL, %l6
338 andcc %l2, FPRS_FEF, %g0
339 be,pn %icc, 5f
340 sll %o0, 3, %o5
341 rd %fprs, %g1
342
343 wr %g1, FPRS_FEF, %fprs
344 ldx [%o1 + %o5], %g1
345 add %g6, TI_XFSR, %o1
1da177e4
LT
346 sll %o0, 8, %o2
347 add %g6, TI_FPREGS, %o3
348 brz,pn %l6, 1f
349 add %g6, TI_FPREGS+0x40, %o4
350
ba639933 351 membar #Sync
1da177e4
LT
352 ldda [%o3 + %o2] ASI_BLK_P, %f0
353 ldda [%o4 + %o2] ASI_BLK_P, %f16
ba639933 354 membar #Sync
1da177e4
LT
3551: andcc %l2, FPRS_DU, %g0
356 be,pn %icc, 1f
357 wr %g1, 0, %gsr
358 add %o2, 0x80, %o2
ba639933 359 membar #Sync
1da177e4
LT
360 ldda [%o3 + %o2] ASI_BLK_P, %f32
361 ldda [%o4 + %o2] ASI_BLK_P, %f48
1da177e4
LT
3621: membar #Sync
363 ldx [%o1 + %o5], %fsr
3642: stb %l5, [%g6 + TI_FPDEPTH]
365 ba,pt %xcc, rt_continue
366 nop
3675: wr %g0, FPRS_FEF, %fprs
1da177e4
LT
368 sll %o0, 8, %o2
369
370 add %g6, TI_FPREGS+0x80, %o3
371 add %g6, TI_FPREGS+0xc0, %o4
ba639933 372 membar #Sync
1da177e4
LT
373 ldda [%o3 + %o2] ASI_BLK_P, %f32
374 ldda [%o4 + %o2] ASI_BLK_P, %f48
375 membar #Sync
376 wr %g0, FPRS_DU, %fprs
377 ba,pt %xcc, rt_continue
378 stb %l5, [%g6 + TI_FPDEPTH]