[mirror_ubuntu-artful-kernel.git] / arch / sparc / kernel / rtrap_64.S

/*
 * rtrap.S: Preparing for return from trap on Sparc V9.
 *
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
 */


#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/visasm.h>
#include <asm/processor.h>

#define		RTRAP_PSTATE		(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
#define		RTRAP_PSTATE_IRQOFF	(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV)
#define		RTRAP_PSTATE_AG_IRQOFF	(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)

#ifdef CONFIG_CONTEXT_TRACKING
# define SCHEDULE_USER schedule_user
#else
# define SCHEDULE_USER schedule
#endif

		.text
		.align			32
__handle_preemption:
		call			SCHEDULE_USER
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_user_windows:
		call			fault_in_user_windows
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_userfpu:
		rd			%fprs, %l5
		andcc			%l5, FPRS_FEF, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,a,pn			%icc, __handle_userfpu_continue
		 andn			%l1, %o0, %l1
		ba,a,pt			%xcc, __handle_userfpu_continue

__handle_signal:
		mov			%l5, %o1
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o2
		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_preemption_continue
		 andn			%l1, %l4, %l1

		/* When returning from a NMI (%pil==15) interrupt we want to
		 * avoid running softirqs, doing IRQ tracing, preempting, etc.
		 */
		.globl			rtrap_nmi
rtrap_nmi:	ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
		ba,pt			%xcc, rtrap_no_irq_enable
		nop
		/* Do not actually set the %pil here.  We will do that
		 * below after we clear PSTATE_IE in the %pstate register.
		 * If we re-enable interrupts here, we can recurse down
		 * the hardirq stack potentially endlessly, causing a
		 * stack overflow.
		 */

		.align			64
		.globl			rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
rtrap_irq:
rtrap:
		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
rtrap_xcall:
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
#ifdef CONFIG_TRACE_IRQFLAGS
		brnz,pn			%l4, rtrap_no_irq_enable
		 nop
		call			trace_hardirqs_on
		 nop
		/* Do not actually set the %pil here.  We will do that
		 * below after we clear PSTATE_IE in the %pstate register.
		 * If we re-enable interrupts here, we can recurse down
		 * the hardirq stack potentially endlessly, causing a
		 * stack overflow.
		 *
		 * It is tempting to put this test and trace_hardirqs_on
		 * call at the 'rt_continue' label, but that will not work
		 * as that path hits unconditionally and we do not want to
		 * execute this in NMI return paths, for example.
		 */
#endif
rtrap_no_irq_enable:
		andcc			%l1, TSTATE_PRIV, %l3
		bne,pn			%icc, to_kernel
		 nop

		/* We must hold IRQs off and atomically test schedule+signal
		 * state, then hold them off all the way back to userspace.
		 * If we are returning to kernel, none of this matters.  Note
		 * that we are disabling interrupts via PSTATE_IE, not using
		 * %pil.
		 *
		 * If we do not do this, there is a window where we would do
		 * the tests, later the signal/resched event arrives but we do
		 * not process it since we are still in kernel mode.  It would
		 * take until the next local IRQ before the signal/resched
		 * event would be handled.
		 *
		 * This also means that if we have to deal with user
		 * windows, we have to redo all of these sched+signal checks
		 * with IRQs disabled.
		 */
to_user:	wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		wrpr			0, %pil
__handle_preemption_continue:
		ldx			[%g6 + TI_FLAGS], %l0
		sethi			%hi(_TIF_USER_WORK_MASK), %o0
		or			%o0, %lo(_TIF_USER_WORK_MASK), %o0
		andcc			%l0, %o0, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,pt			%xcc, user_nowork
		 andcc			%l1, %o0, %g0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		bne,pn			%xcc, __handle_preemption
		 andcc			%l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
		bne,pn			%xcc, __handle_signal
		 ldub			[%g6 + TI_WSAVED], %o2
		brnz,pn			%o2, __handle_user_windows
		 nop
		sethi			%hi(TSTATE_PEF), %o0
		andcc			%l1, %o0, %g0

		/* This fpdepth clear is necessary for non-syscall rtraps only */
user_nowork:
		bne,pn			%xcc, __handle_userfpu
		 stb			%g0, [%g6 + TI_FPDEPTH]
__handle_userfpu_continue:

rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2

		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
		brz,pt			%l3, 1f
		mov			%g6, %l2

		/* Must do this before thread reg is clobbered below.  */
		LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7

		/* Normal globals are restored, go to trap globals.  */
661:		wrpr			%g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
		nop
		.section		.sun4v_2insn_patch, "ax"
		.word			661b
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		SET_GL(1)
		.previous

		mov			%l2, %g6

		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1

		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2

		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
		wr			%o3, %g0, %y
		wrpr			%l4, 0x0, %pil
		wrpr			%g0, 0x1, %tl
		andn			%l1, TSTATE_SYSCALL, %l1
		wrpr			%l1, %g0, %tstate
		wrpr			%l2, %g0, %tpc
		wrpr			%o2, %g0, %tnpc

		brnz,pn			%l3, kern_rtt
		 mov			PRIMARY_CONTEXT, %l7

661:		ldxa			[%l7 + %l7] ASI_DMMU, %l0
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		ldxa			[%l7 + %l7] ASI_MMU, %l0
		.previous

		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1
		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
		or			%l0, %l1, %l0

661:		stxa			%l0, [%l7] ASI_DMMU
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		stxa			%l0, [%l7] ASI_MMU
		.previous

		sethi			%hi(KERNBASE), %l7
		flush			%l7
		rdpr			%wstate, %l1
		rdpr			%otherwin, %l2
		srl			%l1, 3, %l1

		wrpr			%l2, %g0, %canrestore
		wrpr			%l1, %g0, %wstate
		brnz,pt			%l2, user_rtt_restore
		 wrpr			%g0, %g0, %otherwin

		ldx			[%g6 + TI_FLAGS], %g3
		wr			%g0, ASI_AIUP, %asi
		rdpr			%cwp, %g1
		andcc			%g3, _TIF_32BIT, %g0
		sub			%g1, 1, %g1
		bne,pt			%xcc, user_rtt_fill_32bit
		 wrpr			%g1, %cwp
		ba,a,pt			%xcc, user_rtt_fill_64bit

user_rtt_fill_fixup:
		rdpr	%cwp, %g1
		add	%g1, 1, %g1
		wrpr	%g1, 0x0, %cwp

		rdpr	%wstate, %g2
		sll	%g2, 3, %g2
		wrpr	%g2, 0x0, %wstate

		/* We know %canrestore and %otherwin are both zero.  */

		sethi	%hi(sparc64_kern_pri_context), %g2
		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g2
		mov	PRIMARY_CONTEXT, %g1

661:		stxa	%g2, [%g1] ASI_DMMU
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		stxa	%g2, [%g1] ASI_MMU
		.previous

		sethi	%hi(KERNBASE), %g1
		flush	%g1

		or	%g4, FAULT_CODE_WINFIXUP, %g4
		stb	%g4, [%g6 + TI_FAULT_CODE]
		stx	%g5, [%g6 + TI_FAULT_ADDR]

		mov	%g6, %l1
		wrpr	%g0, 0x0, %tl

661:		nop
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		SET_GL(0)
		.previous

		wrpr	%g0, RTRAP_PSTATE, %pstate

		mov	%l1, %g6
		ldx	[%g6 + TI_TASK], %g4
		LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
		call	do_sparc64_fault
		 add	%sp, PTREGS_OFF, %o0
		ba,pt	%xcc, rtrap
		 nop

user_rtt_pre_restore:
		add			%g1, 1, %g1
		wrpr			%g1, 0x0, %cwp

user_rtt_restore:
		restore
		rdpr			%canrestore, %g1
		wrpr			%g1, 0x0, %cleanwin
		retry
		nop

kern_rtt:	rdpr			%canrestore, %g1
		brz,pn			%g1, kern_rtt_fill
		 nop
kern_rtt_restore:
		stw			%g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
		restore
		retry

to_kernel:
#ifdef CONFIG_PREEMPT
		ldsw			[%g6 + TI_PRE_COUNT], %l5
		brnz			%l5, kern_fpucheck
		 ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, kern_fpucheck
		 nop
		cmp			%l4, 0
		bne,pn			%xcc, kern_fpucheck
		 nop
		call			preempt_schedule_irq
		 nop
		ba,pt			%xcc, rtrap
#endif
kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
		brz,pt			%l5, rt_continue
		 srl			%l5, 1, %o0
		add			%g6, TI_FPSAVED, %l6
		ldub			[%l6 + %o0], %l2
		sub			%l5, 2, %l5

		add			%g6, TI_GSR, %o1
		andcc			%l2, (FPRS_FEF|FPRS_DU), %g0
		be,pt			%icc, 2f
		 and			%l2, FPRS_DL, %l6
		andcc			%l2, FPRS_FEF, %g0
		be,pn			%icc, 5f
		 sll			%o0, 3, %o5
		rd			%fprs, %g1

		wr			%g1, FPRS_FEF, %fprs
		ldx			[%o1 + %o5], %g1
		add			%g6, TI_XFSR, %o1
		sll			%o0, 8, %o2
		add			%g6, TI_FPREGS, %o3
		brz,pn			%l6, 1f
		 add			%g6, TI_FPREGS+0x40, %o4

		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f0
		ldda			[%o4 + %o2] ASI_BLK_P, %f16
		membar			#Sync
1:		andcc			%l2, FPRS_DU, %g0
		be,pn			%icc, 1f
		 wr			%g1, 0, %gsr
		add			%o2, 0x80, %o2
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
1:		membar			#Sync
		ldx			[%o1 + %o5], %fsr
2:		stb			%l5, [%g6 + TI_FPDEPTH]
		ba,pt			%xcc, rt_continue
		 nop
5:		wr			%g0, FPRS_FEF, %fprs
		sll			%o0, 8, %o2

		add			%g6, TI_FPREGS+0x80, %o3
		add			%g6, TI_FPREGS+0xc0, %o4
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
		membar			#Sync
		wr			%g0, FPRS_DU, %fprs
		ba,pt			%xcc, rt_continue
		 stb			%l5, [%g6 + TI_FPDEPTH]
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* rtrap.S: Preparing for return from trap on Sparc V9.
	3	*
	4	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	5	* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
	6	*/
	7
1da177e4 LT	8
	9	#include <asm/asi.h>
	10	#include <asm/pstate.h>
	11	#include <asm/ptrace.h>
	12	#include <asm/spitfire.h>
	13	#include <asm/head.h>
	14	#include <asm/visasm.h>
	15	#include <asm/processor.h>
	16
64f2dde3 DM	17	#define RTRAP_PSTATE (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_IE)
	18	#define RTRAP_PSTATE_IRQOFF (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV)
	19	#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_AG)
1da177e4	20
812cb83a KT	21	#ifdef CONFIG_CONTEXT_TRACKING
	22	# define SCHEDULE_USER schedule_user
	23	#else
	24	# define SCHEDULE_USER schedule
	25	#endif
	26
1da177e4 LT	27	.text
1da177e4 LT	28	.align 32
1da177e4	29	__handle_preemption:
812cb83a	30	call SCHEDULE_USER
1da177e4 LT	31	wrpr %g0, RTRAP_PSTATE, %pstate
	32	ba,pt %xcc, __handle_preemption_continue
	33	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	34
	35	__handle_user_windows:
	36	call fault_in_user_windows
	37	wrpr %g0, RTRAP_PSTATE, %pstate
caebf910 AV	38	ba,pt %xcc, __handle_preemption_continue
caebf910 AV	39	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4	40
1da177e4 LT	41	__handle_userfpu:
	42	rd %fprs, %l5
	43	andcc %l5, FPRS_FEF, %g0
	44	sethi %hi(TSTATE_PEF), %o0
	45	be,a,pn %icc, __handle_userfpu_continue
	46	andn %l1, %o0, %l1
	47	ba,a,pt %xcc, __handle_userfpu_continue
	48
	49	__handle_signal:
2d7d5f05	50	mov %l5, %o1
2d7d5f05	51	add %sp, PTREGS_OFF, %o0
7697daaa	52	mov %l0, %o2
1da177e4 LT	53	call do_notify_resume
	54	wrpr %g0, RTRAP_PSTATE, %pstate
	55	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4 LT	56
	57	/* Signal delivery can modify pt_regs tstate, so we must
	58	* reload it.
	59	*/
	60	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	61	sethi %hi(0xf << 20), %l4
	62	and %l1, %l4, %l4
caebf910	63	ba,pt %xcc, __handle_preemption_continue
1da177e4 LT	64	andn %l1, %l4, %l1
1da177e4 LT	65
5565736e DM	66	/* When returning from a NMI (%pil==15) interrupt we want to
	67	* avoid running softirqs, doing IRQ tracing, preempting, etc.
	68	*/
	69	.globl rtrap_nmi
	70	rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	71	sethi %hi(0xf << 20), %l4
	72	and %l1, %l4, %l4
	73	andn %l1, %l4, %l1
	74	srl %l4, 20, %l4
	75	ba,pt %xcc, rtrap_no_irq_enable
1ca04a4c RG	76	nop
	77	/* Do not actually set the %pil here. We will do that
	78	* below after we clear PSTATE_IE in the %pstate register.
	79	* If we re-enable interrupts here, we can recurse down
	80	* the hardirq stack potentially endlessly, causing a
	81	* stack overflow.
	82	*/
5565736e	83
1da177e4	84	.align 64
7697daaa	85	.globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
1da177e4	86	rtrap_irq:
1da177e4	87	rtrap:
1da177e4	88	/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
78b7e3d0	89	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
1da177e4 LT	90	rtrap_xcall:
1da177e4 LT	91	sethi %hi(0xf << 20), %l4
1da177e4	92	and %l1, %l4, %l4
10e26723 DM	93	andn %l1, %l4, %l1
	94	srl %l4, 20, %l4
	95	#ifdef CONFIG_TRACE_IRQFLAGS
	96	brnz,pn %l4, rtrap_no_irq_enable
	97	nop
	98	call trace_hardirqs_on
	99	nop
28a1f533 DM	100	/* Do not actually set the %pil here. We will do that
	101	* below after we clear PSTATE_IE in the %pstate register.
	102	* If we re-enable interrupts here, we can recurse down
	103	* the hardirq stack potentially endlessly, causing a
	104	* stack overflow.
	105	*
	106	* It is tempting to put this test and trace_hardirqs_on
	107	* call at the 'rt_continue' label, but that will not work
	108	* as that path hits unconditionally and we do not want to
	109	* execute this in NMI return paths, for example.
	110	*/
10e26723	111	#endif
5565736e	112	rtrap_no_irq_enable:
10e26723	113	andcc %l1, TSTATE_PRIV, %l3
1da177e4	114	bne,pn %icc, to_kernel
10e26723	115	nop
1da177e4 LT	116
	117	/* We must hold IRQs off and atomically test schedule+signal
	118	* state, then hold them off all the way back to userspace.
10e26723 DM	119	* If we are returning to kernel, none of this matters. Note
	120	* that we are disabling interrupts via PSTATE_IE, not using
	121	* %pil.
1da177e4 LT	122	*
	123	* If we do not do this, there is a window where we would do
	124	* the tests, later the signal/resched event arrives but we do
	125	* not process it since we are still in kernel mode. It would
	126	* take until the next local IRQ before the signal/resched
	127	* event would be handled.
	128	*
c7d5a005 DM	129	* This also means that if we have to deal with user
	130	* windows, we have to redo all of these sched+signal checks
	131	* with IRQs disabled.
1da177e4 LT	132	*/
	133	to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	134	wrpr 0, %pil
	135	__handle_preemption_continue:
	136	ldx [%g6 + TI_FLAGS], %l0
	137	sethi %hi(_TIF_USER_WORK_MASK), %o0
	138	or %o0, %lo(_TIF_USER_WORK_MASK), %o0
	139	andcc %l0, %o0, %g0
	140	sethi %hi(TSTATE_PEF), %o0
	141	be,pt %xcc, user_nowork
	142	andcc %l1, %o0, %g0
	143	andcc %l0, _TIF_NEED_RESCHED, %g0
	144	bne,pn %xcc, __handle_preemption
e35a8925	145	andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
1da177e4	146	bne,pn %xcc, __handle_signal
1da177e4 LT	147	ldub [%g6 + TI_WSAVED], %o2
	148	brnz,pn %o2, __handle_user_windows
	149	nop
1da177e4	150	sethi %hi(TSTATE_PEF), %o0
c7d5a005	151	andcc %l1, %o0, %g0
1da177e4 LT	152
	153	/* This fpdepth clear is necessary for non-syscall rtraps only */
	154	user_nowork:
	155	bne,pn %xcc, __handle_userfpu
	156	stb %g0, [%g6 + TI_FPDEPTH]
	157	__handle_userfpu_continue:
	158
	159	rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
	160	ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
	161
	162	ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
	163	ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
	164	ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
56fb4df6	165	brz,pt %l3, 1f
314981ac DM	166	mov %g6, %l2
314981ac DM	167
56fb4df6	168	/* Must do this before thread reg is clobbered below. */
ffe483d5	169	LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
74bf4312 DM	170	1:
74bf4312 DM	171	ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
1da177e4	172	ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
936f482a DM	173
	174	/* Normal globals are restored, go to trap globals. */
	175	661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
af02bec6 DM	176	nop
af02bec6 DM	177	.section .sun4v_2insn_patch, "ax"
936f482a	178	.word 661b
af02bec6	179	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
936f482a DM	180	SET_GL(1)
	181	.previous
	182
314981ac DM	183	mov %l2, %g6
314981ac DM	184
1da177e4 LT	185	ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
	186	ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
	187
	188	ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
	189	ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
	190	ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
	191	ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
	192	ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
	193	ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
	194	ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
	195	ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
	196
	197	ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
	198	wr %o3, %g0, %y
1da177e4 LT	199	wrpr %l4, 0x0, %pil
1da177e4 LT	200	wrpr %g0, 0x1, %tl
28e61036	201	andn %l1, TSTATE_SYSCALL, %l1
1da177e4 LT	202	wrpr %l1, %g0, %tstate
	203	wrpr %l2, %g0, %tpc
	204	wrpr %o2, %g0, %tnpc
	205
	206	brnz,pn %l3, kern_rtt
	207	mov PRIMARY_CONTEXT, %l7
8b11bd12 DM	208
	209	661: ldxa [%l7 + %l7] ASI_DMMU, %l0
	210	.section .sun4v_1insn_patch, "ax"
	211	.word 661b
	212	ldxa [%l7 + %l7] ASI_MMU, %l0
	213	.previous
	214
0835ae0f DM	215	sethi %hi(sparc64_kern_pri_nuc_bits), %l1
0835ae0f DM	216	ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
1da177e4	217	or %l0, %l1, %l0
8b11bd12 DM	218
	219	661: stxa %l0, [%l7] ASI_DMMU
	220	.section .sun4v_1insn_patch, "ax"
	221	.word 661b
	222	stxa %l0, [%l7] ASI_MMU
	223	.previous
	224
4da808c3 DM	225	sethi %hi(KERNBASE), %l7
4da808c3 DM	226	flush %l7
1da177e4 LT	227	rdpr %wstate, %l1
	228	rdpr %otherwin, %l2
	229	srl %l1, 3, %l1
	230
	231	wrpr %l2, %g0, %canrestore
	232	wrpr %l1, %g0, %wstate
314ef685 DM	233	brnz,pt %l2, user_rtt_restore
	234	wrpr %g0, %g0, %otherwin
	235
	236	ldx [%g6 + TI_FLAGS], %g3
	237	wr %g0, ASI_AIUP, %asi
	238	rdpr %cwp, %g1
	239	andcc %g3, _TIF_32BIT, %g0
	240	sub %g1, 1, %g1
	241	bne,pt %xcc, user_rtt_fill_32bit
	242	wrpr %g1, %cwp
	243	ba,a,pt %xcc, user_rtt_fill_64bit
	244
	245	user_rtt_fill_fixup:
	246	rdpr %cwp, %g1
	247	add %g1, 1, %g1
	248	wrpr %g1, 0x0, %cwp
	249
	250	rdpr %wstate, %g2
	251	sll %g2, 3, %g2
	252	wrpr %g2, 0x0, %wstate
	253
	254	/* We know %canrestore and %otherwin are both zero. */
	255
	256	sethi %hi(sparc64_kern_pri_context), %g2
	257	ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
	258	mov PRIMARY_CONTEXT, %g1
8b11bd12 DM	259
	260	661: stxa %g2, [%g1] ASI_DMMU
	261	.section .sun4v_1insn_patch, "ax"
	262	.word 661b
	263	stxa %g2, [%g1] ASI_MMU
	264	.previous
	265
314ef685 DM	266	sethi %hi(KERNBASE), %g1
	267	flush %g1
	268
	269	or %g4, FAULT_CODE_WINFIXUP, %g4
	270	stb %g4, [%g6 + TI_FAULT_CODE]
	271	stx %g5, [%g6 + TI_FAULT_ADDR]
	272
	273	mov %g6, %l1
	274	wrpr %g0, 0x0, %tl
936f482a DM	275
936f482a DM	276	661: nop
df7d6aec	277	.section .sun4v_1insn_patch, "ax"
936f482a DM	278	.word 661b
	279	SET_GL(0)
	280	.previous
	281
fc504928 DM	282	wrpr %g0, RTRAP_PSTATE, %pstate
fc504928 DM	283
314ef685 DM	284	mov %l1, %g6
	285	ldx [%g6 + TI_TASK], %g4
	286	LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
	287	call do_sparc64_fault
	288	add %sp, PTREGS_OFF, %o0
	289	ba,pt %xcc, rtrap
	290	nop
	291
	292	user_rtt_pre_restore:
	293	add %g1, 1, %g1
	294	wrpr %g1, 0x0, %cwp
	295
	296	user_rtt_restore:
1da177e4 LT	297	restore
	298	rdpr %canrestore, %g1
	299	wrpr %g1, 0x0, %cleanwin
	300	retry
	301	nop
	302
314ef685 DM	303	kern_rtt: rdpr %canrestore, %g1
	304	brz,pn %g1, kern_rtt_fill
	305	nop
	306	kern_rtt_restore:
ada44a04	307	stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
314ef685	308	restore
1da177e4	309	retry
314ef685	310
1da177e4 LT	311	to_kernel:
	312	#ifdef CONFIG_PREEMPT
	313	ldsw [%g6 + TI_PRE_COUNT], %l5
	314	brnz %l5, kern_fpucheck
	315	ldx [%g6 + TI_FLAGS], %l5
	316	andcc %l5, _TIF_NEED_RESCHED, %g0
	317	be,pt %xcc, kern_fpucheck
10e26723 DM	318	nop
10e26723 DM	319	cmp %l4, 0
1da177e4	320	bne,pn %xcc, kern_fpucheck
9385d949 TG	321	nop
9385d949 TG	322	call preempt_schedule_irq
1da177e4 LT	323	nop
1da177e4 LT	324	ba,pt %xcc, rtrap
1da177e4 LT	325	#endif
	326	kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
	327	brz,pt %l5, rt_continue
	328	srl %l5, 1, %o0
	329	add %g6, TI_FPSAVED, %l6
	330	ldub [%l6 + %o0], %l2
	331	sub %l5, 2, %l5
	332
	333	add %g6, TI_GSR, %o1
	334	andcc %l2, (FPRS_FEF\|FPRS_DU), %g0
	335	be,pt %icc, 2f
	336	and %l2, FPRS_DL, %l6
	337	andcc %l2, FPRS_FEF, %g0
	338	be,pn %icc, 5f
	339	sll %o0, 3, %o5
	340	rd %fprs, %g1
	341
	342	wr %g1, FPRS_FEF, %fprs
	343	ldx [%o1 + %o5], %g1
	344	add %g6, TI_XFSR, %o1
1da177e4 LT	345	sll %o0, 8, %o2
	346	add %g6, TI_FPREGS, %o3
	347	brz,pn %l6, 1f
	348	add %g6, TI_FPREGS+0x40, %o4
	349
ba639933	350	membar #Sync
1da177e4 LT	351	ldda [%o3 + %o2] ASI_BLK_P, %f0
1da177e4 LT	352	ldda [%o4 + %o2] ASI_BLK_P, %f16
ba639933	353	membar #Sync
1da177e4 LT	354	1: andcc %l2, FPRS_DU, %g0
	355	be,pn %icc, 1f
	356	wr %g1, 0, %gsr
	357	add %o2, 0x80, %o2
ba639933	358	membar #Sync
1da177e4 LT	359	ldda [%o3 + %o2] ASI_BLK_P, %f32
1da177e4 LT	360	ldda [%o4 + %o2] ASI_BLK_P, %f48
1da177e4 LT	361	1: membar #Sync
	362	ldx [%o1 + %o5], %fsr
	363	2: stb %l5, [%g6 + TI_FPDEPTH]
	364	ba,pt %xcc, rt_continue
	365	nop
	366	5: wr %g0, FPRS_FEF, %fprs
1da177e4 LT	367	sll %o0, 8, %o2
	368
	369	add %g6, TI_FPREGS+0x80, %o3
	370	add %g6, TI_FPREGS+0xc0, %o4
ba639933	371	membar #Sync
1da177e4 LT	372	ldda [%o3 + %o2] ASI_BLK_P, %f32
	373	ldda [%o4 + %o2] ASI_BLK_P, %f48
	374	membar #Sync
	375	wr %g0, FPRS_DU, %fprs
	376	ba,pt %xcc, rt_continue
	377	stb %l5, [%g6 + TI_FPDEPTH]