[mirror_ubuntu-artful-kernel.git] / arch / sparc / kernel / rtrap_64.S

/*
 * rtrap.S: Preparing for return from trap on Sparc V9.
 *
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
 */


#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/visasm.h>
#include <asm/processor.h>

#define		RTRAP_PSTATE		(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE)
#define		RTRAP_PSTATE_IRQOFF	(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV)
#define		RTRAP_PSTATE_AG_IRQOFF	(PSTATE_TSO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG)

		.text
		.align			32
__handle_preemption:
		call			schedule
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_user_windows:
		call			fault_in_user_windows
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_userfpu:
		rd			%fprs, %l5
		andcc			%l5, FPRS_FEF, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,a,pn			%icc, __handle_userfpu_continue
		 andn			%l1, %o0, %l1
		ba,a,pt			%xcc, __handle_userfpu_continue

__handle_signal:
		mov			%l5, %o1
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o2
		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_preemption_continue
		 andn			%l1, %l4, %l1

		/* When returning from a NMI (%pil==15) interrupt we want to
		 * avoid running softirqs, doing IRQ tracing, preempting, etc.
		 */
		.globl			rtrap_nmi
rtrap_nmi:	ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
		ba,pt			%xcc, rtrap_no_irq_enable
		 wrpr			%l4, %pil

		.align			64
		.globl			rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
rtrap_irq:
rtrap:
		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
rtrap_xcall:
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
#ifdef CONFIG_TRACE_IRQFLAGS
		brnz,pn			%l4, rtrap_no_irq_enable
		 nop
		call			trace_hardirqs_on
		 nop
		/* Do not actually set the %pil here.  We will do that
		 * below after we clear PSTATE_IE in the %pstate register.
		 * If we re-enable interrupts here, we can recurse down
		 * the hardirq stack potentially endlessly, causing a
		 * stack overflow.
		 *
		 * It is tempting to put this test and trace_hardirqs_on
		 * call at the 'rt_continue' label, but that will not work
		 * as that path hits unconditionally and we do not want to
		 * execute this in NMI return paths, for example.
		 */
#endif
rtrap_no_irq_enable:
		andcc			%l1, TSTATE_PRIV, %l3
		bne,pn			%icc, to_kernel
		 nop

		/* We must hold IRQs off and atomically test schedule+signal
		 * state, then hold them off all the way back to userspace.
		 * If we are returning to kernel, none of this matters.  Note
		 * that we are disabling interrupts via PSTATE_IE, not using
		 * %pil.
		 *
		 * If we do not do this, there is a window where we would do
		 * the tests, later the signal/resched event arrives but we do
		 * not process it since we are still in kernel mode.  It would
		 * take until the next local IRQ before the signal/resched
		 * event would be handled.
		 *
		 * This also means that if we have to deal with user
		 * windows, we have to redo all of these sched+signal checks
		 * with IRQs disabled.
		 */
to_user:	wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		wrpr			0, %pil
__handle_preemption_continue:
		ldx			[%g6 + TI_FLAGS], %l0
		sethi			%hi(_TIF_USER_WORK_MASK), %o0
		or			%o0, %lo(_TIF_USER_WORK_MASK), %o0
		andcc			%l0, %o0, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,pt			%xcc, user_nowork
		 andcc			%l1, %o0, %g0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		bne,pn			%xcc, __handle_preemption
		 andcc			%l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
		bne,pn			%xcc, __handle_signal
		 ldub			[%g6 + TI_WSAVED], %o2
		brnz,pn			%o2, __handle_user_windows
		 nop
		sethi			%hi(TSTATE_PEF), %o0
		andcc			%l1, %o0, %g0

		/* This fpdepth clear is necessary for non-syscall rtraps only */
user_nowork:
		bne,pn			%xcc, __handle_userfpu
		 stb			%g0, [%g6 + TI_FPDEPTH]
__handle_userfpu_continue:

rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2

		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
		brz,pt			%l3, 1f
		mov			%g6, %l2

		/* Must do this before thread reg is clobbered below.  */
		LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7

		/* Normal globals are restored, go to trap globals.  */
661:		wrpr			%g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
		nop
		.section		.sun4v_2insn_patch, "ax"
		.word			661b
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		SET_GL(1)
		.previous

		mov			%l2, %g6

		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1

		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2

		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
		wr			%o3, %g0, %y
		wrpr			%l4, 0x0, %pil
		wrpr			%g0, 0x1, %tl
		andn			%l1, TSTATE_SYSCALL, %l1
		wrpr			%l1, %g0, %tstate
		wrpr			%l2, %g0, %tpc
		wrpr			%o2, %g0, %tnpc

		brnz,pn			%l3, kern_rtt
		 mov			PRIMARY_CONTEXT, %l7

661:		ldxa			[%l7 + %l7] ASI_DMMU, %l0
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		ldxa			[%l7 + %l7] ASI_MMU, %l0
		.previous

		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1
		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
		or			%l0, %l1, %l0

661:		stxa			%l0, [%l7] ASI_DMMU
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		stxa			%l0, [%l7] ASI_MMU
		.previous

		sethi			%hi(KERNBASE), %l7
		flush			%l7
		rdpr			%wstate, %l1
		rdpr			%otherwin, %l2
		srl			%l1, 3, %l1

		wrpr			%l2, %g0, %canrestore
		wrpr			%l1, %g0, %wstate
		brnz,pt			%l2, user_rtt_restore
		 wrpr			%g0, %g0, %otherwin

		ldx			[%g6 + TI_FLAGS], %g3
		wr			%g0, ASI_AIUP, %asi
		rdpr			%cwp, %g1
		andcc			%g3, _TIF_32BIT, %g0
		sub			%g1, 1, %g1
		bne,pt			%xcc, user_rtt_fill_32bit
		 wrpr			%g1, %cwp
		ba,a,pt			%xcc, user_rtt_fill_64bit

user_rtt_fill_fixup:
		rdpr	%cwp, %g1
		add	%g1, 1, %g1
		wrpr	%g1, 0x0, %cwp

		rdpr	%wstate, %g2
		sll	%g2, 3, %g2
		wrpr	%g2, 0x0, %wstate

		/* We know %canrestore and %otherwin are both zero.  */

		sethi	%hi(sparc64_kern_pri_context), %g2
		ldx	[%g2 + %lo(sparc64_kern_pri_context)], %g2
		mov	PRIMARY_CONTEXT, %g1

661:		stxa	%g2, [%g1] ASI_DMMU
		.section .sun4v_1insn_patch, "ax"
		.word	661b
		stxa	%g2, [%g1] ASI_MMU
		.previous

		sethi	%hi(KERNBASE), %g1
		flush	%g1

		or	%g4, FAULT_CODE_WINFIXUP, %g4
		stb	%g4, [%g6 + TI_FAULT_CODE]
		stx	%g5, [%g6 + TI_FAULT_ADDR]

		mov	%g6, %l1
		wrpr	%g0, 0x0, %tl

661:		nop
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		SET_GL(0)
		.previous

		wrpr	%g0, RTRAP_PSTATE, %pstate

		mov	%l1, %g6
		ldx	[%g6 + TI_TASK], %g4
		LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
		call	do_sparc64_fault
		 add	%sp, PTREGS_OFF, %o0
		ba,pt	%xcc, rtrap
		 nop

user_rtt_pre_restore:
		add			%g1, 1, %g1
		wrpr			%g1, 0x0, %cwp

user_rtt_restore:
		restore
		rdpr			%canrestore, %g1
		wrpr			%g1, 0x0, %cleanwin
		retry
		nop

kern_rtt:	rdpr			%canrestore, %g1
		brz,pn			%g1, kern_rtt_fill
		 nop
kern_rtt_restore:
		stw			%g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
		restore
		retry

to_kernel:
#ifdef CONFIG_PREEMPT
		ldsw			[%g6 + TI_PRE_COUNT], %l5
		brnz			%l5, kern_fpucheck
		 ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, kern_fpucheck
		 nop
		cmp			%l4, 0
		bne,pn			%xcc, kern_fpucheck
		 sethi			%hi(PREEMPT_ACTIVE), %l6
		stw			%l6, [%g6 + TI_PRE_COUNT]
		call			schedule
		 nop
		ba,pt			%xcc, rtrap
		 stw			%g0, [%g6 + TI_PRE_COUNT]
#endif
kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
		brz,pt			%l5, rt_continue
		 srl			%l5, 1, %o0
		add			%g6, TI_FPSAVED, %l6
		ldub			[%l6 + %o0], %l2
		sub			%l5, 2, %l5

		add			%g6, TI_GSR, %o1
		andcc			%l2, (FPRS_FEF|FPRS_DU), %g0
		be,pt			%icc, 2f
		 and			%l2, FPRS_DL, %l6
		andcc			%l2, FPRS_FEF, %g0
		be,pn			%icc, 5f
		 sll			%o0, 3, %o5
		rd			%fprs, %g1

		wr			%g1, FPRS_FEF, %fprs
		ldx			[%o1 + %o5], %g1
		add			%g6, TI_XFSR, %o1
		sll			%o0, 8, %o2
		add			%g6, TI_FPREGS, %o3
		brz,pn			%l6, 1f
		 add			%g6, TI_FPREGS+0x40, %o4

		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f0
		ldda			[%o4 + %o2] ASI_BLK_P, %f16
		membar			#Sync
1:		andcc			%l2, FPRS_DU, %g0
		be,pn			%icc, 1f
		 wr			%g1, 0, %gsr
		add			%o2, 0x80, %o2
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
1:		membar			#Sync
		ldx			[%o1 + %o5], %fsr
2:		stb			%l5, [%g6 + TI_FPDEPTH]
		ba,pt			%xcc, rt_continue
		 nop
5:		wr			%g0, FPRS_FEF, %fprs
		sll			%o0, 8, %o2

		add			%g6, TI_FPREGS+0x80, %o3
		add			%g6, TI_FPREGS+0xc0, %o4
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
		membar			#Sync
		wr			%g0, FPRS_DU, %fprs
		ba,pt			%xcc, rt_continue
		 stb			%l5, [%g6 + TI_FPDEPTH]
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* rtrap.S: Preparing for return from trap on Sparc V9.
	3	*
	4	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	5	* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
	6	*/
	7
1da177e4 LT	8
	9	#include <asm/asi.h>
	10	#include <asm/pstate.h>
	11	#include <asm/ptrace.h>
	12	#include <asm/spitfire.h>
	13	#include <asm/head.h>
	14	#include <asm/visasm.h>
	15	#include <asm/processor.h>
	16
64f2dde3 DM	17	#define RTRAP_PSTATE (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_IE)
	18	#define RTRAP_PSTATE_IRQOFF (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV)
	19	#define RTRAP_PSTATE_AG_IRQOFF (PSTATE_TSO\|PSTATE_PEF\|PSTATE_PRIV\|PSTATE_AG)
1da177e4	20
1da177e4 LT	21	.text
1da177e4 LT	22	.align 32
1da177e4 LT	23	__handle_preemption:
	24	call schedule
	25	wrpr %g0, RTRAP_PSTATE, %pstate
	26	ba,pt %xcc, __handle_preemption_continue
	27	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	28
	29	__handle_user_windows:
	30	call fault_in_user_windows
	31	wrpr %g0, RTRAP_PSTATE, %pstate
caebf910 AV	32	ba,pt %xcc, __handle_preemption_continue
caebf910 AV	33	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4	34
1da177e4 LT	35	__handle_userfpu:
	36	rd %fprs, %l5
	37	andcc %l5, FPRS_FEF, %g0
	38	sethi %hi(TSTATE_PEF), %o0
	39	be,a,pn %icc, __handle_userfpu_continue
	40	andn %l1, %o0, %l1
	41	ba,a,pt %xcc, __handle_userfpu_continue
	42
	43	__handle_signal:
2d7d5f05	44	mov %l5, %o1
2d7d5f05	45	add %sp, PTREGS_OFF, %o0
7697daaa	46	mov %l0, %o2
1da177e4 LT	47	call do_notify_resume
	48	wrpr %g0, RTRAP_PSTATE, %pstate
	49	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4 LT	50
	51	/* Signal delivery can modify pt_regs tstate, so we must
	52	* reload it.
	53	*/
	54	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	55	sethi %hi(0xf << 20), %l4
	56	and %l1, %l4, %l4
caebf910	57	ba,pt %xcc, __handle_preemption_continue
1da177e4 LT	58	andn %l1, %l4, %l1
1da177e4 LT	59
5565736e DM	60	/* When returning from a NMI (%pil==15) interrupt we want to
	61	* avoid running softirqs, doing IRQ tracing, preempting, etc.
	62	*/
	63	.globl rtrap_nmi
	64	rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	65	sethi %hi(0xf << 20), %l4
	66	and %l1, %l4, %l4
	67	andn %l1, %l4, %l1
	68	srl %l4, 20, %l4
	69	ba,pt %xcc, rtrap_no_irq_enable
	70	wrpr %l4, %pil
	71
1da177e4	72	.align 64
7697daaa	73	.globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
1da177e4	74	rtrap_irq:
1da177e4	75	rtrap:
1da177e4	76	/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
78b7e3d0	77	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
1da177e4 LT	78	rtrap_xcall:
1da177e4 LT	79	sethi %hi(0xf << 20), %l4
1da177e4	80	and %l1, %l4, %l4
10e26723 DM	81	andn %l1, %l4, %l1
	82	srl %l4, 20, %l4
	83	#ifdef CONFIG_TRACE_IRQFLAGS
	84	brnz,pn %l4, rtrap_no_irq_enable
	85	nop
	86	call trace_hardirqs_on
	87	nop
28a1f533 DM	88	/* Do not actually set the %pil here. We will do that
	89	* below after we clear PSTATE_IE in the %pstate register.
	90	* If we re-enable interrupts here, we can recurse down
	91	* the hardirq stack potentially endlessly, causing a
	92	* stack overflow.
	93	*
	94	* It is tempting to put this test and trace_hardirqs_on
	95	* call at the 'rt_continue' label, but that will not work
	96	* as that path hits unconditionally and we do not want to
	97	* execute this in NMI return paths, for example.
	98	*/
10e26723	99	#endif
5565736e	100	rtrap_no_irq_enable:
10e26723	101	andcc %l1, TSTATE_PRIV, %l3
1da177e4	102	bne,pn %icc, to_kernel
10e26723	103	nop
1da177e4 LT	104
	105	/* We must hold IRQs off and atomically test schedule+signal
	106	* state, then hold them off all the way back to userspace.
10e26723 DM	107	* If we are returning to kernel, none of this matters. Note
	108	* that we are disabling interrupts via PSTATE_IE, not using
	109	* %pil.
1da177e4 LT	110	*
	111	* If we do not do this, there is a window where we would do
	112	* the tests, later the signal/resched event arrives but we do
	113	* not process it since we are still in kernel mode. It would
	114	* take until the next local IRQ before the signal/resched
	115	* event would be handled.
	116	*
c7d5a005 DM	117	* This also means that if we have to deal with user
	118	* windows, we have to redo all of these sched+signal checks
	119	* with IRQs disabled.
1da177e4 LT	120	*/
	121	to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	122	wrpr 0, %pil
	123	__handle_preemption_continue:
	124	ldx [%g6 + TI_FLAGS], %l0
	125	sethi %hi(_TIF_USER_WORK_MASK), %o0
	126	or %o0, %lo(_TIF_USER_WORK_MASK), %o0
	127	andcc %l0, %o0, %g0
	128	sethi %hi(TSTATE_PEF), %o0
	129	be,pt %xcc, user_nowork
	130	andcc %l1, %o0, %g0
	131	andcc %l0, _TIF_NEED_RESCHED, %g0
	132	bne,pn %xcc, __handle_preemption
e35a8925	133	andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
1da177e4	134	bne,pn %xcc, __handle_signal
1da177e4 LT	135	ldub [%g6 + TI_WSAVED], %o2
	136	brnz,pn %o2, __handle_user_windows
	137	nop
1da177e4	138	sethi %hi(TSTATE_PEF), %o0
c7d5a005	139	andcc %l1, %o0, %g0
1da177e4 LT	140
	141	/* This fpdepth clear is necessary for non-syscall rtraps only */
	142	user_nowork:
	143	bne,pn %xcc, __handle_userfpu
	144	stb %g0, [%g6 + TI_FPDEPTH]
	145	__handle_userfpu_continue:
	146
	147	rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
	148	ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
	149
	150	ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
	151	ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
	152	ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
56fb4df6	153	brz,pt %l3, 1f
314981ac DM	154	mov %g6, %l2
314981ac DM	155
56fb4df6	156	/* Must do this before thread reg is clobbered below. */
ffe483d5	157	LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
74bf4312 DM	158	1:
74bf4312 DM	159	ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
1da177e4	160	ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
936f482a DM	161
	162	/* Normal globals are restored, go to trap globals. */
	163	661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
af02bec6 DM	164	nop
af02bec6 DM	165	.section .sun4v_2insn_patch, "ax"
936f482a	166	.word 661b
af02bec6	167	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
936f482a DM	168	SET_GL(1)
	169	.previous
	170
314981ac DM	171	mov %l2, %g6
314981ac DM	172
1da177e4 LT	173	ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
	174	ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
	175
	176	ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
	177	ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
	178	ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
	179	ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
	180	ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
	181	ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
	182	ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
	183	ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
	184
	185	ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
	186	wr %o3, %g0, %y
1da177e4 LT	187	wrpr %l4, 0x0, %pil
1da177e4 LT	188	wrpr %g0, 0x1, %tl
28e61036	189	andn %l1, TSTATE_SYSCALL, %l1
1da177e4 LT	190	wrpr %l1, %g0, %tstate
	191	wrpr %l2, %g0, %tpc
	192	wrpr %o2, %g0, %tnpc
	193
	194	brnz,pn %l3, kern_rtt
	195	mov PRIMARY_CONTEXT, %l7
8b11bd12 DM	196
	197	661: ldxa [%l7 + %l7] ASI_DMMU, %l0
	198	.section .sun4v_1insn_patch, "ax"
	199	.word 661b
	200	ldxa [%l7 + %l7] ASI_MMU, %l0
	201	.previous
	202
0835ae0f DM	203	sethi %hi(sparc64_kern_pri_nuc_bits), %l1
0835ae0f DM	204	ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
1da177e4	205	or %l0, %l1, %l0
8b11bd12 DM	206
	207	661: stxa %l0, [%l7] ASI_DMMU
	208	.section .sun4v_1insn_patch, "ax"
	209	.word 661b
	210	stxa %l0, [%l7] ASI_MMU
	211	.previous
	212
4da808c3 DM	213	sethi %hi(KERNBASE), %l7
4da808c3 DM	214	flush %l7
1da177e4 LT	215	rdpr %wstate, %l1
	216	rdpr %otherwin, %l2
	217	srl %l1, 3, %l1
	218
	219	wrpr %l2, %g0, %canrestore
	220	wrpr %l1, %g0, %wstate
314ef685 DM	221	brnz,pt %l2, user_rtt_restore
	222	wrpr %g0, %g0, %otherwin
	223
	224	ldx [%g6 + TI_FLAGS], %g3
	225	wr %g0, ASI_AIUP, %asi
	226	rdpr %cwp, %g1
	227	andcc %g3, _TIF_32BIT, %g0
	228	sub %g1, 1, %g1
	229	bne,pt %xcc, user_rtt_fill_32bit
	230	wrpr %g1, %cwp
	231	ba,a,pt %xcc, user_rtt_fill_64bit
	232
	233	user_rtt_fill_fixup:
	234	rdpr %cwp, %g1
	235	add %g1, 1, %g1
	236	wrpr %g1, 0x0, %cwp
	237
	238	rdpr %wstate, %g2
	239	sll %g2, 3, %g2
	240	wrpr %g2, 0x0, %wstate
	241
	242	/* We know %canrestore and %otherwin are both zero. */
	243
	244	sethi %hi(sparc64_kern_pri_context), %g2
	245	ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2
	246	mov PRIMARY_CONTEXT, %g1
8b11bd12 DM	247
	248	661: stxa %g2, [%g1] ASI_DMMU
	249	.section .sun4v_1insn_patch, "ax"
	250	.word 661b
	251	stxa %g2, [%g1] ASI_MMU
	252	.previous
	253
314ef685 DM	254	sethi %hi(KERNBASE), %g1
	255	flush %g1
	256
	257	or %g4, FAULT_CODE_WINFIXUP, %g4
	258	stb %g4, [%g6 + TI_FAULT_CODE]
	259	stx %g5, [%g6 + TI_FAULT_ADDR]
	260
	261	mov %g6, %l1
	262	wrpr %g0, 0x0, %tl
936f482a DM	263
936f482a DM	264	661: nop
df7d6aec	265	.section .sun4v_1insn_patch, "ax"
936f482a DM	266	.word 661b
	267	SET_GL(0)
	268	.previous
	269
fc504928 DM	270	wrpr %g0, RTRAP_PSTATE, %pstate
fc504928 DM	271
314ef685 DM	272	mov %l1, %g6
	273	ldx [%g6 + TI_TASK], %g4
	274	LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3)
	275	call do_sparc64_fault
	276	add %sp, PTREGS_OFF, %o0
	277	ba,pt %xcc, rtrap
	278	nop
	279
	280	user_rtt_pre_restore:
	281	add %g1, 1, %g1
	282	wrpr %g1, 0x0, %cwp
	283
	284	user_rtt_restore:
1da177e4 LT	285	restore
	286	rdpr %canrestore, %g1
	287	wrpr %g1, 0x0, %cleanwin
	288	retry
	289	nop
	290
314ef685 DM	291	kern_rtt: rdpr %canrestore, %g1
	292	brz,pn %g1, kern_rtt_fill
	293	nop
	294	kern_rtt_restore:
ada44a04	295	stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
314ef685	296	restore
1da177e4	297	retry
314ef685	298
1da177e4 LT	299	to_kernel:
	300	#ifdef CONFIG_PREEMPT
	301	ldsw [%g6 + TI_PRE_COUNT], %l5
	302	brnz %l5, kern_fpucheck
	303	ldx [%g6 + TI_FLAGS], %l5
	304	andcc %l5, _TIF_NEED_RESCHED, %g0
	305	be,pt %xcc, kern_fpucheck
10e26723 DM	306	nop
10e26723 DM	307	cmp %l4, 0
1da177e4 LT	308	bne,pn %xcc, kern_fpucheck
	309	sethi %hi(PREEMPT_ACTIVE), %l6
	310	stw %l6, [%g6 + TI_PRE_COUNT]
	311	call schedule
	312	nop
	313	ba,pt %xcc, rtrap
	314	stw %g0, [%g6 + TI_PRE_COUNT]
	315	#endif
	316	kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
	317	brz,pt %l5, rt_continue
	318	srl %l5, 1, %o0
	319	add %g6, TI_FPSAVED, %l6
	320	ldub [%l6 + %o0], %l2
	321	sub %l5, 2, %l5
	322
	323	add %g6, TI_GSR, %o1
	324	andcc %l2, (FPRS_FEF\|FPRS_DU), %g0
	325	be,pt %icc, 2f
	326	and %l2, FPRS_DL, %l6
	327	andcc %l2, FPRS_FEF, %g0
	328	be,pn %icc, 5f
	329	sll %o0, 3, %o5
	330	rd %fprs, %g1
	331
	332	wr %g1, FPRS_FEF, %fprs
	333	ldx [%o1 + %o5], %g1
	334	add %g6, TI_XFSR, %o1
1da177e4 LT	335	sll %o0, 8, %o2
	336	add %g6, TI_FPREGS, %o3
	337	brz,pn %l6, 1f
	338	add %g6, TI_FPREGS+0x40, %o4
	339
ba639933	340	membar #Sync
1da177e4 LT	341	ldda [%o3 + %o2] ASI_BLK_P, %f0
1da177e4 LT	342	ldda [%o4 + %o2] ASI_BLK_P, %f16
ba639933	343	membar #Sync
1da177e4 LT	344	1: andcc %l2, FPRS_DU, %g0
	345	be,pn %icc, 1f
	346	wr %g1, 0, %gsr
	347	add %o2, 0x80, %o2
ba639933	348	membar #Sync
1da177e4 LT	349	ldda [%o3 + %o2] ASI_BLK_P, %f32
1da177e4 LT	350	ldda [%o4 + %o2] ASI_BLK_P, %f48
1da177e4 LT	351	1: membar #Sync
	352	ldx [%o1 + %o5], %fsr
	353	2: stb %l5, [%g6 + TI_FPDEPTH]
	354	ba,pt %xcc, rt_continue
	355	nop
	356	5: wr %g0, FPRS_FEF, %fprs
1da177e4 LT	357	sll %o0, 8, %o2
	358
	359	add %g6, TI_FPREGS+0x80, %o3
	360	add %g6, TI_FPREGS+0xc0, %o4
ba639933	361	membar #Sync
1da177e4 LT	362	ldda [%o3 + %o2] ASI_BLK_P, %f32
	363	ldda [%o4 + %o2] ASI_BLK_P, %f48
	364	membar #Sync
	365	wr %g0, FPRS_DU, %fprs
	366	ba,pt %xcc, rt_continue
	367	stb %l5, [%g6 + TI_FPDEPTH]