[mirror_ubuntu-bionic-kernel.git] / arch / sparc / kernel / rtrap_64.S

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * rtrap.S: Preparing for return from trap on Sparc V9.
 *
 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
 */


#include <asm/asi.h>
#include <asm/pstate.h>
#include <asm/ptrace.h>
#include <asm/spitfire.h>
#include <asm/head.h>
#include <asm/visasm.h>
#include <asm/processor.h>

#ifdef CONFIG_CONTEXT_TRACKING
# define SCHEDULE_USER schedule_user
#else
# define SCHEDULE_USER schedule
#endif

		.text
		.align			32
__handle_preemption:
		call			SCHEDULE_USER
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_user_windows:
		call			fault_in_user_windows
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		ba,pt			%xcc, __handle_preemption_continue
		 wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

__handle_userfpu:
		rd			%fprs, %l5
		andcc			%l5, FPRS_FEF, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,a,pn			%icc, __handle_userfpu_continue
		 andn			%l1, %o0, %l1
		ba,a,pt			%xcc, __handle_userfpu_continue

__handle_signal:
		mov			%l5, %o1
		add			%sp, PTREGS_OFF, %o0
		mov			%l0, %o2
		call			do_notify_resume
		 wrpr			%g0, RTRAP_PSTATE, %pstate
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate

		/* Signal delivery can modify pt_regs tstate, so we must
		 * reload it.
		 */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		ba,pt			%xcc, __handle_preemption_continue
		 andn			%l1, %l4, %l1

		/* When returning from a NMI (%pil==15) interrupt we want to
		 * avoid running softirqs, doing IRQ tracing, preempting, etc.
		 */
		.globl			rtrap_nmi
rtrap_nmi:	ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
		ba,pt			%xcc, rtrap_no_irq_enable
		nop
		/* Do not actually set the %pil here.  We will do that
		 * below after we clear PSTATE_IE in the %pstate register.
		 * If we re-enable interrupts here, we can recurse down
		 * the hardirq stack potentially endlessly, causing a
		 * stack overflow.
		 */

		.align			64
		.globl			rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
rtrap_irq:
rtrap:
		/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
		ldx			[%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
rtrap_xcall:
		sethi			%hi(0xf << 20), %l4
		and			%l1, %l4, %l4
		andn			%l1, %l4, %l1
		srl			%l4, 20, %l4
#ifdef CONFIG_TRACE_IRQFLAGS
		brnz,pn			%l4, rtrap_no_irq_enable
		 nop
		call			trace_hardirqs_on
		 nop
		/* Do not actually set the %pil here.  We will do that
		 * below after we clear PSTATE_IE in the %pstate register.
		 * If we re-enable interrupts here, we can recurse down
		 * the hardirq stack potentially endlessly, causing a
		 * stack overflow.
		 *
		 * It is tempting to put this test and trace_hardirqs_on
		 * call at the 'rt_continue' label, but that will not work
		 * as that path hits unconditionally and we do not want to
		 * execute this in NMI return paths, for example.
		 */
#endif
rtrap_no_irq_enable:
		andcc			%l1, TSTATE_PRIV, %l3
		bne,pn			%icc, to_kernel
		 nop

		/* We must hold IRQs off and atomically test schedule+signal
		 * state, then hold them off all the way back to userspace.
		 * If we are returning to kernel, none of this matters.  Note
		 * that we are disabling interrupts via PSTATE_IE, not using
		 * %pil.
		 *
		 * If we do not do this, there is a window where we would do
		 * the tests, later the signal/resched event arrives but we do
		 * not process it since we are still in kernel mode.  It would
		 * take until the next local IRQ before the signal/resched
		 * event would be handled.
		 *
		 * This also means that if we have to deal with user
		 * windows, we have to redo all of these sched+signal checks
		 * with IRQs disabled.
		 */
to_user:	wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		wrpr			0, %pil
__handle_preemption_continue:
		ldx			[%g6 + TI_FLAGS], %l0
		sethi			%hi(_TIF_USER_WORK_MASK), %o0
		or			%o0, %lo(_TIF_USER_WORK_MASK), %o0
		andcc			%l0, %o0, %g0
		sethi			%hi(TSTATE_PEF), %o0
		be,pt			%xcc, user_nowork
		 andcc			%l1, %o0, %g0
		andcc			%l0, _TIF_NEED_RESCHED, %g0
		bne,pn			%xcc, __handle_preemption
		 andcc			%l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
		bne,pn			%xcc, __handle_signal
		 ldub			[%g6 + TI_WSAVED], %o2
		brnz,pn			%o2, __handle_user_windows
		 nop
		sethi			%hi(TSTATE_PEF), %o0
		andcc			%l1, %o0, %g0

		/* This fpdepth clear is necessary for non-syscall rtraps only */
user_nowork:
		bne,pn			%xcc, __handle_userfpu
		 stb			%g0, [%g6 + TI_FPDEPTH]
__handle_userfpu_continue:

rt_continue:	ldx			[%sp + PTREGS_OFF + PT_V9_G1], %g1
		ldx			[%sp + PTREGS_OFF + PT_V9_G2], %g2

		ldx			[%sp + PTREGS_OFF + PT_V9_G3], %g3
		ldx			[%sp + PTREGS_OFF + PT_V9_G4], %g4
		ldx			[%sp + PTREGS_OFF + PT_V9_G5], %g5
		brz,pt			%l3, 1f
		mov			%g6, %l2

		/* Must do this before thread reg is clobbered below.  */
		LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
1:
		ldx			[%sp + PTREGS_OFF + PT_V9_G6], %g6
		ldx			[%sp + PTREGS_OFF + PT_V9_G7], %g7

		/* Normal globals are restored, go to trap globals.  */
661:		wrpr			%g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
		nop
		.section		.sun4v_2insn_patch, "ax"
		.word			661b
		wrpr			%g0, RTRAP_PSTATE_IRQOFF, %pstate
		SET_GL(1)
		.previous

		mov			%l2, %g6

		ldx			[%sp + PTREGS_OFF + PT_V9_I0], %i0
		ldx			[%sp + PTREGS_OFF + PT_V9_I1], %i1

		ldx			[%sp + PTREGS_OFF + PT_V9_I2], %i2
		ldx			[%sp + PTREGS_OFF + PT_V9_I3], %i3
		ldx			[%sp + PTREGS_OFF + PT_V9_I4], %i4
		ldx			[%sp + PTREGS_OFF + PT_V9_I5], %i5
		ldx			[%sp + PTREGS_OFF + PT_V9_I6], %i6
		ldx			[%sp + PTREGS_OFF + PT_V9_I7], %i7
		ldx			[%sp + PTREGS_OFF + PT_V9_TPC], %l2
		ldx			[%sp + PTREGS_OFF + PT_V9_TNPC], %o2

		ld			[%sp + PTREGS_OFF + PT_V9_Y], %o3
		wr			%o3, %g0, %y
		wrpr			%l4, 0x0, %pil
		wrpr			%g0, 0x1, %tl
		andn			%l1, TSTATE_SYSCALL, %l1
		wrpr			%l1, %g0, %tstate
		wrpr			%l2, %g0, %tpc
		wrpr			%o2, %g0, %tnpc

		brnz,pn			%l3, kern_rtt
		 mov			PRIMARY_CONTEXT, %l7

661:		ldxa			[%l7 + %l7] ASI_DMMU, %l0
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		ldxa			[%l7 + %l7] ASI_MMU, %l0
		.previous

		sethi			%hi(sparc64_kern_pri_nuc_bits), %l1
		ldx			[%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
		or			%l0, %l1, %l0

661:		stxa			%l0, [%l7] ASI_DMMU
		.section		.sun4v_1insn_patch, "ax"
		.word			661b
		stxa			%l0, [%l7] ASI_MMU
		.previous

		sethi			%hi(KERNBASE), %l7
		flush			%l7
		rdpr			%wstate, %l1
		rdpr			%otherwin, %l2
		srl			%l1, 3, %l1

661:		wrpr			%l2, %g0, %canrestore
		.section		.fast_win_ctrl_1insn_patch, "ax"
		.word			661b
		.word			0x89880000	! normalw
		.previous

		wrpr			%l1, %g0, %wstate
		brnz,pt			%l2, user_rtt_restore
661:		 wrpr			%g0, %g0, %otherwin
		.section		.fast_win_ctrl_1insn_patch, "ax"
		.word			661b
		 nop
		.previous

		ldx			[%g6 + TI_FLAGS], %g3
		wr			%g0, ASI_AIUP, %asi
		rdpr			%cwp, %g1
		andcc			%g3, _TIF_32BIT, %g0
		sub			%g1, 1, %g1
		bne,pt			%xcc, user_rtt_fill_32bit
		 wrpr			%g1, %cwp
		ba,a,pt			%xcc, user_rtt_fill_64bit
		 nop

user_rtt_fill_fixup_dax:
		ba,pt	%xcc, user_rtt_fill_fixup_common
		 mov	1, %g3

user_rtt_fill_fixup_mna:
		ba,pt	%xcc, user_rtt_fill_fixup_common
		 mov	2, %g3

user_rtt_fill_fixup:
		ba,pt	%xcc, user_rtt_fill_fixup_common
		 clr	%g3

user_rtt_pre_restore:
		add			%g1, 1, %g1
		wrpr			%g1, 0x0, %cwp

user_rtt_restore:
		restore
		rdpr			%canrestore, %g1
		wrpr			%g1, 0x0, %cleanwin
		retry
		nop

kern_rtt:	rdpr			%canrestore, %g1
		brz,pn			%g1, kern_rtt_fill
		 nop
kern_rtt_restore:
		stw			%g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
		restore
		retry

to_kernel:
#ifdef CONFIG_PREEMPT
		ldsw			[%g6 + TI_PRE_COUNT], %l5
		brnz			%l5, kern_fpucheck
		 ldx			[%g6 + TI_FLAGS], %l5
		andcc			%l5, _TIF_NEED_RESCHED, %g0
		be,pt			%xcc, kern_fpucheck
		 nop
		cmp			%l4, 0
		bne,pn			%xcc, kern_fpucheck
		 nop
		call			preempt_schedule_irq
		 nop
		ba,pt			%xcc, rtrap
#endif
kern_fpucheck:	ldub			[%g6 + TI_FPDEPTH], %l5
		brz,pt			%l5, rt_continue
		 srl			%l5, 1, %o0
		add			%g6, TI_FPSAVED, %l6
		ldub			[%l6 + %o0], %l2
		sub			%l5, 2, %l5

		add			%g6, TI_GSR, %o1
		andcc			%l2, (FPRS_FEF|FPRS_DU), %g0
		be,pt			%icc, 2f
		 and			%l2, FPRS_DL, %l6
		andcc			%l2, FPRS_FEF, %g0
		be,pn			%icc, 5f
		 sll			%o0, 3, %o5
		rd			%fprs, %g1

		wr			%g1, FPRS_FEF, %fprs
		ldx			[%o1 + %o5], %g1
		add			%g6, TI_XFSR, %o1
		sll			%o0, 8, %o2
		add			%g6, TI_FPREGS, %o3
		brz,pn			%l6, 1f
		 add			%g6, TI_FPREGS+0x40, %o4

		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f0
		ldda			[%o4 + %o2] ASI_BLK_P, %f16
		membar			#Sync
1:		andcc			%l2, FPRS_DU, %g0
		be,pn			%icc, 1f
		 wr			%g1, 0, %gsr
		add			%o2, 0x80, %o2
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
1:		membar			#Sync
		ldx			[%o1 + %o5], %fsr
2:		stb			%l5, [%g6 + TI_FPDEPTH]
		ba,pt			%xcc, rt_continue
		 nop
5:		wr			%g0, FPRS_FEF, %fprs
		sll			%o0, 8, %o2

		add			%g6, TI_FPREGS+0x80, %o3
		add			%g6, TI_FPREGS+0xc0, %o4
		membar			#Sync
		ldda			[%o3 + %o2] ASI_BLK_P, %f32
		ldda			[%o4 + %o2] ASI_BLK_P, %f48
		membar			#Sync
		wr			%g0, FPRS_DU, %fprs
		ba,pt			%xcc, rt_continue
		 stb			%l5, [%g6 + TI_FPDEPTH]
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
b00dc837	2	/*
1da177e4 LT	3	* rtrap.S: Preparing for return from trap on Sparc V9.
	4	*
	5	* Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	6	* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
	7	*/
	8
1da177e4 LT	9
	10	#include <asm/asi.h>
	11	#include <asm/pstate.h>
	12	#include <asm/ptrace.h>
	13	#include <asm/spitfire.h>
	14	#include <asm/head.h>
	15	#include <asm/visasm.h>
	16	#include <asm/processor.h>
	17
812cb83a KT	18	#ifdef CONFIG_CONTEXT_TRACKING
	19	# define SCHEDULE_USER schedule_user
	20	#else
	21	# define SCHEDULE_USER schedule
	22	#endif
	23
1da177e4 LT	24	.text
1da177e4 LT	25	.align 32
1da177e4	26	__handle_preemption:
812cb83a	27	call SCHEDULE_USER
1da177e4 LT	28	wrpr %g0, RTRAP_PSTATE, %pstate
	29	ba,pt %xcc, __handle_preemption_continue
	30	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	31
	32	__handle_user_windows:
	33	call fault_in_user_windows
	34	wrpr %g0, RTRAP_PSTATE, %pstate
caebf910 AV	35	ba,pt %xcc, __handle_preemption_continue
caebf910 AV	36	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4	37
1da177e4 LT	38	__handle_userfpu:
	39	rd %fprs, %l5
	40	andcc %l5, FPRS_FEF, %g0
	41	sethi %hi(TSTATE_PEF), %o0
	42	be,a,pn %icc, __handle_userfpu_continue
	43	andn %l1, %o0, %l1
	44	ba,a,pt %xcc, __handle_userfpu_continue
	45
	46	__handle_signal:
2d7d5f05	47	mov %l5, %o1
2d7d5f05	48	add %sp, PTREGS_OFF, %o0
7697daaa	49	mov %l0, %o2
1da177e4 LT	50	call do_notify_resume
	51	wrpr %g0, RTRAP_PSTATE, %pstate
	52	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
1da177e4 LT	53
	54	/* Signal delivery can modify pt_regs tstate, so we must
	55	* reload it.
	56	*/
	57	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	58	sethi %hi(0xf << 20), %l4
	59	and %l1, %l4, %l4
caebf910	60	ba,pt %xcc, __handle_preemption_continue
1da177e4 LT	61	andn %l1, %l4, %l1
1da177e4 LT	62
5565736e DM	63	/* When returning from a NMI (%pil==15) interrupt we want to
	64	* avoid running softirqs, doing IRQ tracing, preempting, etc.
	65	*/
	66	.globl rtrap_nmi
	67	rtrap_nmi: ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
	68	sethi %hi(0xf << 20), %l4
	69	and %l1, %l4, %l4
	70	andn %l1, %l4, %l1
	71	srl %l4, 20, %l4
	72	ba,pt %xcc, rtrap_no_irq_enable
1ca04a4c RG	73	nop
	74	/* Do not actually set the %pil here. We will do that
	75	* below after we clear PSTATE_IE in the %pstate register.
	76	* If we re-enable interrupts here, we can recurse down
	77	* the hardirq stack potentially endlessly, causing a
	78	* stack overflow.
	79	*/
5565736e	80
1da177e4	81	.align 64
7697daaa	82	.globl rtrap_irq, rtrap, irqsz_patchme, rtrap_xcall
1da177e4	83	rtrap_irq:
1da177e4	84	rtrap:
1da177e4	85	/* mm/ultra.S:xcall_report_regs KNOWS about this load. */
78b7e3d0	86	ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
1da177e4 LT	87	rtrap_xcall:
1da177e4 LT	88	sethi %hi(0xf << 20), %l4
1da177e4	89	and %l1, %l4, %l4
10e26723 DM	90	andn %l1, %l4, %l1
	91	srl %l4, 20, %l4
	92	#ifdef CONFIG_TRACE_IRQFLAGS
	93	brnz,pn %l4, rtrap_no_irq_enable
	94	nop
	95	call trace_hardirqs_on
	96	nop
28a1f533 DM	97	/* Do not actually set the %pil here. We will do that
	98	* below after we clear PSTATE_IE in the %pstate register.
	99	* If we re-enable interrupts here, we can recurse down
	100	* the hardirq stack potentially endlessly, causing a
	101	* stack overflow.
	102	*
	103	* It is tempting to put this test and trace_hardirqs_on
	104	* call at the 'rt_continue' label, but that will not work
	105	* as that path hits unconditionally and we do not want to
	106	* execute this in NMI return paths, for example.
	107	*/
10e26723	108	#endif
5565736e	109	rtrap_no_irq_enable:
10e26723	110	andcc %l1, TSTATE_PRIV, %l3
1da177e4	111	bne,pn %icc, to_kernel
10e26723	112	nop
1da177e4 LT	113
	114	/* We must hold IRQs off and atomically test schedule+signal
	115	* state, then hold them off all the way back to userspace.
10e26723 DM	116	* If we are returning to kernel, none of this matters. Note
	117	* that we are disabling interrupts via PSTATE_IE, not using
	118	* %pil.
1da177e4 LT	119	*
	120	* If we do not do this, there is a window where we would do
	121	* the tests, later the signal/resched event arrives but we do
	122	* not process it since we are still in kernel mode. It would
	123	* take until the next local IRQ before the signal/resched
	124	* event would be handled.
	125	*
c7d5a005 DM	126	* This also means that if we have to deal with user
	127	* windows, we have to redo all of these sched+signal checks
	128	* with IRQs disabled.
1da177e4 LT	129	*/
	130	to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
	131	wrpr 0, %pil
	132	__handle_preemption_continue:
	133	ldx [%g6 + TI_FLAGS], %l0
	134	sethi %hi(_TIF_USER_WORK_MASK), %o0
	135	or %o0, %lo(_TIF_USER_WORK_MASK), %o0
	136	andcc %l0, %o0, %g0
	137	sethi %hi(TSTATE_PEF), %o0
	138	be,pt %xcc, user_nowork
	139	andcc %l1, %o0, %g0
	140	andcc %l0, _TIF_NEED_RESCHED, %g0
	141	bne,pn %xcc, __handle_preemption
e35a8925	142	andcc %l0, _TIF_DO_NOTIFY_RESUME_MASK, %g0
1da177e4	143	bne,pn %xcc, __handle_signal
1da177e4 LT	144	ldub [%g6 + TI_WSAVED], %o2
	145	brnz,pn %o2, __handle_user_windows
	146	nop
1da177e4	147	sethi %hi(TSTATE_PEF), %o0
c7d5a005	148	andcc %l1, %o0, %g0
1da177e4 LT	149
	150	/* This fpdepth clear is necessary for non-syscall rtraps only */
	151	user_nowork:
	152	bne,pn %xcc, __handle_userfpu
	153	stb %g0, [%g6 + TI_FPDEPTH]
	154	__handle_userfpu_continue:
	155
	156	rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1
	157	ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2
	158
	159	ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3
	160	ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4
	161	ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5
56fb4df6	162	brz,pt %l3, 1f
314981ac DM	163	mov %g6, %l2
314981ac DM	164
56fb4df6	165	/* Must do this before thread reg is clobbered below. */
ffe483d5	166	LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2)
74bf4312 DM	167	1:
74bf4312 DM	168	ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6
1da177e4	169	ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7
936f482a DM	170
	171	/* Normal globals are restored, go to trap globals. */
	172	661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate
af02bec6 DM	173	nop
af02bec6 DM	174	.section .sun4v_2insn_patch, "ax"
936f482a	175	.word 661b
af02bec6	176	wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate
936f482a DM	177	SET_GL(1)
	178	.previous
	179
314981ac DM	180	mov %l2, %g6
314981ac DM	181
1da177e4 LT	182	ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0
	183	ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1
	184
	185	ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2
	186	ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3
	187	ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4
	188	ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5
	189	ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6
	190	ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7
	191	ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2
	192	ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2
	193
	194	ld [%sp + PTREGS_OFF + PT_V9_Y], %o3
	195	wr %o3, %g0, %y
1da177e4 LT	196	wrpr %l4, 0x0, %pil
1da177e4 LT	197	wrpr %g0, 0x1, %tl
28e61036	198	andn %l1, TSTATE_SYSCALL, %l1
1da177e4 LT	199	wrpr %l1, %g0, %tstate
	200	wrpr %l2, %g0, %tpc
	201	wrpr %o2, %g0, %tnpc
	202
	203	brnz,pn %l3, kern_rtt
	204	mov PRIMARY_CONTEXT, %l7
8b11bd12 DM	205
	206	661: ldxa [%l7 + %l7] ASI_DMMU, %l0
	207	.section .sun4v_1insn_patch, "ax"
	208	.word 661b
	209	ldxa [%l7 + %l7] ASI_MMU, %l0
	210	.previous
	211
0835ae0f DM	212	sethi %hi(sparc64_kern_pri_nuc_bits), %l1
0835ae0f DM	213	ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1
1da177e4	214	or %l0, %l1, %l0
8b11bd12 DM	215
	216	661: stxa %l0, [%l7] ASI_DMMU
	217	.section .sun4v_1insn_patch, "ax"
	218	.word 661b
	219	stxa %l0, [%l7] ASI_MMU
	220	.previous
	221
4da808c3 DM	222	sethi %hi(KERNBASE), %l7
4da808c3 DM	223	flush %l7
1da177e4 LT	224	rdpr %wstate, %l1
	225	rdpr %otherwin, %l2
	226	srl %l1, 3, %l1
	227
a7159a87 AY	228	661: wrpr %l2, %g0, %canrestore
	229	.section .fast_win_ctrl_1insn_patch, "ax"
	230	.word 661b
	231	.word 0x89880000 ! normalw
	232	.previous
	233
1da177e4	234	wrpr %l1, %g0, %wstate
314ef685	235	brnz,pt %l2, user_rtt_restore
a7159a87 AY	236	661: wrpr %g0, %g0, %otherwin
	237	.section .fast_win_ctrl_1insn_patch, "ax"
	238	.word 661b
	239	nop
	240	.previous
314ef685 DM	241
	242	ldx [%g6 + TI_FLAGS], %g3
	243	wr %g0, ASI_AIUP, %asi
	244	rdpr %cwp, %g1
	245	andcc %g3, _TIF_32BIT, %g0
	246	sub %g1, 1, %g1
	247	bne,pt %xcc, user_rtt_fill_32bit
	248	wrpr %g1, %cwp
	249	ba,a,pt %xcc, user_rtt_fill_64bit
0ae2d26f	250	nop
314ef685	251
7cafc0b8 DM	252	user_rtt_fill_fixup_dax:
	253	ba,pt %xcc, user_rtt_fill_fixup_common
	254	mov 1, %g3
314ef685	255
7cafc0b8 DM	256	user_rtt_fill_fixup_mna:
	257	ba,pt %xcc, user_rtt_fill_fixup_common
	258	mov 2, %g3
314ef685	259
7cafc0b8 DM	260	user_rtt_fill_fixup:
	261	ba,pt %xcc, user_rtt_fill_fixup_common
	262	clr %g3
314ef685 DM	263
	264	user_rtt_pre_restore:
	265	add %g1, 1, %g1
	266	wrpr %g1, 0x0, %cwp
	267
	268	user_rtt_restore:
1da177e4 LT	269	restore
	270	rdpr %canrestore, %g1
	271	wrpr %g1, 0x0, %cleanwin
	272	retry
	273	nop
	274
314ef685 DM	275	kern_rtt: rdpr %canrestore, %g1
	276	brz,pn %g1, kern_rtt_fill
	277	nop
	278	kern_rtt_restore:
ada44a04	279	stw %g0, [%sp + PTREGS_OFF + PT_V9_MAGIC]
314ef685	280	restore
1da177e4	281	retry
314ef685	282
1da177e4 LT	283	to_kernel:
	284	#ifdef CONFIG_PREEMPT
	285	ldsw [%g6 + TI_PRE_COUNT], %l5
	286	brnz %l5, kern_fpucheck
	287	ldx [%g6 + TI_FLAGS], %l5
	288	andcc %l5, _TIF_NEED_RESCHED, %g0
	289	be,pt %xcc, kern_fpucheck
10e26723 DM	290	nop
10e26723 DM	291	cmp %l4, 0
1da177e4	292	bne,pn %xcc, kern_fpucheck
9385d949 TG	293	nop
9385d949 TG	294	call preempt_schedule_irq
1da177e4 LT	295	nop
1da177e4 LT	296	ba,pt %xcc, rtrap
1da177e4 LT	297	#endif
	298	kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5
	299	brz,pt %l5, rt_continue
	300	srl %l5, 1, %o0
	301	add %g6, TI_FPSAVED, %l6
	302	ldub [%l6 + %o0], %l2
	303	sub %l5, 2, %l5
	304
	305	add %g6, TI_GSR, %o1
	306	andcc %l2, (FPRS_FEF\|FPRS_DU), %g0
	307	be,pt %icc, 2f
	308	and %l2, FPRS_DL, %l6
	309	andcc %l2, FPRS_FEF, %g0
	310	be,pn %icc, 5f
	311	sll %o0, 3, %o5
	312	rd %fprs, %g1
	313
	314	wr %g1, FPRS_FEF, %fprs
	315	ldx [%o1 + %o5], %g1
	316	add %g6, TI_XFSR, %o1
1da177e4 LT	317	sll %o0, 8, %o2
	318	add %g6, TI_FPREGS, %o3
	319	brz,pn %l6, 1f
	320	add %g6, TI_FPREGS+0x40, %o4
	321
ba639933	322	membar #Sync
1da177e4 LT	323	ldda [%o3 + %o2] ASI_BLK_P, %f0
1da177e4 LT	324	ldda [%o4 + %o2] ASI_BLK_P, %f16
ba639933	325	membar #Sync
1da177e4 LT	326	1: andcc %l2, FPRS_DU, %g0
	327	be,pn %icc, 1f
	328	wr %g1, 0, %gsr
	329	add %o2, 0x80, %o2
ba639933	330	membar #Sync
1da177e4 LT	331	ldda [%o3 + %o2] ASI_BLK_P, %f32
1da177e4 LT	332	ldda [%o4 + %o2] ASI_BLK_P, %f48
1da177e4 LT	333	1: membar #Sync
	334	ldx [%o1 + %o5], %fsr
	335	2: stb %l5, [%g6 + TI_FPDEPTH]
	336	ba,pt %xcc, rt_continue
	337	nop
	338	5: wr %g0, FPRS_FEF, %fprs
1da177e4 LT	339	sll %o0, 8, %o2
	340
	341	add %g6, TI_FPREGS+0x80, %o3
	342	add %g6, TI_FPREGS+0xc0, %o4
ba639933	343	membar #Sync
1da177e4 LT	344	ldda [%o3 + %o2] ASI_BLK_P, %f32
	345	ldda [%o4 + %o2] ASI_BLK_P, %f48
	346	membar #Sync
	347	wr %g0, FPRS_DU, %fprs
	348	ba,pt %xcc, rt_continue
	349	stb %l5, [%g6 + TI_FPDEPTH]