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Commit | Line | Data |
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b00dc837 | 1 | /* |
1da177e4 LT |
2 | * linux/arch/sparc64/kernel/setup.c |
3 | * | |
4 | * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
8 | #include <linux/errno.h> | |
9 | #include <linux/sched.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/mm.h> | |
12 | #include <linux/stddef.h> | |
13 | #include <linux/unistd.h> | |
14 | #include <linux/ptrace.h> | |
1da177e4 LT |
15 | #include <asm/smp.h> |
16 | #include <linux/user.h> | |
894673ee | 17 | #include <linux/screen_info.h> |
1da177e4 | 18 | #include <linux/delay.h> |
1da177e4 LT |
19 | #include <linux/fs.h> |
20 | #include <linux/seq_file.h> | |
21 | #include <linux/syscalls.h> | |
22 | #include <linux/kdev_t.h> | |
23 | #include <linux/major.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/inet.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/initrd.h> | |
ac85fe8b | 32 | #include <linux/module.h> |
1da177e4 | 33 | |
1da177e4 LT |
34 | #include <asm/system.h> |
35 | #include <asm/io.h> | |
36 | #include <asm/processor.h> | |
37 | #include <asm/oplib.h> | |
38 | #include <asm/page.h> | |
39 | #include <asm/pgtable.h> | |
40 | #include <asm/idprom.h> | |
41 | #include <asm/head.h> | |
42 | #include <asm/starfire.h> | |
43 | #include <asm/mmu_context.h> | |
44 | #include <asm/timer.h> | |
45 | #include <asm/sections.h> | |
46 | #include <asm/setup.h> | |
47 | #include <asm/mmu.h> | |
5cbc3073 | 48 | #include <asm/ns87303.h> |
c57ec52f | 49 | #include <asm/btext.h> |
ac85fe8b DM |
50 | #include <asm/elf.h> |
51 | #include <asm/mdesc.h> | |
1da177e4 LT |
52 | |
53 | #ifdef CONFIG_IP_PNP | |
54 | #include <net/ipconfig.h> | |
55 | #endif | |
56 | ||
3d5ae6b6 | 57 | #include "entry.h" |
53ae3419 | 58 | #include "kernel.h" |
3d5ae6b6 | 59 | |
5cbc3073 DM |
60 | /* Used to synchronize accesses to NatSemi SUPER I/O chip configure |
61 | * operations in asm/ns87303.h | |
62 | */ | |
63 | DEFINE_SPINLOCK(ns87303_lock); | |
917c3660 | 64 | EXPORT_SYMBOL(ns87303_lock); |
5cbc3073 | 65 | |
1da177e4 LT |
66 | struct screen_info screen_info = { |
67 | 0, 0, /* orig-x, orig-y */ | |
68 | 0, /* unused */ | |
69 | 0, /* orig-video-page */ | |
70 | 0, /* orig-video-mode */ | |
71 | 128, /* orig-video-cols */ | |
72 | 0, 0, 0, /* unused, ega_bx, unused */ | |
73 | 54, /* orig-video-lines */ | |
74 | 0, /* orig-video-isVGA */ | |
75 | 16 /* orig-video-points */ | |
76 | }; | |
77 | ||
1da177e4 LT |
78 | static void |
79 | prom_console_write(struct console *con, const char *s, unsigned n) | |
80 | { | |
81 | prom_write(s, n); | |
82 | } | |
83 | ||
1da177e4 LT |
84 | /* Exported for mm/init.c:paging_init. */ |
85 | unsigned long cmdline_memory_size = 0; | |
86 | ||
3c62a2d3 DM |
87 | static struct console prom_early_console = { |
88 | .name = "earlyprom", | |
1da177e4 | 89 | .write = prom_console_write, |
db9a7fb1 | 90 | .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME, |
1da177e4 LT |
91 | .index = -1, |
92 | }; | |
93 | ||
1da177e4 LT |
94 | /* |
95 | * Process kernel command line switches that are specific to the | |
96 | * SPARC or that require special low-level processing. | |
97 | */ | |
98 | static void __init process_switch(char c) | |
99 | { | |
100 | switch (c) { | |
101 | case 'd': | |
1da177e4 | 102 | case 's': |
1da177e4 LT |
103 | break; |
104 | case 'h': | |
105 | prom_printf("boot_flags_init: Halt!\n"); | |
106 | prom_halt(); | |
107 | break; | |
108 | case 'p': | |
3c62a2d3 | 109 | /* Just ignore, this behavior is now the default. */ |
1da177e4 | 110 | break; |
816242da DM |
111 | case 'P': |
112 | /* Force UltraSPARC-III P-Cache on. */ | |
113 | if (tlb_type != cheetah) { | |
114 | printk("BOOT: Ignoring P-Cache force option.\n"); | |
115 | break; | |
116 | } | |
117 | cheetah_pcache_forced_on = 1; | |
118 | add_taint(TAINT_MACHINE_CHECK); | |
119 | cheetah_enable_pcache(); | |
120 | break; | |
121 | ||
1da177e4 LT |
122 | default: |
123 | printk("Unknown boot switch (-%c)\n", c); | |
124 | break; | |
125 | } | |
126 | } | |
127 | ||
1da177e4 LT |
128 | static void __init boot_flags_init(char *commands) |
129 | { | |
130 | while (*commands) { | |
131 | /* Move to the start of the next "argument". */ | |
132 | while (*commands && *commands == ' ') | |
133 | commands++; | |
134 | ||
135 | /* Process any command switches, otherwise skip it. */ | |
136 | if (*commands == '\0') | |
137 | break; | |
138 | if (*commands == '-') { | |
139 | commands++; | |
140 | while (*commands && *commands != ' ') | |
141 | process_switch(*commands++); | |
142 | continue; | |
143 | } | |
c73fcc84 | 144 | if (!strncmp(commands, "mem=", 4)) { |
1da177e4 LT |
145 | /* |
146 | * "mem=XXX[kKmM]" overrides the PROM-reported | |
147 | * memory size. | |
148 | */ | |
149 | cmdline_memory_size = simple_strtoul(commands + 4, | |
150 | &commands, 0); | |
151 | if (*commands == 'K' || *commands == 'k') { | |
152 | cmdline_memory_size <<= 10; | |
153 | commands++; | |
154 | } else if (*commands=='M' || *commands=='m') { | |
155 | cmdline_memory_size <<= 20; | |
156 | commands++; | |
157 | } | |
158 | } | |
159 | while (*commands && *commands != ' ') | |
160 | commands++; | |
161 | } | |
162 | } | |
163 | ||
1da177e4 LT |
164 | extern unsigned short root_flags; |
165 | extern unsigned short root_dev; | |
166 | extern unsigned short ram_flags; | |
167 | #define RAMDISK_IMAGE_START_MASK 0x07FF | |
168 | #define RAMDISK_PROMPT_FLAG 0x8000 | |
169 | #define RAMDISK_LOAD_FLAG 0x4000 | |
170 | ||
171 | extern int root_mountflags; | |
172 | ||
173 | char reboot_command[COMMAND_LINE_SIZE]; | |
174 | ||
175 | static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 }; | |
176 | ||
951bc82c | 177 | void __init per_cpu_patch(void) |
92704a1c | 178 | { |
92704a1c DM |
179 | struct cpuid_patch_entry *p; |
180 | unsigned long ver; | |
181 | int is_jbus; | |
182 | ||
183 | if (tlb_type == spitfire && !this_is_starfire) | |
184 | return; | |
185 | ||
d82ace7d DM |
186 | is_jbus = 0; |
187 | if (tlb_type != hypervisor) { | |
188 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
ebd8c56c DM |
189 | is_jbus = ((ver >> 32UL) == __JALAPENO_ID || |
190 | (ver >> 32UL) == __SERRANO_ID); | |
d82ace7d | 191 | } |
92704a1c DM |
192 | |
193 | p = &__cpuid_patch; | |
194 | while (p < &__cpuid_patch_end) { | |
195 | unsigned long addr = p->addr; | |
196 | unsigned int *insns; | |
197 | ||
198 | switch (tlb_type) { | |
199 | case spitfire: | |
200 | insns = &p->starfire[0]; | |
201 | break; | |
202 | case cheetah: | |
203 | case cheetah_plus: | |
204 | if (is_jbus) | |
205 | insns = &p->cheetah_jbus[0]; | |
206 | else | |
207 | insns = &p->cheetah_safari[0]; | |
208 | break; | |
d96b8153 DM |
209 | case hypervisor: |
210 | insns = &p->sun4v[0]; | |
211 | break; | |
92704a1c DM |
212 | default: |
213 | prom_printf("Unknown cpu type, halting.\n"); | |
214 | prom_halt(); | |
6cb79b3f | 215 | } |
92704a1c DM |
216 | |
217 | *(unsigned int *) (addr + 0) = insns[0]; | |
840aaef8 | 218 | wmb(); |
92704a1c DM |
219 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); |
220 | ||
221 | *(unsigned int *) (addr + 4) = insns[1]; | |
840aaef8 | 222 | wmb(); |
92704a1c DM |
223 | __asm__ __volatile__("flush %0" : : "r" (addr + 4)); |
224 | ||
225 | *(unsigned int *) (addr + 8) = insns[2]; | |
840aaef8 | 226 | wmb(); |
92704a1c DM |
227 | __asm__ __volatile__("flush %0" : : "r" (addr + 8)); |
228 | ||
229 | *(unsigned int *) (addr + 12) = insns[3]; | |
840aaef8 | 230 | wmb(); |
92704a1c DM |
231 | __asm__ __volatile__("flush %0" : : "r" (addr + 12)); |
232 | ||
233 | p++; | |
234 | } | |
92704a1c DM |
235 | } |
236 | ||
951bc82c | 237 | void __init sun4v_patch(void) |
936f482a | 238 | { |
c7754d46 | 239 | extern void sun4v_hvapi_init(void); |
df7d6aec DM |
240 | struct sun4v_1insn_patch_entry *p1; |
241 | struct sun4v_2insn_patch_entry *p2; | |
936f482a DM |
242 | |
243 | if (tlb_type != hypervisor) | |
244 | return; | |
245 | ||
df7d6aec DM |
246 | p1 = &__sun4v_1insn_patch; |
247 | while (p1 < &__sun4v_1insn_patch_end) { | |
45fec05f | 248 | unsigned long addr = p1->addr; |
936f482a | 249 | |
45fec05f | 250 | *(unsigned int *) (addr + 0) = p1->insn; |
840aaef8 | 251 | wmb(); |
936f482a DM |
252 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); |
253 | ||
45fec05f DM |
254 | p1++; |
255 | } | |
256 | ||
df7d6aec DM |
257 | p2 = &__sun4v_2insn_patch; |
258 | while (p2 < &__sun4v_2insn_patch_end) { | |
45fec05f DM |
259 | unsigned long addr = p2->addr; |
260 | ||
261 | *(unsigned int *) (addr + 0) = p2->insns[0]; | |
840aaef8 | 262 | wmb(); |
45fec05f DM |
263 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); |
264 | ||
fd05068d | 265 | *(unsigned int *) (addr + 4) = p2->insns[1]; |
840aaef8 | 266 | wmb(); |
45fec05f DM |
267 | __asm__ __volatile__("flush %0" : : "r" (addr + 4)); |
268 | ||
269 | p2++; | |
936f482a | 270 | } |
c7754d46 DM |
271 | |
272 | sun4v_hvapi_init(); | |
936f482a DM |
273 | } |
274 | ||
ef7c4d46 DM |
275 | static void __init popc_patch(void) |
276 | { | |
277 | struct popc_3insn_patch_entry *p3; | |
56d205cc | 278 | struct popc_6insn_patch_entry *p6; |
ef7c4d46 DM |
279 | |
280 | p3 = &__popc_3insn_patch; | |
281 | while (p3 < &__popc_3insn_patch_end) { | |
56d205cc | 282 | unsigned long i, addr = p3->addr; |
ef7c4d46 | 283 | |
56d205cc DM |
284 | for (i = 0; i < 3; i++) { |
285 | *(unsigned int *) (addr + (i * 4)) = p3->insns[i]; | |
286 | wmb(); | |
287 | __asm__ __volatile__("flush %0" | |
288 | : : "r" (addr + (i * 4))); | |
289 | } | |
ef7c4d46 | 290 | |
56d205cc DM |
291 | p3++; |
292 | } | |
ef7c4d46 | 293 | |
56d205cc DM |
294 | p6 = &__popc_6insn_patch; |
295 | while (p6 < &__popc_6insn_patch_end) { | |
296 | unsigned long i, addr = p6->addr; | |
ef7c4d46 | 297 | |
56d205cc DM |
298 | for (i = 0; i < 6; i++) { |
299 | *(unsigned int *) (addr + (i * 4)) = p6->insns[i]; | |
300 | wmb(); | |
301 | __asm__ __volatile__("flush %0" | |
302 | : : "r" (addr + (i * 4))); | |
303 | } | |
304 | ||
305 | p6++; | |
ef7c4d46 DM |
306 | } |
307 | } | |
308 | ||
951bc82c DM |
309 | #ifdef CONFIG_SMP |
310 | void __init boot_cpu_id_too_large(int cpu) | |
311 | { | |
312 | prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n", | |
313 | cpu, NR_CPUS); | |
314 | prom_halt(); | |
315 | } | |
316 | #endif | |
317 | ||
ac85fe8b DM |
318 | /* On Ultra, we support all of the v8 capabilities. */ |
319 | unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | | |
320 | HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV | | |
321 | HWCAP_SPARC_V9); | |
322 | EXPORT_SYMBOL(sparc64_elf_hwcap); | |
323 | ||
324 | static const char *hwcaps[] = { | |
325 | "flush", "stbar", "swap", "muldiv", "v9", | |
326 | "ultra3", "blkinit", "n2", | |
327 | ||
328 | /* These strings are as they appear in the machine description | |
329 | * 'hwcap-list' property for cpu nodes. | |
330 | */ | |
331 | "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2", | |
332 | "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau", | |
333 | "ima", "cspare", | |
334 | }; | |
335 | ||
336 | void cpucap_info(struct seq_file *m) | |
337 | { | |
338 | unsigned long caps = sparc64_elf_hwcap; | |
339 | int i, printed = 0; | |
340 | ||
341 | seq_puts(m, "cpucaps\t\t: "); | |
342 | for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { | |
343 | unsigned long bit = 1UL << i; | |
344 | if (caps & bit) { | |
345 | seq_printf(m, "%s%s", | |
346 | printed ? "," : "", hwcaps[i]); | |
347 | printed++; | |
348 | } | |
349 | } | |
350 | seq_putc(m, '\n'); | |
351 | } | |
352 | ||
353 | static void __init report_hwcaps(unsigned long caps) | |
354 | { | |
355 | int i, printed = 0; | |
356 | ||
357 | printk(KERN_INFO "CPU CAPS: ["); | |
358 | for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { | |
359 | unsigned long bit = 1UL << i; | |
360 | if (caps & bit) { | |
361 | printk(KERN_CONT "%s%s", | |
362 | printed ? "," : "", hwcaps[i]); | |
363 | if (++printed == 8) { | |
364 | printk(KERN_CONT "]\n"); | |
365 | printk(KERN_INFO "CPU CAPS: ["); | |
366 | printed = 0; | |
367 | } | |
368 | } | |
369 | } | |
370 | printk(KERN_CONT "]\n"); | |
371 | } | |
372 | ||
373 | static unsigned long __init mdesc_cpu_hwcap_list(void) | |
374 | { | |
375 | struct mdesc_handle *hp; | |
376 | unsigned long caps = 0; | |
377 | const char *prop; | |
378 | int len; | |
379 | u64 pn; | |
380 | ||
381 | hp = mdesc_grab(); | |
382 | if (!hp) | |
383 | return 0; | |
384 | ||
385 | pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu"); | |
386 | if (pn == MDESC_NODE_NULL) | |
387 | goto out; | |
388 | ||
389 | prop = mdesc_get_property(hp, pn, "hwcap-list", &len); | |
390 | if (!prop) | |
391 | goto out; | |
392 | ||
393 | while (len) { | |
394 | int i, plen; | |
395 | ||
396 | for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { | |
397 | unsigned long bit = 1UL << i; | |
398 | ||
399 | if (!strcmp(prop, hwcaps[i])) { | |
400 | caps |= bit; | |
401 | break; | |
402 | } | |
403 | } | |
404 | ||
405 | plen = strlen(prop) + 1; | |
406 | prop += plen; | |
407 | len -= plen; | |
408 | } | |
409 | ||
410 | out: | |
411 | mdesc_release(hp); | |
412 | return caps; | |
413 | } | |
414 | ||
415 | /* This yields a mask that user programs can use to figure out what | |
416 | * instruction set this cpu supports. | |
417 | */ | |
418 | static void __init init_sparc64_elf_hwcap(void) | |
419 | { | |
420 | unsigned long cap = sparc64_elf_hwcap; | |
421 | unsigned long mdesc_caps; | |
422 | ||
423 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
424 | cap |= HWCAP_SPARC_ULTRA3; | |
425 | else if (tlb_type == hypervisor) { | |
426 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || | |
427 | sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || | |
428 | sun4v_chip_type == SUN4V_CHIP_NIAGARA3) | |
429 | cap |= HWCAP_SPARC_BLKINIT; | |
430 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || | |
431 | sun4v_chip_type == SUN4V_CHIP_NIAGARA3) | |
432 | cap |= HWCAP_SPARC_N2; | |
433 | } | |
434 | ||
435 | cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS); | |
436 | ||
437 | mdesc_caps = mdesc_cpu_hwcap_list(); | |
438 | if (!mdesc_caps) { | |
439 | if (tlb_type == spitfire) | |
440 | cap |= AV_SPARC_VIS; | |
441 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
442 | cap |= AV_SPARC_VIS | AV_SPARC_VIS2; | |
1a8e0da5 DM |
443 | if (tlb_type == cheetah_plus) { |
444 | unsigned long impl, ver; | |
445 | ||
446 | __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); | |
447 | impl = ((ver >> 32) & 0xffff); | |
448 | if (impl == PANTHER_IMPL) | |
449 | cap |= AV_SPARC_POPC; | |
450 | } | |
ac85fe8b DM |
451 | if (tlb_type == hypervisor) { |
452 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1) | |
453 | cap |= AV_SPARC_ASI_BLK_INIT; | |
454 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || | |
455 | sun4v_chip_type == SUN4V_CHIP_NIAGARA3) | |
456 | cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | | |
457 | AV_SPARC_ASI_BLK_INIT | | |
458 | AV_SPARC_POPC); | |
459 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3) | |
460 | cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | | |
461 | AV_SPARC_FMAF); | |
462 | } | |
463 | } | |
464 | sparc64_elf_hwcap = cap | mdesc_caps; | |
465 | ||
466 | report_hwcaps(sparc64_elf_hwcap); | |
ef7c4d46 DM |
467 | |
468 | if (sparc64_elf_hwcap & AV_SPARC_POPC) | |
469 | popc_patch(); | |
ac85fe8b DM |
470 | } |
471 | ||
1da177e4 LT |
472 | void __init setup_arch(char **cmdline_p) |
473 | { | |
1da177e4 LT |
474 | /* Initialize PROM console and command line. */ |
475 | *cmdline_p = prom_getbootargs(); | |
383464c0 | 476 | strcpy(boot_command_line, *cmdline_p); |
ce3b1d47 | 477 | parse_early_param(); |
1da177e4 | 478 | |
3c62a2d3 | 479 | boot_flags_init(*cmdline_p); |
c57ec52f DM |
480 | #ifdef CONFIG_EARLYFB |
481 | if (btext_find_display()) | |
482 | #endif | |
483 | register_console(&prom_early_console); | |
3c62a2d3 | 484 | |
3a8c069d DM |
485 | if (tlb_type == hypervisor) |
486 | printk("ARCH: SUN4V\n"); | |
487 | else | |
488 | printk("ARCH: SUN4U\n"); | |
1da177e4 LT |
489 | |
490 | #ifdef CONFIG_DUMMY_CONSOLE | |
491 | conswitchp = &dummy_con; | |
1da177e4 LT |
492 | #endif |
493 | ||
1da177e4 | 494 | idprom_init(); |
1da177e4 LT |
495 | |
496 | if (!root_flags) | |
497 | root_mountflags &= ~MS_RDONLY; | |
498 | ROOT_DEV = old_decode_dev(root_dev); | |
467418f3 | 499 | #ifdef CONFIG_BLK_DEV_RAM |
1da177e4 LT |
500 | rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK; |
501 | rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0); | |
502 | rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0); | |
503 | #endif | |
504 | ||
f3169641 | 505 | task_thread_info(&init_task)->kregs = &fake_swapper_regs; |
1da177e4 LT |
506 | |
507 | #ifdef CONFIG_IP_PNP | |
508 | if (!ic_set_manually) { | |
8d125562 | 509 | phandle chosen = prom_finddevice("/chosen"); |
1da177e4 LT |
510 | u32 cl, sv, gw; |
511 | ||
512 | cl = prom_getintdefault (chosen, "client-ip", 0); | |
513 | sv = prom_getintdefault (chosen, "server-ip", 0); | |
514 | gw = prom_getintdefault (chosen, "gateway-ip", 0); | |
515 | if (cl && sv) { | |
516 | ic_myaddr = cl; | |
517 | ic_servaddr = sv; | |
518 | if (gw) | |
519 | ic_gateway = gw; | |
520 | #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP) | |
521 | ic_proto_enabled = 0; | |
522 | #endif | |
523 | } | |
524 | } | |
525 | #endif | |
526 | ||
56fb4df6 | 527 | /* Get boot processor trap_block[] setup. */ |
72aff53f | 528 | init_cur_cpu_trap(current_thread_info()); |
52845cdb DM |
529 | |
530 | paging_init(); | |
ac85fe8b | 531 | init_sparc64_elf_hwcap(); |
1da177e4 LT |
532 | } |
533 | ||
1da177e4 LT |
534 | extern int stop_a_enabled; |
535 | ||
536 | void sun_do_break(void) | |
537 | { | |
538 | if (!stop_a_enabled) | |
539 | return; | |
540 | ||
541 | prom_printf("\n"); | |
542 | flush_user_windows(); | |
543 | ||
544 | prom_cmdline(); | |
545 | } | |
917c3660 | 546 | EXPORT_SYMBOL(sun_do_break); |
1da177e4 | 547 | |
1da177e4 | 548 | int stop_a_enabled = 1; |
917c3660 | 549 | EXPORT_SYMBOL(stop_a_enabled); |