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Commit | Line | Data |
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b00dc837 | 1 | /* |
1da177e4 LT |
2 | * linux/arch/sparc64/kernel/setup.c |
3 | * | |
4 | * Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
6 | */ | |
7 | ||
8 | #include <linux/errno.h> | |
9 | #include <linux/sched.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/mm.h> | |
12 | #include <linux/stddef.h> | |
13 | #include <linux/unistd.h> | |
14 | #include <linux/ptrace.h> | |
1da177e4 LT |
15 | #include <asm/smp.h> |
16 | #include <linux/user.h> | |
894673ee | 17 | #include <linux/screen_info.h> |
1da177e4 | 18 | #include <linux/delay.h> |
1da177e4 LT |
19 | #include <linux/fs.h> |
20 | #include <linux/seq_file.h> | |
21 | #include <linux/syscalls.h> | |
22 | #include <linux/kdev_t.h> | |
23 | #include <linux/major.h> | |
24 | #include <linux/string.h> | |
25 | #include <linux/init.h> | |
26 | #include <linux/inet.h> | |
27 | #include <linux/console.h> | |
28 | #include <linux/root_dev.h> | |
29 | #include <linux/interrupt.h> | |
30 | #include <linux/cpu.h> | |
31 | #include <linux/initrd.h> | |
ac85fe8b | 32 | #include <linux/module.h> |
1da177e4 | 33 | |
1da177e4 LT |
34 | #include <asm/io.h> |
35 | #include <asm/processor.h> | |
36 | #include <asm/oplib.h> | |
37 | #include <asm/page.h> | |
38 | #include <asm/pgtable.h> | |
39 | #include <asm/idprom.h> | |
40 | #include <asm/head.h> | |
41 | #include <asm/starfire.h> | |
42 | #include <asm/mmu_context.h> | |
43 | #include <asm/timer.h> | |
44 | #include <asm/sections.h> | |
45 | #include <asm/setup.h> | |
46 | #include <asm/mmu.h> | |
5cbc3073 | 47 | #include <asm/ns87303.h> |
c57ec52f | 48 | #include <asm/btext.h> |
ac85fe8b DM |
49 | #include <asm/elf.h> |
50 | #include <asm/mdesc.h> | |
d550bbd4 | 51 | #include <asm/cacheflush.h> |
1da177e4 LT |
52 | |
53 | #ifdef CONFIG_IP_PNP | |
54 | #include <net/ipconfig.h> | |
55 | #endif | |
56 | ||
3d5ae6b6 | 57 | #include "entry.h" |
53ae3419 | 58 | #include "kernel.h" |
3d5ae6b6 | 59 | |
5cbc3073 DM |
60 | /* Used to synchronize accesses to NatSemi SUPER I/O chip configure |
61 | * operations in asm/ns87303.h | |
62 | */ | |
63 | DEFINE_SPINLOCK(ns87303_lock); | |
917c3660 | 64 | EXPORT_SYMBOL(ns87303_lock); |
5cbc3073 | 65 | |
1da177e4 LT |
66 | struct screen_info screen_info = { |
67 | 0, 0, /* orig-x, orig-y */ | |
68 | 0, /* unused */ | |
69 | 0, /* orig-video-page */ | |
70 | 0, /* orig-video-mode */ | |
71 | 128, /* orig-video-cols */ | |
72 | 0, 0, 0, /* unused, ega_bx, unused */ | |
73 | 54, /* orig-video-lines */ | |
74 | 0, /* orig-video-isVGA */ | |
75 | 16 /* orig-video-points */ | |
76 | }; | |
77 | ||
1da177e4 LT |
78 | static void |
79 | prom_console_write(struct console *con, const char *s, unsigned n) | |
80 | { | |
81 | prom_write(s, n); | |
82 | } | |
83 | ||
1da177e4 LT |
84 | /* Exported for mm/init.c:paging_init. */ |
85 | unsigned long cmdline_memory_size = 0; | |
86 | ||
3c62a2d3 DM |
87 | static struct console prom_early_console = { |
88 | .name = "earlyprom", | |
1da177e4 | 89 | .write = prom_console_write, |
db9a7fb1 | 90 | .flags = CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME, |
1da177e4 LT |
91 | .index = -1, |
92 | }; | |
93 | ||
1da177e4 LT |
94 | /* |
95 | * Process kernel command line switches that are specific to the | |
96 | * SPARC or that require special low-level processing. | |
97 | */ | |
98 | static void __init process_switch(char c) | |
99 | { | |
100 | switch (c) { | |
101 | case 'd': | |
1da177e4 | 102 | case 's': |
1da177e4 LT |
103 | break; |
104 | case 'h': | |
105 | prom_printf("boot_flags_init: Halt!\n"); | |
106 | prom_halt(); | |
107 | break; | |
108 | case 'p': | |
11032c17 | 109 | prom_early_console.flags &= ~CON_BOOT; |
1da177e4 | 110 | break; |
816242da DM |
111 | case 'P': |
112 | /* Force UltraSPARC-III P-Cache on. */ | |
113 | if (tlb_type != cheetah) { | |
114 | printk("BOOT: Ignoring P-Cache force option.\n"); | |
115 | break; | |
116 | } | |
117 | cheetah_pcache_forced_on = 1; | |
118 | add_taint(TAINT_MACHINE_CHECK); | |
119 | cheetah_enable_pcache(); | |
120 | break; | |
121 | ||
1da177e4 LT |
122 | default: |
123 | printk("Unknown boot switch (-%c)\n", c); | |
124 | break; | |
125 | } | |
126 | } | |
127 | ||
1da177e4 LT |
128 | static void __init boot_flags_init(char *commands) |
129 | { | |
130 | while (*commands) { | |
131 | /* Move to the start of the next "argument". */ | |
132 | while (*commands && *commands == ' ') | |
133 | commands++; | |
134 | ||
135 | /* Process any command switches, otherwise skip it. */ | |
136 | if (*commands == '\0') | |
137 | break; | |
138 | if (*commands == '-') { | |
139 | commands++; | |
140 | while (*commands && *commands != ' ') | |
141 | process_switch(*commands++); | |
142 | continue; | |
143 | } | |
c73fcc84 | 144 | if (!strncmp(commands, "mem=", 4)) { |
1da177e4 LT |
145 | /* |
146 | * "mem=XXX[kKmM]" overrides the PROM-reported | |
147 | * memory size. | |
148 | */ | |
149 | cmdline_memory_size = simple_strtoul(commands + 4, | |
150 | &commands, 0); | |
151 | if (*commands == 'K' || *commands == 'k') { | |
152 | cmdline_memory_size <<= 10; | |
153 | commands++; | |
154 | } else if (*commands=='M' || *commands=='m') { | |
155 | cmdline_memory_size <<= 20; | |
156 | commands++; | |
157 | } | |
158 | } | |
159 | while (*commands && *commands != ' ') | |
160 | commands++; | |
161 | } | |
162 | } | |
163 | ||
1da177e4 LT |
164 | extern unsigned short root_flags; |
165 | extern unsigned short root_dev; | |
166 | extern unsigned short ram_flags; | |
167 | #define RAMDISK_IMAGE_START_MASK 0x07FF | |
168 | #define RAMDISK_PROMPT_FLAG 0x8000 | |
169 | #define RAMDISK_LOAD_FLAG 0x4000 | |
170 | ||
171 | extern int root_mountflags; | |
172 | ||
173 | char reboot_command[COMMAND_LINE_SIZE]; | |
174 | ||
175 | static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 }; | |
176 | ||
951bc82c | 177 | void __init per_cpu_patch(void) |
92704a1c | 178 | { |
92704a1c DM |
179 | struct cpuid_patch_entry *p; |
180 | unsigned long ver; | |
181 | int is_jbus; | |
182 | ||
183 | if (tlb_type == spitfire && !this_is_starfire) | |
184 | return; | |
185 | ||
d82ace7d DM |
186 | is_jbus = 0; |
187 | if (tlb_type != hypervisor) { | |
188 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
ebd8c56c DM |
189 | is_jbus = ((ver >> 32UL) == __JALAPENO_ID || |
190 | (ver >> 32UL) == __SERRANO_ID); | |
d82ace7d | 191 | } |
92704a1c DM |
192 | |
193 | p = &__cpuid_patch; | |
194 | while (p < &__cpuid_patch_end) { | |
195 | unsigned long addr = p->addr; | |
196 | unsigned int *insns; | |
197 | ||
198 | switch (tlb_type) { | |
199 | case spitfire: | |
200 | insns = &p->starfire[0]; | |
201 | break; | |
202 | case cheetah: | |
203 | case cheetah_plus: | |
204 | if (is_jbus) | |
205 | insns = &p->cheetah_jbus[0]; | |
206 | else | |
207 | insns = &p->cheetah_safari[0]; | |
208 | break; | |
d96b8153 DM |
209 | case hypervisor: |
210 | insns = &p->sun4v[0]; | |
211 | break; | |
92704a1c DM |
212 | default: |
213 | prom_printf("Unknown cpu type, halting.\n"); | |
214 | prom_halt(); | |
6cb79b3f | 215 | } |
92704a1c DM |
216 | |
217 | *(unsigned int *) (addr + 0) = insns[0]; | |
840aaef8 | 218 | wmb(); |
92704a1c DM |
219 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); |
220 | ||
221 | *(unsigned int *) (addr + 4) = insns[1]; | |
840aaef8 | 222 | wmb(); |
92704a1c DM |
223 | __asm__ __volatile__("flush %0" : : "r" (addr + 4)); |
224 | ||
225 | *(unsigned int *) (addr + 8) = insns[2]; | |
840aaef8 | 226 | wmb(); |
92704a1c DM |
227 | __asm__ __volatile__("flush %0" : : "r" (addr + 8)); |
228 | ||
229 | *(unsigned int *) (addr + 12) = insns[3]; | |
840aaef8 | 230 | wmb(); |
92704a1c DM |
231 | __asm__ __volatile__("flush %0" : : "r" (addr + 12)); |
232 | ||
233 | p++; | |
234 | } | |
92704a1c DM |
235 | } |
236 | ||
0b64120c DM |
237 | void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start, |
238 | struct sun4v_1insn_patch_entry *end) | |
936f482a | 239 | { |
0b64120c DM |
240 | while (start < end) { |
241 | unsigned long addr = start->addr; | |
936f482a | 242 | |
0b64120c | 243 | *(unsigned int *) (addr + 0) = start->insn; |
840aaef8 | 244 | wmb(); |
936f482a DM |
245 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); |
246 | ||
0b64120c | 247 | start++; |
45fec05f | 248 | } |
0b64120c | 249 | } |
45fec05f | 250 | |
0b64120c DM |
251 | void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start, |
252 | struct sun4v_2insn_patch_entry *end) | |
253 | { | |
254 | while (start < end) { | |
255 | unsigned long addr = start->addr; | |
45fec05f | 256 | |
0b64120c | 257 | *(unsigned int *) (addr + 0) = start->insns[0]; |
840aaef8 | 258 | wmb(); |
45fec05f DM |
259 | __asm__ __volatile__("flush %0" : : "r" (addr + 0)); |
260 | ||
0b64120c | 261 | *(unsigned int *) (addr + 4) = start->insns[1]; |
840aaef8 | 262 | wmb(); |
45fec05f DM |
263 | __asm__ __volatile__("flush %0" : : "r" (addr + 4)); |
264 | ||
0b64120c | 265 | start++; |
936f482a | 266 | } |
0b64120c DM |
267 | } |
268 | ||
269 | void __init sun4v_patch(void) | |
270 | { | |
271 | extern void sun4v_hvapi_init(void); | |
272 | ||
273 | if (tlb_type != hypervisor) | |
274 | return; | |
275 | ||
276 | sun4v_patch_1insn_range(&__sun4v_1insn_patch, | |
277 | &__sun4v_1insn_patch_end); | |
278 | ||
279 | sun4v_patch_2insn_range(&__sun4v_2insn_patch, | |
280 | &__sun4v_2insn_patch_end); | |
c7754d46 DM |
281 | |
282 | sun4v_hvapi_init(); | |
936f482a DM |
283 | } |
284 | ||
ef7c4d46 DM |
285 | static void __init popc_patch(void) |
286 | { | |
287 | struct popc_3insn_patch_entry *p3; | |
56d205cc | 288 | struct popc_6insn_patch_entry *p6; |
ef7c4d46 DM |
289 | |
290 | p3 = &__popc_3insn_patch; | |
291 | while (p3 < &__popc_3insn_patch_end) { | |
56d205cc | 292 | unsigned long i, addr = p3->addr; |
ef7c4d46 | 293 | |
56d205cc DM |
294 | for (i = 0; i < 3; i++) { |
295 | *(unsigned int *) (addr + (i * 4)) = p3->insns[i]; | |
296 | wmb(); | |
297 | __asm__ __volatile__("flush %0" | |
298 | : : "r" (addr + (i * 4))); | |
299 | } | |
ef7c4d46 | 300 | |
56d205cc DM |
301 | p3++; |
302 | } | |
ef7c4d46 | 303 | |
56d205cc DM |
304 | p6 = &__popc_6insn_patch; |
305 | while (p6 < &__popc_6insn_patch_end) { | |
306 | unsigned long i, addr = p6->addr; | |
ef7c4d46 | 307 | |
56d205cc DM |
308 | for (i = 0; i < 6; i++) { |
309 | *(unsigned int *) (addr + (i * 4)) = p6->insns[i]; | |
310 | wmb(); | |
311 | __asm__ __volatile__("flush %0" | |
312 | : : "r" (addr + (i * 4))); | |
313 | } | |
314 | ||
315 | p6++; | |
ef7c4d46 DM |
316 | } |
317 | } | |
318 | ||
951bc82c DM |
319 | #ifdef CONFIG_SMP |
320 | void __init boot_cpu_id_too_large(int cpu) | |
321 | { | |
322 | prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n", | |
323 | cpu, NR_CPUS); | |
324 | prom_halt(); | |
325 | } | |
326 | #endif | |
327 | ||
ac85fe8b DM |
328 | /* On Ultra, we support all of the v8 capabilities. */ |
329 | unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | | |
330 | HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV | | |
331 | HWCAP_SPARC_V9); | |
332 | EXPORT_SYMBOL(sparc64_elf_hwcap); | |
333 | ||
334 | static const char *hwcaps[] = { | |
335 | "flush", "stbar", "swap", "muldiv", "v9", | |
336 | "ultra3", "blkinit", "n2", | |
337 | ||
338 | /* These strings are as they appear in the machine description | |
339 | * 'hwcap-list' property for cpu nodes. | |
340 | */ | |
341 | "mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2", | |
342 | "ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau", | |
343 | "ima", "cspare", | |
344 | }; | |
345 | ||
346 | void cpucap_info(struct seq_file *m) | |
347 | { | |
348 | unsigned long caps = sparc64_elf_hwcap; | |
349 | int i, printed = 0; | |
350 | ||
351 | seq_puts(m, "cpucaps\t\t: "); | |
352 | for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { | |
353 | unsigned long bit = 1UL << i; | |
354 | if (caps & bit) { | |
355 | seq_printf(m, "%s%s", | |
356 | printed ? "," : "", hwcaps[i]); | |
357 | printed++; | |
358 | } | |
359 | } | |
360 | seq_putc(m, '\n'); | |
361 | } | |
362 | ||
363 | static void __init report_hwcaps(unsigned long caps) | |
364 | { | |
365 | int i, printed = 0; | |
366 | ||
367 | printk(KERN_INFO "CPU CAPS: ["); | |
368 | for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { | |
369 | unsigned long bit = 1UL << i; | |
370 | if (caps & bit) { | |
371 | printk(KERN_CONT "%s%s", | |
372 | printed ? "," : "", hwcaps[i]); | |
373 | if (++printed == 8) { | |
374 | printk(KERN_CONT "]\n"); | |
375 | printk(KERN_INFO "CPU CAPS: ["); | |
376 | printed = 0; | |
377 | } | |
378 | } | |
379 | } | |
380 | printk(KERN_CONT "]\n"); | |
381 | } | |
382 | ||
383 | static unsigned long __init mdesc_cpu_hwcap_list(void) | |
384 | { | |
385 | struct mdesc_handle *hp; | |
386 | unsigned long caps = 0; | |
387 | const char *prop; | |
388 | int len; | |
389 | u64 pn; | |
390 | ||
391 | hp = mdesc_grab(); | |
392 | if (!hp) | |
393 | return 0; | |
394 | ||
395 | pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu"); | |
396 | if (pn == MDESC_NODE_NULL) | |
397 | goto out; | |
398 | ||
399 | prop = mdesc_get_property(hp, pn, "hwcap-list", &len); | |
400 | if (!prop) | |
401 | goto out; | |
402 | ||
403 | while (len) { | |
404 | int i, plen; | |
405 | ||
406 | for (i = 0; i < ARRAY_SIZE(hwcaps); i++) { | |
407 | unsigned long bit = 1UL << i; | |
408 | ||
409 | if (!strcmp(prop, hwcaps[i])) { | |
410 | caps |= bit; | |
411 | break; | |
412 | } | |
413 | } | |
414 | ||
415 | plen = strlen(prop) + 1; | |
416 | prop += plen; | |
417 | len -= plen; | |
418 | } | |
419 | ||
420 | out: | |
421 | mdesc_release(hp); | |
422 | return caps; | |
423 | } | |
424 | ||
425 | /* This yields a mask that user programs can use to figure out what | |
426 | * instruction set this cpu supports. | |
427 | */ | |
428 | static void __init init_sparc64_elf_hwcap(void) | |
429 | { | |
430 | unsigned long cap = sparc64_elf_hwcap; | |
431 | unsigned long mdesc_caps; | |
432 | ||
433 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
434 | cap |= HWCAP_SPARC_ULTRA3; | |
435 | else if (tlb_type == hypervisor) { | |
436 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || | |
437 | sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || | |
08cefa9f DM |
438 | sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || |
439 | sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || | |
440 | sun4v_chip_type == SUN4V_CHIP_NIAGARA5) | |
ac85fe8b DM |
441 | cap |= HWCAP_SPARC_BLKINIT; |
442 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || | |
08cefa9f DM |
443 | sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || |
444 | sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || | |
445 | sun4v_chip_type == SUN4V_CHIP_NIAGARA5) | |
ac85fe8b DM |
446 | cap |= HWCAP_SPARC_N2; |
447 | } | |
448 | ||
449 | cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS); | |
450 | ||
451 | mdesc_caps = mdesc_cpu_hwcap_list(); | |
452 | if (!mdesc_caps) { | |
453 | if (tlb_type == spitfire) | |
454 | cap |= AV_SPARC_VIS; | |
455 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
456 | cap |= AV_SPARC_VIS | AV_SPARC_VIS2; | |
1a8e0da5 DM |
457 | if (tlb_type == cheetah_plus) { |
458 | unsigned long impl, ver; | |
459 | ||
460 | __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); | |
461 | impl = ((ver >> 32) & 0xffff); | |
462 | if (impl == PANTHER_IMPL) | |
463 | cap |= AV_SPARC_POPC; | |
464 | } | |
ac85fe8b DM |
465 | if (tlb_type == hypervisor) { |
466 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1) | |
467 | cap |= AV_SPARC_ASI_BLK_INIT; | |
468 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || | |
08cefa9f DM |
469 | sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || |
470 | sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || | |
471 | sun4v_chip_type == SUN4V_CHIP_NIAGARA5) | |
ac85fe8b DM |
472 | cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 | |
473 | AV_SPARC_ASI_BLK_INIT | | |
474 | AV_SPARC_POPC); | |
08cefa9f DM |
475 | if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || |
476 | sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || | |
477 | sun4v_chip_type == SUN4V_CHIP_NIAGARA5) | |
ac85fe8b DM |
478 | cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC | |
479 | AV_SPARC_FMAF); | |
480 | } | |
481 | } | |
482 | sparc64_elf_hwcap = cap | mdesc_caps; | |
483 | ||
484 | report_hwcaps(sparc64_elf_hwcap); | |
ef7c4d46 DM |
485 | |
486 | if (sparc64_elf_hwcap & AV_SPARC_POPC) | |
487 | popc_patch(); | |
ac85fe8b DM |
488 | } |
489 | ||
1da177e4 LT |
490 | void __init setup_arch(char **cmdline_p) |
491 | { | |
1da177e4 LT |
492 | /* Initialize PROM console and command line. */ |
493 | *cmdline_p = prom_getbootargs(); | |
383464c0 | 494 | strcpy(boot_command_line, *cmdline_p); |
ce3b1d47 | 495 | parse_early_param(); |
1da177e4 | 496 | |
3c62a2d3 | 497 | boot_flags_init(*cmdline_p); |
c57ec52f DM |
498 | #ifdef CONFIG_EARLYFB |
499 | if (btext_find_display()) | |
500 | #endif | |
501 | register_console(&prom_early_console); | |
3c62a2d3 | 502 | |
3a8c069d DM |
503 | if (tlb_type == hypervisor) |
504 | printk("ARCH: SUN4V\n"); | |
505 | else | |
506 | printk("ARCH: SUN4U\n"); | |
1da177e4 LT |
507 | |
508 | #ifdef CONFIG_DUMMY_CONSOLE | |
509 | conswitchp = &dummy_con; | |
1da177e4 LT |
510 | #endif |
511 | ||
1da177e4 | 512 | idprom_init(); |
1da177e4 LT |
513 | |
514 | if (!root_flags) | |
515 | root_mountflags &= ~MS_RDONLY; | |
516 | ROOT_DEV = old_decode_dev(root_dev); | |
467418f3 | 517 | #ifdef CONFIG_BLK_DEV_RAM |
1da177e4 LT |
518 | rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK; |
519 | rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0); | |
520 | rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0); | |
521 | #endif | |
522 | ||
f3169641 | 523 | task_thread_info(&init_task)->kregs = &fake_swapper_regs; |
1da177e4 LT |
524 | |
525 | #ifdef CONFIG_IP_PNP | |
526 | if (!ic_set_manually) { | |
8d125562 | 527 | phandle chosen = prom_finddevice("/chosen"); |
1da177e4 LT |
528 | u32 cl, sv, gw; |
529 | ||
530 | cl = prom_getintdefault (chosen, "client-ip", 0); | |
531 | sv = prom_getintdefault (chosen, "server-ip", 0); | |
532 | gw = prom_getintdefault (chosen, "gateway-ip", 0); | |
533 | if (cl && sv) { | |
534 | ic_myaddr = cl; | |
535 | ic_servaddr = sv; | |
536 | if (gw) | |
537 | ic_gateway = gw; | |
538 | #if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP) | |
539 | ic_proto_enabled = 0; | |
540 | #endif | |
541 | } | |
542 | } | |
543 | #endif | |
544 | ||
56fb4df6 | 545 | /* Get boot processor trap_block[] setup. */ |
72aff53f | 546 | init_cur_cpu_trap(current_thread_info()); |
52845cdb DM |
547 | |
548 | paging_init(); | |
ac85fe8b | 549 | init_sparc64_elf_hwcap(); |
1da177e4 LT |
550 | } |
551 | ||
1da177e4 LT |
552 | extern int stop_a_enabled; |
553 | ||
554 | void sun_do_break(void) | |
555 | { | |
556 | if (!stop_a_enabled) | |
557 | return; | |
558 | ||
559 | prom_printf("\n"); | |
560 | flush_user_windows(); | |
561 | ||
562 | prom_cmdline(); | |
563 | } | |
917c3660 | 564 | EXPORT_SYMBOL(sun_do_break); |
1da177e4 | 565 | |
1da177e4 | 566 | int stop_a_enabled = 1; |
917c3660 | 567 | EXPORT_SYMBOL(stop_a_enabled); |