[mirror_ubuntu-artful-kernel.git] / arch / sparc / kernel / setup_64.c

/*
 *  linux/arch/sparc64/kernel/setup.c
 *
 *  Copyright (C) 1995,1996  David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1997       Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <asm/smp.h>
#include <linux/user.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/syscalls.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/inet.h>
#include <linux/console.h>
#include <linux/root_dev.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/start_kernel.h>
#include <linux/bootmem.h>

#include <asm/io.h>
#include <asm/processor.h>
#include <asm/oplib.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/idprom.h>
#include <asm/head.h>
#include <asm/starfire.h>
#include <asm/mmu_context.h>
#include <asm/timer.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/mmu.h>
#include <asm/ns87303.h>
#include <asm/btext.h>
#include <asm/elf.h>
#include <asm/mdesc.h>
#include <asm/cacheflush.h>
#include <asm/dma.h>
#include <asm/irq.h>

#ifdef CONFIG_IP_PNP
#include <net/ipconfig.h>
#endif

#include "entry.h"
#include "kernel.h"

/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
 * operations in asm/ns87303.h
 */
DEFINE_SPINLOCK(ns87303_lock);
EXPORT_SYMBOL(ns87303_lock);

struct screen_info screen_info = {
	0, 0,			/* orig-x, orig-y */
	0,			/* unused */
	0,			/* orig-video-page */
	0,			/* orig-video-mode */
	128,			/* orig-video-cols */
	0, 0, 0,		/* unused, ega_bx, unused */
	54,			/* orig-video-lines */
	0,                      /* orig-video-isVGA */
	16                      /* orig-video-points */
};

static void
prom_console_write(struct console *con, const char *s, unsigned int n)
{
	prom_write(s, n);
}

/* Exported for mm/init.c:paging_init. */
unsigned long cmdline_memory_size = 0;

static struct console prom_early_console = {
	.name =		"earlyprom",
	.write =	prom_console_write,
	.flags =	CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
	.index =	-1,
};

/*
 * Process kernel command line switches that are specific to the
 * SPARC or that require special low-level processing.
 */
static void __init process_switch(char c)
{
	switch (c) {
	case 'd':
	case 's':
		break;
	case 'h':
		prom_printf("boot_flags_init: Halt!\n");
		prom_halt();
		break;
	case 'p':
		prom_early_console.flags &= ~CON_BOOT;
		break;
	case 'P':
		/* Force UltraSPARC-III P-Cache on. */
		if (tlb_type != cheetah) {
			printk("BOOT: Ignoring P-Cache force option.\n");
			break;
		}
		cheetah_pcache_forced_on = 1;
		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
		cheetah_enable_pcache();
		break;

	default:
		printk("Unknown boot switch (-%c)\n", c);
		break;
	}
}

static void __init boot_flags_init(char *commands)
{
	while (*commands) {
		/* Move to the start of the next "argument". */
		while (*commands == ' ')
			commands++;

		/* Process any command switches, otherwise skip it. */
		if (*commands == '\0')
			break;
		if (*commands == '-') {
			commands++;
			while (*commands && *commands != ' ')
				process_switch(*commands++);
			continue;
		}
		if (!strncmp(commands, "mem=", 4))
			cmdline_memory_size = memparse(commands + 4, &commands);

		while (*commands && *commands != ' ')
			commands++;
	}
}

extern unsigned short root_flags;
extern unsigned short root_dev;
extern unsigned short ram_flags;
#define RAMDISK_IMAGE_START_MASK	0x07FF
#define RAMDISK_PROMPT_FLAG		0x8000
#define RAMDISK_LOAD_FLAG		0x4000

extern int root_mountflags;

char reboot_command[COMMAND_LINE_SIZE];

static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };

static void __init per_cpu_patch(void)
{
	struct cpuid_patch_entry *p;
	unsigned long ver;
	int is_jbus;

	if (tlb_type == spitfire && !this_is_starfire)
		return;

	is_jbus = 0;
	if (tlb_type != hypervisor) {
		__asm__ ("rdpr %%ver, %0" : "=r" (ver));
		is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
			   (ver >> 32UL) == __SERRANO_ID);
	}

	p = &__cpuid_patch;
	while (p < &__cpuid_patch_end) {
		unsigned long addr = p->addr;
		unsigned int *insns;

		switch (tlb_type) {
		case spitfire:
			insns = &p->starfire[0];
			break;
		case cheetah:
		case cheetah_plus:
			if (is_jbus)
				insns = &p->cheetah_jbus[0];
			else
				insns = &p->cheetah_safari[0];
			break;
		case hypervisor:
			insns = &p->sun4v[0];
			break;
		default:
			prom_printf("Unknown cpu type, halting.\n");
			prom_halt();
		}

		*(unsigned int *) (addr +  0) = insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		*(unsigned int *) (addr +  8) = insns[2];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  8));

		*(unsigned int *) (addr + 12) = insns[3];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr + 12));

		p++;
	}
}

void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
			     struct sun4v_1insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insn;
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		start++;
	}
}

void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
			     struct sun4v_2insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = start->insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		start++;
	}
}

void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
			     struct sun4v_2insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = start->insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		start++;
	}
}

static void __init sun4v_patch(void)
{
	extern void sun4v_hvapi_init(void);

	if (tlb_type != hypervisor)
		return;

	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
				&__sun4v_1insn_patch_end);

	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
				&__sun4v_2insn_patch_end);

	switch (sun4v_chip_type) {
	case SUN4V_CHIP_SPARC_M7:
	case SUN4V_CHIP_SPARC_M8:
	case SUN4V_CHIP_SPARC_SN:
		sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
					 &__sun_m7_2insn_patch_end);
		break;
	default:
		break;
	}

	sun4v_hvapi_init();
}

static void __init popc_patch(void)
{
	struct popc_3insn_patch_entry *p3;
	struct popc_6insn_patch_entry *p6;

	p3 = &__popc_3insn_patch;
	while (p3 < &__popc_3insn_patch_end) {
		unsigned long i, addr = p3->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p3->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p3++;
	}

	p6 = &__popc_6insn_patch;
	while (p6 < &__popc_6insn_patch_end) {
		unsigned long i, addr = p6->addr;

		for (i = 0; i < 6; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p6->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p6++;
	}
}

static void __init pause_patch(void)
{
	struct pause_patch_entry *p;

	p = &__pause_3insn_patch;
	while (p < &__pause_3insn_patch_end) {
		unsigned long i, addr = p->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p++;
	}
}

void __init start_early_boot(void)
{
	int cpu;

	check_if_starfire();
	per_cpu_patch();
	sun4v_patch();

	cpu = hard_smp_processor_id();
	if (cpu >= NR_CPUS) {
		prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
			    cpu, NR_CPUS);
		prom_halt();
	}
	current_thread_info()->cpu = cpu;

	time_init_early();
	prom_init_report();
	start_kernel();
}

/* On Ultra, we support all of the v8 capabilities. */
unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
				   HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
				   HWCAP_SPARC_V9);
EXPORT_SYMBOL(sparc64_elf_hwcap);

static const char *hwcaps[] = {
	"flush", "stbar", "swap", "muldiv", "v9",
	"ultra3", "blkinit", "n2",

	/* These strings are as they appear in the machine description
	 * 'hwcap-list' property for cpu nodes.
	 */
	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
	"ima", "cspare", "pause", "cbcond", NULL /*reserved for crypto */,
	"adp",
};

static const char *crypto_hwcaps[] = {
	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
};

void cpucap_info(struct seq_file *m)
{
	unsigned long caps = sparc64_elf_hwcap;
	int i, printed = 0;

	seq_puts(m, "cpucaps\t\t: ");
	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (hwcaps[i] && (caps & bit)) {
			seq_printf(m, "%s%s",
				   printed ? "," : "", hwcaps[i]);
			printed++;
		}
	}
	if (caps & HWCAP_SPARC_CRYPTO) {
		unsigned long cfr;

		__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			unsigned long bit = 1UL << i;
			if (cfr & bit) {
				seq_printf(m, "%s%s",
					   printed ? "," : "", crypto_hwcaps[i]);
				printed++;
			}
		}
	}
	seq_putc(m, '\n');
}

static void __init report_one_hwcap(int *printed, const char *name)
{
	if ((*printed) == 0)
		printk(KERN_INFO "CPU CAPS: [");
	printk(KERN_CONT "%s%s",
	       (*printed) ? "," : "", name);
	if (++(*printed) == 8) {
		printk(KERN_CONT "]\n");
		*printed = 0;
	}
}

static void __init report_crypto_hwcaps(int *printed)
{
	unsigned long cfr;
	int i;

	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));

	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (cfr & bit)
			report_one_hwcap(printed, crypto_hwcaps[i]);
	}
}

static void __init report_hwcaps(unsigned long caps)
{
	int i, printed = 0;

	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (hwcaps[i] && (caps & bit))
			report_one_hwcap(&printed, hwcaps[i]);
	}
	if (caps & HWCAP_SPARC_CRYPTO)
		report_crypto_hwcaps(&printed);
	if (printed != 0)
		printk(KERN_CONT "]\n");
}

static unsigned long __init mdesc_cpu_hwcap_list(void)
{
	struct mdesc_handle *hp;
	unsigned long caps = 0;
	const char *prop;
	int len;
	u64 pn;

	hp = mdesc_grab();
	if (!hp)
		return 0;

	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	if (pn == MDESC_NODE_NULL)
		goto out;

	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	if (!prop)
		goto out;

	while (len) {
		int i, plen;

		for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
			unsigned long bit = 1UL << i;

			if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
				caps |= bit;
				break;
			}
		}
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			if (!strcmp(prop, crypto_hwcaps[i]))
				caps |= HWCAP_SPARC_CRYPTO;
		}

		plen = strlen(prop) + 1;
		prop += plen;
		len -= plen;
	}

out:
	mdesc_release(hp);
	return caps;
}

/* This yields a mask that user programs can use to figure out what
 * instruction set this cpu supports.
 */
static void __init init_sparc64_elf_hwcap(void)
{
	unsigned long cap = sparc64_elf_hwcap;
	unsigned long mdesc_caps;

	if (tlb_type == cheetah || tlb_type == cheetah_plus)
		cap |= HWCAP_SPARC_ULTRA3;
	else if (tlb_type == hypervisor) {
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_BLKINIT;
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_N2;
	}

	cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);

	mdesc_caps = mdesc_cpu_hwcap_list();
	if (!mdesc_caps) {
		if (tlb_type == spitfire)
			cap |= AV_SPARC_VIS;
		if (tlb_type == cheetah || tlb_type == cheetah_plus)
			cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
		if (tlb_type == cheetah_plus) {
			unsigned long impl, ver;

			__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
			impl = ((ver >> 32) & 0xffff);
			if (impl == PANTHER_IMPL)
				cap |= AV_SPARC_POPC;
		}
		if (tlb_type == hypervisor) {
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
				cap |= AV_SPARC_ASI_BLK_INIT;
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
					AV_SPARC_ASI_BLK_INIT |
					AV_SPARC_POPC);
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M8 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_SN ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
					AV_SPARC_FMAF);
		}
	}
	sparc64_elf_hwcap = cap | mdesc_caps;

	report_hwcaps(sparc64_elf_hwcap);

	if (sparc64_elf_hwcap & AV_SPARC_POPC)
		popc_patch();
	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
		pause_patch();
}

void __init alloc_irqstack_bootmem(void)
{
	unsigned int i, node;

	for_each_possible_cpu(i) {
		node = cpu_to_node(i);

		softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
							THREAD_SIZE,
							THREAD_SIZE, 0);
		hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
							THREAD_SIZE,
							THREAD_SIZE, 0);
	}
}

void __init setup_arch(char **cmdline_p)
{
	/* Initialize PROM console and command line. */
	*cmdline_p = prom_getbootargs();
	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
	parse_early_param();

	boot_flags_init(*cmdline_p);
#ifdef CONFIG_EARLYFB
	if (btext_find_display())
#endif
		register_console(&prom_early_console);

	if (tlb_type == hypervisor)
		printk("ARCH: SUN4V\n");
	else
		printk("ARCH: SUN4U\n");

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	idprom_init();

	if (!root_flags)
		root_mountflags &= ~MS_RDONLY;
	ROOT_DEV = old_decode_dev(root_dev);
#ifdef CONFIG_BLK_DEV_RAM
	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
#endif

	task_thread_info(&init_task)->kregs = &fake_swapper_regs;

#ifdef CONFIG_IP_PNP
	if (!ic_set_manually) {
		phandle chosen = prom_finddevice("/chosen");
		u32 cl, sv, gw;

		cl = prom_getintdefault (chosen, "client-ip", 0);
		sv = prom_getintdefault (chosen, "server-ip", 0);
		gw = prom_getintdefault (chosen, "gateway-ip", 0);
		if (cl && sv) {
			ic_myaddr = cl;
			ic_servaddr = sv;
			if (gw)
				ic_gateway = gw;
#if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
			ic_proto_enabled = 0;
#endif
		}
	}
#endif

	/* Get boot processor trap_block[] setup.  */
	init_cur_cpu_trap(current_thread_info());

	paging_init();
	init_sparc64_elf_hwcap();
	smp_fill_in_cpu_possible_map();
	/*
	 * Once the OF device tree and MDESC have been setup and nr_cpus has
	 * been parsed, we know the list of possible cpus.  Therefore we can
	 * allocate the IRQ stacks.
	 */
	alloc_irqstack_bootmem();
}

extern int stop_a_enabled;

void sun_do_break(void)
{
	if (!stop_a_enabled)
		return;

	prom_printf("\n");
	flush_user_windows();

	prom_cmdline();
}
EXPORT_SYMBOL(sun_do_break);

int stop_a_enabled = 1;
EXPORT_SYMBOL(stop_a_enabled);
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* linux/arch/sparc64/kernel/setup.c
	3	*
	4	* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
	5	* Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	6	*/
	7
	8	#include <linux/errno.h>
	9	#include <linux/sched.h>
	10	#include <linux/kernel.h>
	11	#include <linux/mm.h>
	12	#include <linux/stddef.h>
	13	#include <linux/unistd.h>
	14	#include <linux/ptrace.h>
1da177e4 LT	15	#include <asm/smp.h>
1da177e4 LT	16	#include <linux/user.h>
894673ee	17	#include <linux/screen_info.h>
1da177e4	18	#include <linux/delay.h>
1da177e4 LT	19	#include <linux/fs.h>
	20	#include <linux/seq_file.h>
	21	#include <linux/syscalls.h>
	22	#include <linux/kdev_t.h>
	23	#include <linux/major.h>
	24	#include <linux/string.h>
	25	#include <linux/init.h>
	26	#include <linux/inet.h>
	27	#include <linux/console.h>
	28	#include <linux/root_dev.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/cpu.h>
	31	#include <linux/initrd.h>
ac85fe8b	32	#include <linux/module.h>
ef3e035c	33	#include <linux/start_kernel.h>
ebb99a4c	34	#include <linux/bootmem.h>
1da177e4	35
1da177e4 LT	36	#include <asm/io.h>
	37	#include <asm/processor.h>
	38	#include <asm/oplib.h>
	39	#include <asm/page.h>
	40	#include <asm/pgtable.h>
	41	#include <asm/idprom.h>
	42	#include <asm/head.h>
	43	#include <asm/starfire.h>
	44	#include <asm/mmu_context.h>
	45	#include <asm/timer.h>
	46	#include <asm/sections.h>
	47	#include <asm/setup.h>
	48	#include <asm/mmu.h>
5cbc3073	49	#include <asm/ns87303.h>
c57ec52f	50	#include <asm/btext.h>
ac85fe8b DM	51	#include <asm/elf.h>
ac85fe8b DM	52	#include <asm/mdesc.h>
d550bbd4	53	#include <asm/cacheflush.h>
ebb99a4c AP	54	#include <asm/dma.h>
ebb99a4c AP	55	#include <asm/irq.h>
1da177e4 LT	56
	57	#ifdef CONFIG_IP_PNP
	58	#include <net/ipconfig.h>
	59	#endif
	60
3d5ae6b6	61	#include "entry.h"
53ae3419	62	#include "kernel.h"
3d5ae6b6	63
5cbc3073 DM	64	/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
	65	* operations in asm/ns87303.h
	66	*/
	67	DEFINE_SPINLOCK(ns87303_lock);
917c3660	68	EXPORT_SYMBOL(ns87303_lock);
5cbc3073	69
1da177e4 LT	70	struct screen_info screen_info = {
	71	0, 0, /* orig-x, orig-y */
	72	0, /* unused */
	73	0, /* orig-video-page */
	74	0, /* orig-video-mode */
	75	128, /* orig-video-cols */
	76	0, 0, 0, /* unused, ega_bx, unused */
	77	54, /* orig-video-lines */
	78	0, /* orig-video-isVGA */
	79	16 /* orig-video-points */
	80	};
	81
1da177e4	82	static void
9ef595d8	83	prom_console_write(struct console con, const char s, unsigned int n)
1da177e4 LT	84	{
	85	prom_write(s, n);
	86	}
	87
1da177e4 LT	88	/* Exported for mm/init.c:paging_init. */
	89	unsigned long cmdline_memory_size = 0;
	90
3c62a2d3 DM	91	static struct console prom_early_console = {
3c62a2d3 DM	92	.name = "earlyprom",
1da177e4	93	.write = prom_console_write,
db9a7fb1	94	.flags = CON_PRINTBUFFER \| CON_BOOT \| CON_ANYTIME,
1da177e4 LT	95	.index = -1,
	96	};
	97
68a79217	98	/*
1da177e4 LT	99	* Process kernel command line switches that are specific to the
	100	* SPARC or that require special low-level processing.
	101	*/
	102	static void __init process_switch(char c)
	103	{
	104	switch (c) {
	105	case 'd':
1da177e4	106	case 's':
1da177e4 LT	107	break;
	108	case 'h':
	109	prom_printf("boot_flags_init: Halt!\n");
	110	prom_halt();
	111	break;
	112	case 'p':
11032c17	113	prom_early_console.flags &= ~CON_BOOT;
1da177e4	114	break;
816242da DM	115	case 'P':
	116	/* Force UltraSPARC-III P-Cache on. */
	117	if (tlb_type != cheetah) {
	118	printk("BOOT: Ignoring P-Cache force option.\n");
	119	break;
	120	}
	121	cheetah_pcache_forced_on = 1;
373d4d09	122	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
816242da DM	123	cheetah_enable_pcache();
	124	break;
	125
1da177e4 LT	126	default:
	127	printk("Unknown boot switch (-%c)\n", c);
	128	break;
	129	}
	130	}
	131
1da177e4 LT	132	static void __init boot_flags_init(char *commands)
	133	{
	134	while (*commands) {
	135	/* Move to the start of the next "argument". */
8c64415c	136	while (*commands == ' ')
1da177e4 LT	137	commands++;
	138
	139	/* Process any command switches, otherwise skip it. */
	140	if (*commands == '\0')
	141	break;
	142	if (*commands == '-') {
	143	commands++;
	144	while (commands && commands != ' ')
	145	process_switch(*commands++);
	146	continue;
	147	}
7c21d533	148	if (!strncmp(commands, "mem=", 4))
	149	cmdline_memory_size = memparse(commands + 4, &commands);
	150
1da177e4 LT	151	while (commands && commands != ' ')
	152	commands++;
	153	}
	154	}
	155
1da177e4 LT	156	extern unsigned short root_flags;
	157	extern unsigned short root_dev;
	158	extern unsigned short ram_flags;
	159	#define RAMDISK_IMAGE_START_MASK 0x07FF
	160	#define RAMDISK_PROMPT_FLAG 0x8000
	161	#define RAMDISK_LOAD_FLAG 0x4000
	162
	163	extern int root_mountflags;
	164
	165	char reboot_command[COMMAND_LINE_SIZE];
	166
	167	static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
	168
ef3e035c	169	static void __init per_cpu_patch(void)
92704a1c	170	{
92704a1c DM	171	struct cpuid_patch_entry *p;
	172	unsigned long ver;
	173	int is_jbus;
	174
	175	if (tlb_type == spitfire && !this_is_starfire)
	176	return;
	177
d82ace7d DM	178	is_jbus = 0;
	179	if (tlb_type != hypervisor) {
	180	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
ebd8c56c DM	181	is_jbus = ((ver >> 32UL) == __JALAPENO_ID \|\|
ebd8c56c DM	182	(ver >> 32UL) == __SERRANO_ID);
d82ace7d	183	}
92704a1c DM	184
	185	p = &__cpuid_patch;
	186	while (p < &__cpuid_patch_end) {
	187	unsigned long addr = p->addr;
	188	unsigned int *insns;
	189
	190	switch (tlb_type) {
	191	case spitfire:
	192	insns = &p->starfire[0];
	193	break;
	194	case cheetah:
	195	case cheetah_plus:
	196	if (is_jbus)
	197	insns = &p->cheetah_jbus[0];
	198	else
	199	insns = &p->cheetah_safari[0];
	200	break;
d96b8153 DM	201	case hypervisor:
	202	insns = &p->sun4v[0];
	203	break;
92704a1c DM	204	default:
	205	prom_printf("Unknown cpu type, halting.\n");
	206	prom_halt();
6cb79b3f	207	}
92704a1c DM	208
92704a1c DM	209	(unsigned int ) (addr + 0) = insns[0];
840aaef8	210	wmb();
92704a1c DM	211	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
	212
	213	(unsigned int ) (addr + 4) = insns[1];
840aaef8	214	wmb();
92704a1c DM	215	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
	216
	217	(unsigned int ) (addr + 8) = insns[2];
840aaef8	218	wmb();
92704a1c DM	219	__asm__ __volatile__("flush %0" : : "r" (addr + 8));
	220
	221	(unsigned int ) (addr + 12) = insns[3];
840aaef8	222	wmb();
92704a1c DM	223	__asm__ __volatile__("flush %0" : : "r" (addr + 12));
	224
	225	p++;
	226	}
92704a1c DM	227	}
92704a1c DM	228
0b64120c DM	229	void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
0b64120c DM	230	struct sun4v_1insn_patch_entry *end)
936f482a	231	{
0b64120c DM	232	while (start < end) {
0b64120c DM	233	unsigned long addr = start->addr;
936f482a	234
0b64120c	235	(unsigned int ) (addr + 0) = start->insn;
840aaef8	236	wmb();
936f482a DM	237	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
936f482a DM	238
0b64120c	239	start++;
45fec05f	240	}
0b64120c	241	}
45fec05f	242
0b64120c DM	243	void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
	244	struct sun4v_2insn_patch_entry *end)
	245	{
	246	while (start < end) {
	247	unsigned long addr = start->addr;
45fec05f	248
0b64120c	249	(unsigned int ) (addr + 0) = start->insns[0];
840aaef8	250	wmb();
45fec05f DM	251	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
45fec05f DM	252
0b64120c	253	(unsigned int ) (addr + 4) = start->insns[1];
840aaef8	254	wmb();
45fec05f DM	255	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
45fec05f DM	256
0b64120c	257	start++;
936f482a	258	}
0b64120c DM	259	}
0b64120c DM	260
494e5b6f KA	261	void sun_m7_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
	262	struct sun4v_2insn_patch_entry *end)
	263	{
	264	while (start < end) {
	265	unsigned long addr = start->addr;
	266
	267	(unsigned int ) (addr + 0) = start->insns[0];
	268	wmb();
	269	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
	270
	271	(unsigned int ) (addr + 4) = start->insns[1];
	272	wmb();
	273	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
	274
	275	start++;
	276	}
	277	}
	278
ef3e035c	279	static void __init sun4v_patch(void)
0b64120c DM	280	{
	281	extern void sun4v_hvapi_init(void);
	282
	283	if (tlb_type != hypervisor)
	284	return;
	285
	286	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
	287	&__sun4v_1insn_patch_end);
	288
	289	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
	290	&__sun4v_2insn_patch_end);
7d484acb AP	291
	292	switch (sun4v_chip_type) {
	293	case SUN4V_CHIP_SPARC_M7:
	294	case SUN4V_CHIP_SPARC_M8:
	295	case SUN4V_CHIP_SPARC_SN:
494e5b6f KA	296	sun_m7_patch_2insn_range(&__sun_m7_2insn_patch,
494e5b6f KA	297	&__sun_m7_2insn_patch_end);
7d484acb AP	298	break;
	299	default:
	300	break;
	301	}
c7754d46 DM	302
c7754d46 DM	303	sun4v_hvapi_init();
936f482a DM	304	}
936f482a DM	305
ef7c4d46 DM	306	static void __init popc_patch(void)
	307	{
	308	struct popc_3insn_patch_entry *p3;
56d205cc	309	struct popc_6insn_patch_entry *p6;
ef7c4d46 DM	310
	311	p3 = &__popc_3insn_patch;
	312	while (p3 < &__popc_3insn_patch_end) {
56d205cc	313	unsigned long i, addr = p3->addr;
ef7c4d46	314
56d205cc DM	315	for (i = 0; i < 3; i++) {
	316	(unsigned int ) (addr + (i * 4)) = p3->insns[i];
	317	wmb();
	318	__asm__ __volatile__("flush %0"
	319	: : "r" (addr + (i * 4)));
	320	}
ef7c4d46	321
56d205cc DM	322	p3++;
56d205cc DM	323	}
ef7c4d46	324
56d205cc DM	325	p6 = &__popc_6insn_patch;
	326	while (p6 < &__popc_6insn_patch_end) {
	327	unsigned long i, addr = p6->addr;
ef7c4d46	328
56d205cc DM	329	for (i = 0; i < 6; i++) {
	330	(unsigned int ) (addr + (i * 4)) = p6->insns[i];
	331	wmb();
	332	__asm__ __volatile__("flush %0"
	333	: : "r" (addr + (i * 4)));
	334	}
	335
	336	p6++;
ef7c4d46 DM	337	}
	338	}
	339
e9b9eb59 DM	340	static void __init pause_patch(void)
	341	{
	342	struct pause_patch_entry *p;
	343
187818cd DM	344	p = &__pause_3insn_patch;
187818cd DM	345	while (p < &__pause_3insn_patch_end) {
e9b9eb59 DM	346	unsigned long i, addr = p->addr;
	347
	348	for (i = 0; i < 3; i++) {
	349	(unsigned int ) (addr + (i * 4)) = p->insns[i];
	350	wmb();
	351	__asm__ __volatile__("flush %0"
	352	: : "r" (addr + (i * 4)));
	353	}
	354
	355	p++;
	356	}
	357	}
	358
ef3e035c	359	void __init start_early_boot(void)
951bc82c	360	{
ef3e035c DM	361	int cpu;
	362
	363	check_if_starfire();
	364	per_cpu_patch();
	365	sun4v_patch();
	366
	367	cpu = hard_smp_processor_id();
	368	if (cpu >= NR_CPUS) {
	369	prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
	370	cpu, NR_CPUS);
	371	prom_halt();
	372	}
	373	current_thread_info()->cpu = cpu;
	374
83e8eb99	375	time_init_early();
ef3e035c DM	376	prom_init_report();
ef3e035c DM	377	start_kernel();
951bc82c	378	}
951bc82c	379
ac85fe8b DM	380	/* On Ultra, we support all of the v8 capabilities. */
	381	unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH \| HWCAP_SPARC_STBAR \|
	382	HWCAP_SPARC_SWAP \| HWCAP_SPARC_MULDIV \|
	383	HWCAP_SPARC_V9);
	384	EXPORT_SYMBOL(sparc64_elf_hwcap);
	385
	386	static const char *hwcaps[] = {
	387	"flush", "stbar", "swap", "muldiv", "v9",
	388	"ultra3", "blkinit", "n2",
	389
	390	/* These strings are as they appear in the machine description
	391	* 'hwcap-list' property for cpu nodes.
	392	*/
	393	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	394	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
82924e54 KA	395	"ima", "cspare", "pause", "cbcond", NULL /reserved for crypto /,
82924e54 KA	396	"adp",
6f859c0e DM	397	};
	398
	399	static const char *crypto_hwcaps[] = {
	400	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	401	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
ac85fe8b DM	402	};
	403
	404	void cpucap_info(struct seq_file *m)
	405	{
	406	unsigned long caps = sparc64_elf_hwcap;
	407	int i, printed = 0;
	408
	409	seq_puts(m, "cpucaps\t\t: ");
	410	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	411	unsigned long bit = 1UL << i;
82924e54	412	if (hwcaps[i] && (caps & bit)) {
ac85fe8b DM	413	seq_printf(m, "%s%s",
	414	printed ? "," : "", hwcaps[i]);
	415	printed++;
	416	}
	417	}
6f859c0e DM	418	if (caps & HWCAP_SPARC_CRYPTO) {
	419	unsigned long cfr;
	420
	421	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	422	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	423	unsigned long bit = 1UL << i;
	424	if (cfr & bit) {
	425	seq_printf(m, "%s%s",
	426	printed ? "," : "", crypto_hwcaps[i]);
	427	printed++;
	428	}
	429	}
	430	}
ac85fe8b DM	431	seq_putc(m, '\n');
	432	}
	433
6f859c0e DM	434	static void __init report_one_hwcap(int printed, const char name)
	435	{
	436	if ((*printed) == 0)
	437	printk(KERN_INFO "CPU CAPS: [");
	438	printk(KERN_CONT "%s%s",
	439	(*printed) ? "," : "", name);
	440	if (++(*printed) == 8) {
	441	printk(KERN_CONT "]\n");
	442	*printed = 0;
	443	}
	444	}
	445
	446	static void __init report_crypto_hwcaps(int *printed)
	447	{
	448	unsigned long cfr;
	449	int i;
	450
	451	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	452
	453	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	454	unsigned long bit = 1UL << i;
	455	if (cfr & bit)
	456	report_one_hwcap(printed, crypto_hwcaps[i]);
	457	}
	458	}
	459
ac85fe8b DM	460	static void __init report_hwcaps(unsigned long caps)
	461	{
	462	int i, printed = 0;
	463
ac85fe8b DM	464	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
ac85fe8b DM	465	unsigned long bit = 1UL << i;
82924e54	466	if (hwcaps[i] && (caps & bit))
6f859c0e	467	report_one_hwcap(&printed, hwcaps[i]);
ac85fe8b	468	}
6f859c0e DM	469	if (caps & HWCAP_SPARC_CRYPTO)
	470	report_crypto_hwcaps(&printed);
	471	if (printed != 0)
	472	printk(KERN_CONT "]\n");
ac85fe8b DM	473	}
	474
	475	static unsigned long __init mdesc_cpu_hwcap_list(void)
	476	{
	477	struct mdesc_handle *hp;
	478	unsigned long caps = 0;
	479	const char *prop;
	480	int len;
	481	u64 pn;
	482
	483	hp = mdesc_grab();
	484	if (!hp)
	485	return 0;
	486
	487	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	488	if (pn == MDESC_NODE_NULL)
	489	goto out;
	490
	491	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	492	if (!prop)
	493	goto out;
	494
	495	while (len) {
	496	int i, plen;
	497
	498	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	499	unsigned long bit = 1UL << i;
	500
82924e54	501	if (hwcaps[i] && !strcmp(prop, hwcaps[i])) {
ac85fe8b DM	502	caps \|= bit;
	503	break;
	504	}
	505	}
6f859c0e DM	506	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	507	if (!strcmp(prop, crypto_hwcaps[i]))
	508	caps \|= HWCAP_SPARC_CRYPTO;
	509	}
ac85fe8b DM	510
	511	plen = strlen(prop) + 1;
	512	prop += plen;
	513	len -= plen;
	514	}
	515
	516	out:
	517	mdesc_release(hp);
	518	return caps;
	519	}
	520
	521	/* This yields a mask that user programs can use to figure out what
	522	* instruction set this cpu supports.
	523	*/
	524	static void __init init_sparc64_elf_hwcap(void)
	525	{
	526	unsigned long cap = sparc64_elf_hwcap;
	527	unsigned long mdesc_caps;
	528
	529	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	530	cap \|= HWCAP_SPARC_ULTRA3;
	531	else if (tlb_type == hypervisor) {
	532	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 \|\|
	533	sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	534	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	535	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	536	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	537	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	538	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	539	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	540	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	541	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	542	cap \|= HWCAP_SPARC_BLKINIT;
ac85fe8b DM	543	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	544	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	545	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	546	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	547	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	548	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	549	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	550	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	551	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	552	cap \|= HWCAP_SPARC_N2;
	553	}
	554
	555	cap \|= (AV_SPARC_MUL32 \| AV_SPARC_DIV32 \| AV_SPARC_V8PLUS);
	556
	557	mdesc_caps = mdesc_cpu_hwcap_list();
	558	if (!mdesc_caps) {
	559	if (tlb_type == spitfire)
	560	cap \|= AV_SPARC_VIS;
	561	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	562	cap \|= AV_SPARC_VIS \| AV_SPARC_VIS2;
1a8e0da5 DM	563	if (tlb_type == cheetah_plus) {
	564	unsigned long impl, ver;
	565
	566	__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
	567	impl = ((ver >> 32) & 0xffff);
	568	if (impl == PANTHER_IMPL)
	569	cap \|= AV_SPARC_POPC;
	570	}
ac85fe8b DM	571	if (tlb_type == hypervisor) {
	572	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
	573	cap \|= AV_SPARC_ASI_BLK_INIT;
	574	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	575	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	576	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	577	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	578	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	579	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	580	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	581	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	582	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	583	cap \|= (AV_SPARC_VIS \| AV_SPARC_VIS2 \|
	584	AV_SPARC_ASI_BLK_INIT \|
	585	AV_SPARC_POPC);
08cefa9f DM	586	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	587	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	588	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	589	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	590	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
7d484acb	591	sun4v_chip_type == SUN4V_CHIP_SPARC_M8 \|\|
c5b8b5be	592	sun4v_chip_type == SUN4V_CHIP_SPARC_SN \|\|
4e963779	593	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	594	cap \|= (AV_SPARC_VIS3 \| AV_SPARC_HPC \|
	595	AV_SPARC_FMAF);
	596	}
	597	}
	598	sparc64_elf_hwcap = cap \| mdesc_caps;
	599
	600	report_hwcaps(sparc64_elf_hwcap);
ef7c4d46 DM	601
	602	if (sparc64_elf_hwcap & AV_SPARC_POPC)
	603	popc_patch();
e9b9eb59 DM	604	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
e9b9eb59 DM	605	pause_patch();
ac85fe8b DM	606	}
ac85fe8b DM	607
ebb99a4c AP	608	void __init alloc_irqstack_bootmem(void)
	609	{
	610	unsigned int i, node;
	611
	612	for_each_possible_cpu(i) {
	613	node = cpu_to_node(i);
	614
	615	softirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
	616	THREAD_SIZE,
	617	THREAD_SIZE, 0);
	618	hardirq_stack[i] = __alloc_bootmem_node(NODE_DATA(node),
	619	THREAD_SIZE,
	620	THREAD_SIZE, 0);
	621	}
	622	}
	623
1da177e4 LT	624	void __init setup_arch(char **cmdline_p)
1da177e4 LT	625	{
1da177e4 LT	626	/* Initialize PROM console and command line. */
1da177e4 LT	627	*cmdline_p = prom_getbootargs();
117a0c5f	628	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
ce3b1d47	629	parse_early_param();
1da177e4	630
3c62a2d3	631	boot_flags_init(*cmdline_p);
c57ec52f DM	632	#ifdef CONFIG_EARLYFB
	633	if (btext_find_display())
	634	#endif
	635	register_console(&prom_early_console);
3c62a2d3	636
3a8c069d DM	637	if (tlb_type == hypervisor)
	638	printk("ARCH: SUN4V\n");
	639	else
	640	printk("ARCH: SUN4U\n");
1da177e4 LT	641
	642	#ifdef CONFIG_DUMMY_CONSOLE
	643	conswitchp = &dummy_con;
1da177e4 LT	644	#endif
1da177e4 LT	645
1da177e4	646	idprom_init();
1da177e4 LT	647
	648	if (!root_flags)
	649	root_mountflags &= ~MS_RDONLY;
	650	ROOT_DEV = old_decode_dev(root_dev);
467418f3	651	#ifdef CONFIG_BLK_DEV_RAM
1da177e4 LT	652	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
1da177e4 LT	653	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
68a79217	654	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
1da177e4 LT	655	#endif
1da177e4 LT	656
f3169641	657	task_thread_info(&init_task)->kregs = &fake_swapper_regs;
1da177e4 LT	658
	659	#ifdef CONFIG_IP_PNP
	660	if (!ic_set_manually) {
8d125562	661	phandle chosen = prom_finddevice("/chosen");
1da177e4	662	u32 cl, sv, gw;
68a79217	663
1da177e4 LT	664	cl = prom_getintdefault (chosen, "client-ip", 0);
	665	sv = prom_getintdefault (chosen, "server-ip", 0);
	666	gw = prom_getintdefault (chosen, "gateway-ip", 0);
	667	if (cl && sv) {
	668	ic_myaddr = cl;
	669	ic_servaddr = sv;
	670	if (gw)
	671	ic_gateway = gw;
	672	#if defined(CONFIG_IP_PNP_BOOTP) \|\| defined(CONFIG_IP_PNP_RARP)
	673	ic_proto_enabled = 0;
	674	#endif
	675	}
	676	}
	677	#endif
	678
56fb4df6	679	/* Get boot processor trap_block[] setup. */
72aff53f	680	init_cur_cpu_trap(current_thread_info());
52845cdb DM	681
52845cdb DM	682	paging_init();
ac85fe8b	683	init_sparc64_elf_hwcap();
9b2f753e	684	smp_fill_in_cpu_possible_map();
ebb99a4c AP	685	/*
	686	* Once the OF device tree and MDESC have been setup and nr_cpus has
	687	* been parsed, we know the list of possible cpus. Therefore we can
	688	* allocate the IRQ stacks.
	689	*/
	690	alloc_irqstack_bootmem();
1da177e4 LT	691	}
1da177e4 LT	692
1da177e4 LT	693	extern int stop_a_enabled;
	694
	695	void sun_do_break(void)
	696	{
	697	if (!stop_a_enabled)
	698	return;
	699
	700	prom_printf("\n");
	701	flush_user_windows();
	702
	703	prom_cmdline();
	704	}
917c3660	705	EXPORT_SYMBOL(sun_do_break);
1da177e4	706
1da177e4	707	int stop_a_enabled = 1;
917c3660	708	EXPORT_SYMBOL(stop_a_enabled);