[mirror_ubuntu-artful-kernel.git] / arch / sparc / kernel / setup_64.c

/*
 *  linux/arch/sparc64/kernel/setup.c
 *
 *  Copyright (C) 1995,1996  David S. Miller (davem@caip.rutgers.edu)
 *  Copyright (C) 1997       Jakub Jelinek (jj@sunsite.mff.cuni.cz)
 */

#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/stddef.h>
#include <linux/unistd.h>
#include <linux/ptrace.h>
#include <asm/smp.h>
#include <linux/user.h>
#include <linux/screen_info.h>
#include <linux/delay.h>
#include <linux/fs.h>
#include <linux/seq_file.h>
#include <linux/syscalls.h>
#include <linux/kdev_t.h>
#include <linux/major.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/inet.h>
#include <linux/console.h>
#include <linux/root_dev.h>
#include <linux/interrupt.h>
#include <linux/cpu.h>
#include <linux/initrd.h>
#include <linux/module.h>
#include <linux/start_kernel.h>

#include <asm/io.h>
#include <asm/processor.h>
#include <asm/oplib.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/idprom.h>
#include <asm/head.h>
#include <asm/starfire.h>
#include <asm/mmu_context.h>
#include <asm/timer.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/mmu.h>
#include <asm/ns87303.h>
#include <asm/btext.h>
#include <asm/elf.h>
#include <asm/mdesc.h>
#include <asm/cacheflush.h>

#ifdef CONFIG_IP_PNP
#include <net/ipconfig.h>
#endif

#include "entry.h"
#include "kernel.h"

/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
 * operations in asm/ns87303.h
 */
DEFINE_SPINLOCK(ns87303_lock);
EXPORT_SYMBOL(ns87303_lock);

struct screen_info screen_info = {
	0, 0,			/* orig-x, orig-y */
	0,			/* unused */
	0,			/* orig-video-page */
	0,			/* orig-video-mode */
	128,			/* orig-video-cols */
	0, 0, 0,		/* unused, ega_bx, unused */
	54,			/* orig-video-lines */
	0,                      /* orig-video-isVGA */
	16                      /* orig-video-points */
};

static void
prom_console_write(struct console *con, const char *s, unsigned n)
{
	prom_write(s, n);
}

/* Exported for mm/init.c:paging_init. */
unsigned long cmdline_memory_size = 0;

static struct console prom_early_console = {
	.name =		"earlyprom",
	.write =	prom_console_write,
	.flags =	CON_PRINTBUFFER | CON_BOOT | CON_ANYTIME,
	.index =	-1,
};

/* 
 * Process kernel command line switches that are specific to the
 * SPARC or that require special low-level processing.
 */
static void __init process_switch(char c)
{
	switch (c) {
	case 'd':
	case 's':
		break;
	case 'h':
		prom_printf("boot_flags_init: Halt!\n");
		prom_halt();
		break;
	case 'p':
		prom_early_console.flags &= ~CON_BOOT;
		break;
	case 'P':
		/* Force UltraSPARC-III P-Cache on. */
		if (tlb_type != cheetah) {
			printk("BOOT: Ignoring P-Cache force option.\n");
			break;
		}
		cheetah_pcache_forced_on = 1;
		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
		cheetah_enable_pcache();
		break;

	default:
		printk("Unknown boot switch (-%c)\n", c);
		break;
	}
}

static void __init boot_flags_init(char *commands)
{
	while (*commands) {
		/* Move to the start of the next "argument". */
		while (*commands && *commands == ' ')
			commands++;

		/* Process any command switches, otherwise skip it. */
		if (*commands == '\0')
			break;
		if (*commands == '-') {
			commands++;
			while (*commands && *commands != ' ')
				process_switch(*commands++);
			continue;
		}
		if (!strncmp(commands, "mem=", 4))
			cmdline_memory_size = memparse(commands + 4, &commands);

		while (*commands && *commands != ' ')
			commands++;
	}
}

extern unsigned short root_flags;
extern unsigned short root_dev;
extern unsigned short ram_flags;
#define RAMDISK_IMAGE_START_MASK	0x07FF
#define RAMDISK_PROMPT_FLAG		0x8000
#define RAMDISK_LOAD_FLAG		0x4000

extern int root_mountflags;

char reboot_command[COMMAND_LINE_SIZE];

static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };

static void __init per_cpu_patch(void)
{
	struct cpuid_patch_entry *p;
	unsigned long ver;
	int is_jbus;

	if (tlb_type == spitfire && !this_is_starfire)
		return;

	is_jbus = 0;
	if (tlb_type != hypervisor) {
		__asm__ ("rdpr %%ver, %0" : "=r" (ver));
		is_jbus = ((ver >> 32UL) == __JALAPENO_ID ||
			   (ver >> 32UL) == __SERRANO_ID);
	}

	p = &__cpuid_patch;
	while (p < &__cpuid_patch_end) {
		unsigned long addr = p->addr;
		unsigned int *insns;

		switch (tlb_type) {
		case spitfire:
			insns = &p->starfire[0];
			break;
		case cheetah:
		case cheetah_plus:
			if (is_jbus)
				insns = &p->cheetah_jbus[0];
			else
				insns = &p->cheetah_safari[0];
			break;
		case hypervisor:
			insns = &p->sun4v[0];
			break;
		default:
			prom_printf("Unknown cpu type, halting.\n");
			prom_halt();
		}

		*(unsigned int *) (addr +  0) = insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		*(unsigned int *) (addr +  8) = insns[2];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  8));

		*(unsigned int *) (addr + 12) = insns[3];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr + 12));

		p++;
	}
}

void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
			     struct sun4v_1insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insn;
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		start++;
	}
}

void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
			     struct sun4v_2insn_patch_entry *end)
{
	while (start < end) {
		unsigned long addr = start->addr;

		*(unsigned int *) (addr +  0) = start->insns[0];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  0));

		*(unsigned int *) (addr +  4) = start->insns[1];
		wmb();
		__asm__ __volatile__("flush	%0" : : "r" (addr +  4));

		start++;
	}
}

static void __init sun4v_patch(void)
{
	extern void sun4v_hvapi_init(void);

	if (tlb_type != hypervisor)
		return;

	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
				&__sun4v_1insn_patch_end);

	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
				&__sun4v_2insn_patch_end);

	sun4v_hvapi_init();
}

static void __init popc_patch(void)
{
	struct popc_3insn_patch_entry *p3;
	struct popc_6insn_patch_entry *p6;

	p3 = &__popc_3insn_patch;
	while (p3 < &__popc_3insn_patch_end) {
		unsigned long i, addr = p3->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p3->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p3++;
	}

	p6 = &__popc_6insn_patch;
	while (p6 < &__popc_6insn_patch_end) {
		unsigned long i, addr = p6->addr;

		for (i = 0; i < 6; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p6->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p6++;
	}
}

static void __init pause_patch(void)
{
	struct pause_patch_entry *p;

	p = &__pause_3insn_patch;
	while (p < &__pause_3insn_patch_end) {
		unsigned long i, addr = p->addr;

		for (i = 0; i < 3; i++) {
			*(unsigned int *) (addr +  (i * 4)) = p->insns[i];
			wmb();
			__asm__ __volatile__("flush	%0"
					     : : "r" (addr +  (i * 4)));
		}

		p++;
	}
}

void __init start_early_boot(void)
{
	int cpu;

	check_if_starfire();
	per_cpu_patch();
	sun4v_patch();

	cpu = hard_smp_processor_id();
	if (cpu >= NR_CPUS) {
		prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
			    cpu, NR_CPUS);
		prom_halt();
	}
	current_thread_info()->cpu = cpu;

	prom_init_report();
	start_kernel();
}

/* On Ultra, we support all of the v8 capabilities. */
unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR |
				   HWCAP_SPARC_SWAP | HWCAP_SPARC_MULDIV |
				   HWCAP_SPARC_V9);
EXPORT_SYMBOL(sparc64_elf_hwcap);

static const char *hwcaps[] = {
	"flush", "stbar", "swap", "muldiv", "v9",
	"ultra3", "blkinit", "n2",

	/* These strings are as they appear in the machine description
	 * 'hwcap-list' property for cpu nodes.
	 */
	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
	"ima", "cspare", "pause", "cbcond",
};

static const char *crypto_hwcaps[] = {
	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
};

void cpucap_info(struct seq_file *m)
{
	unsigned long caps = sparc64_elf_hwcap;
	int i, printed = 0;

	seq_puts(m, "cpucaps\t\t: ");
	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (caps & bit) {
			seq_printf(m, "%s%s",
				   printed ? "," : "", hwcaps[i]);
			printed++;
		}
	}
	if (caps & HWCAP_SPARC_CRYPTO) {
		unsigned long cfr;

		__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			unsigned long bit = 1UL << i;
			if (cfr & bit) {
				seq_printf(m, "%s%s",
					   printed ? "," : "", crypto_hwcaps[i]);
				printed++;
			}
		}
	}
	seq_putc(m, '\n');
}

static void __init report_one_hwcap(int *printed, const char *name)
{
	if ((*printed) == 0)
		printk(KERN_INFO "CPU CAPS: [");
	printk(KERN_CONT "%s%s",
	       (*printed) ? "," : "", name);
	if (++(*printed) == 8) {
		printk(KERN_CONT "]\n");
		*printed = 0;
	}
}

static void __init report_crypto_hwcaps(int *printed)
{
	unsigned long cfr;
	int i;

	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));

	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (cfr & bit)
			report_one_hwcap(printed, crypto_hwcaps[i]);
	}
}

static void __init report_hwcaps(unsigned long caps)
{
	int i, printed = 0;

	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
		unsigned long bit = 1UL << i;
		if (caps & bit)
			report_one_hwcap(&printed, hwcaps[i]);
	}
	if (caps & HWCAP_SPARC_CRYPTO)
		report_crypto_hwcaps(&printed);
	if (printed != 0)
		printk(KERN_CONT "]\n");
}

static unsigned long __init mdesc_cpu_hwcap_list(void)
{
	struct mdesc_handle *hp;
	unsigned long caps = 0;
	const char *prop;
	int len;
	u64 pn;

	hp = mdesc_grab();
	if (!hp)
		return 0;

	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	if (pn == MDESC_NODE_NULL)
		goto out;

	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	if (!prop)
		goto out;

	while (len) {
		int i, plen;

		for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
			unsigned long bit = 1UL << i;

			if (!strcmp(prop, hwcaps[i])) {
				caps |= bit;
				break;
			}
		}
		for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
			if (!strcmp(prop, crypto_hwcaps[i]))
				caps |= HWCAP_SPARC_CRYPTO;
		}

		plen = strlen(prop) + 1;
		prop += plen;
		len -= plen;
	}

out:
	mdesc_release(hp);
	return caps;
}

/* This yields a mask that user programs can use to figure out what
 * instruction set this cpu supports.
 */
static void __init init_sparc64_elf_hwcap(void)
{
	unsigned long cap = sparc64_elf_hwcap;
	unsigned long mdesc_caps;

	if (tlb_type == cheetah || tlb_type == cheetah_plus)
		cap |= HWCAP_SPARC_ULTRA3;
	else if (tlb_type == hypervisor) {
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_BLKINIT;
		if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
		    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
		    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
			cap |= HWCAP_SPARC_N2;
	}

	cap |= (AV_SPARC_MUL32 | AV_SPARC_DIV32 | AV_SPARC_V8PLUS);

	mdesc_caps = mdesc_cpu_hwcap_list();
	if (!mdesc_caps) {
		if (tlb_type == spitfire)
			cap |= AV_SPARC_VIS;
		if (tlb_type == cheetah || tlb_type == cheetah_plus)
			cap |= AV_SPARC_VIS | AV_SPARC_VIS2;
		if (tlb_type == cheetah_plus) {
			unsigned long impl, ver;

			__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
			impl = ((ver >> 32) & 0xffff);
			if (impl == PANTHER_IMPL)
				cap |= AV_SPARC_POPC;
		}
		if (tlb_type == hypervisor) {
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
				cap |= AV_SPARC_ASI_BLK_INIT;
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS | AV_SPARC_VIS2 |
					AV_SPARC_ASI_BLK_INIT |
					AV_SPARC_POPC);
			if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||
			    sun4v_chip_type == SUN4V_CHIP_NIAGARA5 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M6 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC_M7 ||
			    sun4v_chip_type == SUN4V_CHIP_SPARC64X)
				cap |= (AV_SPARC_VIS3 | AV_SPARC_HPC |
					AV_SPARC_FMAF);
		}
	}
	sparc64_elf_hwcap = cap | mdesc_caps;

	report_hwcaps(sparc64_elf_hwcap);

	if (sparc64_elf_hwcap & AV_SPARC_POPC)
		popc_patch();
	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
		pause_patch();
}

void __init setup_arch(char **cmdline_p)
{
	/* Initialize PROM console and command line. */
	*cmdline_p = prom_getbootargs();
	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
	parse_early_param();

	boot_flags_init(*cmdline_p);
#ifdef CONFIG_EARLYFB
	if (btext_find_display())
#endif
		register_console(&prom_early_console);

	if (tlb_type == hypervisor)
		printk("ARCH: SUN4V\n");
	else
		printk("ARCH: SUN4U\n");

#ifdef CONFIG_DUMMY_CONSOLE
	conswitchp = &dummy_con;
#endif

	idprom_init();

	if (!root_flags)
		root_mountflags &= ~MS_RDONLY;
	ROOT_DEV = old_decode_dev(root_dev);
#ifdef CONFIG_BLK_DEV_RAM
	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);	
#endif

	task_thread_info(&init_task)->kregs = &fake_swapper_regs;

#ifdef CONFIG_IP_PNP
	if (!ic_set_manually) {
		phandle chosen = prom_finddevice("/chosen");
		u32 cl, sv, gw;
		
		cl = prom_getintdefault (chosen, "client-ip", 0);
		sv = prom_getintdefault (chosen, "server-ip", 0);
		gw = prom_getintdefault (chosen, "gateway-ip", 0);
		if (cl && sv) {
			ic_myaddr = cl;
			ic_servaddr = sv;
			if (gw)
				ic_gateway = gw;
#if defined(CONFIG_IP_PNP_BOOTP) || defined(CONFIG_IP_PNP_RARP)
			ic_proto_enabled = 0;
#endif
		}
	}
#endif

	/* Get boot processor trap_block[] setup.  */
	init_cur_cpu_trap(current_thread_info());

	paging_init();
	init_sparc64_elf_hwcap();
}

extern int stop_a_enabled;

void sun_do_break(void)
{
	if (!stop_a_enabled)
		return;

	prom_printf("\n");
	flush_user_windows();

	prom_cmdline();
}
EXPORT_SYMBOL(sun_do_break);

int stop_a_enabled = 1;
EXPORT_SYMBOL(stop_a_enabled);
Commit	Line	Data
b00dc837	1	/*
1da177e4 LT	2	* linux/arch/sparc64/kernel/setup.c
	3	*
	4	* Copyright (C) 1995,1996 David S. Miller (davem@caip.rutgers.edu)
	5	* Copyright (C) 1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
	6	*/
	7
	8	#include <linux/errno.h>
	9	#include <linux/sched.h>
	10	#include <linux/kernel.h>
	11	#include <linux/mm.h>
	12	#include <linux/stddef.h>
	13	#include <linux/unistd.h>
	14	#include <linux/ptrace.h>
1da177e4 LT	15	#include <asm/smp.h>
1da177e4 LT	16	#include <linux/user.h>
894673ee	17	#include <linux/screen_info.h>
1da177e4	18	#include <linux/delay.h>
1da177e4 LT	19	#include <linux/fs.h>
	20	#include <linux/seq_file.h>
	21	#include <linux/syscalls.h>
	22	#include <linux/kdev_t.h>
	23	#include <linux/major.h>
	24	#include <linux/string.h>
	25	#include <linux/init.h>
	26	#include <linux/inet.h>
	27	#include <linux/console.h>
	28	#include <linux/root_dev.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/cpu.h>
	31	#include <linux/initrd.h>
ac85fe8b	32	#include <linux/module.h>
ef3e035c	33	#include <linux/start_kernel.h>
1da177e4	34
1da177e4 LT	35	#include <asm/io.h>
	36	#include <asm/processor.h>
	37	#include <asm/oplib.h>
	38	#include <asm/page.h>
	39	#include <asm/pgtable.h>
	40	#include <asm/idprom.h>
	41	#include <asm/head.h>
	42	#include <asm/starfire.h>
	43	#include <asm/mmu_context.h>
	44	#include <asm/timer.h>
	45	#include <asm/sections.h>
	46	#include <asm/setup.h>
	47	#include <asm/mmu.h>
5cbc3073	48	#include <asm/ns87303.h>
c57ec52f	49	#include <asm/btext.h>
ac85fe8b DM	50	#include <asm/elf.h>
ac85fe8b DM	51	#include <asm/mdesc.h>
d550bbd4	52	#include <asm/cacheflush.h>
1da177e4 LT	53
	54	#ifdef CONFIG_IP_PNP
	55	#include <net/ipconfig.h>
	56	#endif
	57
3d5ae6b6	58	#include "entry.h"
53ae3419	59	#include "kernel.h"
3d5ae6b6	60
5cbc3073 DM	61	/* Used to synchronize accesses to NatSemi SUPER I/O chip configure
	62	* operations in asm/ns87303.h
	63	*/
	64	DEFINE_SPINLOCK(ns87303_lock);
917c3660	65	EXPORT_SYMBOL(ns87303_lock);
5cbc3073	66
1da177e4 LT	67	struct screen_info screen_info = {
	68	0, 0, /* orig-x, orig-y */
	69	0, /* unused */
	70	0, /* orig-video-page */
	71	0, /* orig-video-mode */
	72	128, /* orig-video-cols */
	73	0, 0, 0, /* unused, ega_bx, unused */
	74	54, /* orig-video-lines */
	75	0, /* orig-video-isVGA */
	76	16 /* orig-video-points */
	77	};
	78
1da177e4 LT	79	static void
	80	prom_console_write(struct console con, const char s, unsigned n)
	81	{
	82	prom_write(s, n);
	83	}
	84
1da177e4 LT	85	/* Exported for mm/init.c:paging_init. */
	86	unsigned long cmdline_memory_size = 0;
	87
3c62a2d3 DM	88	static struct console prom_early_console = {
3c62a2d3 DM	89	.name = "earlyprom",
1da177e4	90	.write = prom_console_write,
db9a7fb1	91	.flags = CON_PRINTBUFFER \| CON_BOOT \| CON_ANYTIME,
1da177e4 LT	92	.index = -1,
	93	};
	94
1da177e4 LT	95	/*
	96	* Process kernel command line switches that are specific to the
	97	* SPARC or that require special low-level processing.
	98	*/
	99	static void __init process_switch(char c)
	100	{
	101	switch (c) {
	102	case 'd':
1da177e4	103	case 's':
1da177e4 LT	104	break;
	105	case 'h':
	106	prom_printf("boot_flags_init: Halt!\n");
	107	prom_halt();
	108	break;
	109	case 'p':
11032c17	110	prom_early_console.flags &= ~CON_BOOT;
1da177e4	111	break;
816242da DM	112	case 'P':
	113	/* Force UltraSPARC-III P-Cache on. */
	114	if (tlb_type != cheetah) {
	115	printk("BOOT: Ignoring P-Cache force option.\n");
	116	break;
	117	}
	118	cheetah_pcache_forced_on = 1;
373d4d09	119	add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
816242da DM	120	cheetah_enable_pcache();
	121	break;
	122
1da177e4 LT	123	default:
	124	printk("Unknown boot switch (-%c)\n", c);
	125	break;
	126	}
	127	}
	128
1da177e4 LT	129	static void __init boot_flags_init(char *commands)
	130	{
	131	while (*commands) {
	132	/* Move to the start of the next "argument". */
	133	while (commands && commands == ' ')
	134	commands++;
	135
	136	/* Process any command switches, otherwise skip it. */
	137	if (*commands == '\0')
	138	break;
	139	if (*commands == '-') {
	140	commands++;
	141	while (commands && commands != ' ')
	142	process_switch(*commands++);
	143	continue;
	144	}
7c21d533	145	if (!strncmp(commands, "mem=", 4))
	146	cmdline_memory_size = memparse(commands + 4, &commands);
	147
1da177e4 LT	148	while (commands && commands != ' ')
	149	commands++;
	150	}
	151	}
	152
1da177e4 LT	153	extern unsigned short root_flags;
	154	extern unsigned short root_dev;
	155	extern unsigned short ram_flags;
	156	#define RAMDISK_IMAGE_START_MASK 0x07FF
	157	#define RAMDISK_PROMPT_FLAG 0x8000
	158	#define RAMDISK_LOAD_FLAG 0x4000
	159
	160	extern int root_mountflags;
	161
	162	char reboot_command[COMMAND_LINE_SIZE];
	163
	164	static struct pt_regs fake_swapper_regs = { { 0, }, 0, 0, 0, 0 };
	165
ef3e035c	166	static void __init per_cpu_patch(void)
92704a1c	167	{
92704a1c DM	168	struct cpuid_patch_entry *p;
	169	unsigned long ver;
	170	int is_jbus;
	171
	172	if (tlb_type == spitfire && !this_is_starfire)
	173	return;
	174
d82ace7d DM	175	is_jbus = 0;
	176	if (tlb_type != hypervisor) {
	177	__asm__ ("rdpr %%ver, %0" : "=r" (ver));
ebd8c56c DM	178	is_jbus = ((ver >> 32UL) == __JALAPENO_ID \|\|
ebd8c56c DM	179	(ver >> 32UL) == __SERRANO_ID);
d82ace7d	180	}
92704a1c DM	181
	182	p = &__cpuid_patch;
	183	while (p < &__cpuid_patch_end) {
	184	unsigned long addr = p->addr;
	185	unsigned int *insns;
	186
	187	switch (tlb_type) {
	188	case spitfire:
	189	insns = &p->starfire[0];
	190	break;
	191	case cheetah:
	192	case cheetah_plus:
	193	if (is_jbus)
	194	insns = &p->cheetah_jbus[0];
	195	else
	196	insns = &p->cheetah_safari[0];
	197	break;
d96b8153 DM	198	case hypervisor:
	199	insns = &p->sun4v[0];
	200	break;
92704a1c DM	201	default:
	202	prom_printf("Unknown cpu type, halting.\n");
	203	prom_halt();
6cb79b3f	204	}
92704a1c DM	205
92704a1c DM	206	(unsigned int ) (addr + 0) = insns[0];
840aaef8	207	wmb();
92704a1c DM	208	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
	209
	210	(unsigned int ) (addr + 4) = insns[1];
840aaef8	211	wmb();
92704a1c DM	212	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
	213
	214	(unsigned int ) (addr + 8) = insns[2];
840aaef8	215	wmb();
92704a1c DM	216	__asm__ __volatile__("flush %0" : : "r" (addr + 8));
	217
	218	(unsigned int ) (addr + 12) = insns[3];
840aaef8	219	wmb();
92704a1c DM	220	__asm__ __volatile__("flush %0" : : "r" (addr + 12));
	221
	222	p++;
	223	}
92704a1c DM	224	}
92704a1c DM	225
0b64120c DM	226	void sun4v_patch_1insn_range(struct sun4v_1insn_patch_entry *start,
0b64120c DM	227	struct sun4v_1insn_patch_entry *end)
936f482a	228	{
0b64120c DM	229	while (start < end) {
0b64120c DM	230	unsigned long addr = start->addr;
936f482a	231
0b64120c	232	(unsigned int ) (addr + 0) = start->insn;
840aaef8	233	wmb();
936f482a DM	234	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
936f482a DM	235
0b64120c	236	start++;
45fec05f	237	}
0b64120c	238	}
45fec05f	239
0b64120c DM	240	void sun4v_patch_2insn_range(struct sun4v_2insn_patch_entry *start,
	241	struct sun4v_2insn_patch_entry *end)
	242	{
	243	while (start < end) {
	244	unsigned long addr = start->addr;
45fec05f	245
0b64120c	246	(unsigned int ) (addr + 0) = start->insns[0];
840aaef8	247	wmb();
45fec05f DM	248	__asm__ __volatile__("flush %0" : : "r" (addr + 0));
45fec05f DM	249
0b64120c	250	(unsigned int ) (addr + 4) = start->insns[1];
840aaef8	251	wmb();
45fec05f DM	252	__asm__ __volatile__("flush %0" : : "r" (addr + 4));
45fec05f DM	253
0b64120c	254	start++;
936f482a	255	}
0b64120c DM	256	}
0b64120c DM	257
ef3e035c	258	static void __init sun4v_patch(void)
0b64120c DM	259	{
	260	extern void sun4v_hvapi_init(void);
	261
	262	if (tlb_type != hypervisor)
	263	return;
	264
	265	sun4v_patch_1insn_range(&__sun4v_1insn_patch,
	266	&__sun4v_1insn_patch_end);
	267
	268	sun4v_patch_2insn_range(&__sun4v_2insn_patch,
	269	&__sun4v_2insn_patch_end);
c7754d46 DM	270
c7754d46 DM	271	sun4v_hvapi_init();
936f482a DM	272	}
936f482a DM	273
ef7c4d46 DM	274	static void __init popc_patch(void)
	275	{
	276	struct popc_3insn_patch_entry *p3;
56d205cc	277	struct popc_6insn_patch_entry *p6;
ef7c4d46 DM	278
	279	p3 = &__popc_3insn_patch;
	280	while (p3 < &__popc_3insn_patch_end) {
56d205cc	281	unsigned long i, addr = p3->addr;
ef7c4d46	282
56d205cc DM	283	for (i = 0; i < 3; i++) {
	284	(unsigned int ) (addr + (i * 4)) = p3->insns[i];
	285	wmb();
	286	__asm__ __volatile__("flush %0"
	287	: : "r" (addr + (i * 4)));
	288	}
ef7c4d46	289
56d205cc DM	290	p3++;
56d205cc DM	291	}
ef7c4d46	292
56d205cc DM	293	p6 = &__popc_6insn_patch;
	294	while (p6 < &__popc_6insn_patch_end) {
	295	unsigned long i, addr = p6->addr;
ef7c4d46	296
56d205cc DM	297	for (i = 0; i < 6; i++) {
	298	(unsigned int ) (addr + (i * 4)) = p6->insns[i];
	299	wmb();
	300	__asm__ __volatile__("flush %0"
	301	: : "r" (addr + (i * 4)));
	302	}
	303
	304	p6++;
ef7c4d46 DM	305	}
	306	}
	307
e9b9eb59 DM	308	static void __init pause_patch(void)
	309	{
	310	struct pause_patch_entry *p;
	311
187818cd DM	312	p = &__pause_3insn_patch;
187818cd DM	313	while (p < &__pause_3insn_patch_end) {
e9b9eb59 DM	314	unsigned long i, addr = p->addr;
	315
	316	for (i = 0; i < 3; i++) {
	317	(unsigned int ) (addr + (i * 4)) = p->insns[i];
	318	wmb();
	319	__asm__ __volatile__("flush %0"
	320	: : "r" (addr + (i * 4)));
	321	}
	322
	323	p++;
	324	}
	325	}
	326
ef3e035c	327	void __init start_early_boot(void)
951bc82c	328	{
ef3e035c DM	329	int cpu;
	330
	331	check_if_starfire();
	332	per_cpu_patch();
	333	sun4v_patch();
	334
	335	cpu = hard_smp_processor_id();
	336	if (cpu >= NR_CPUS) {
	337	prom_printf("Serious problem, boot cpu id (%d) >= NR_CPUS (%d)\n",
	338	cpu, NR_CPUS);
	339	prom_halt();
	340	}
	341	current_thread_info()->cpu = cpu;
	342
	343	prom_init_report();
	344	start_kernel();
951bc82c	345	}
951bc82c	346
ac85fe8b DM	347	/* On Ultra, we support all of the v8 capabilities. */
	348	unsigned long sparc64_elf_hwcap = (HWCAP_SPARC_FLUSH \| HWCAP_SPARC_STBAR \|
	349	HWCAP_SPARC_SWAP \| HWCAP_SPARC_MULDIV \|
	350	HWCAP_SPARC_V9);
	351	EXPORT_SYMBOL(sparc64_elf_hwcap);
	352
	353	static const char *hwcaps[] = {
	354	"flush", "stbar", "swap", "muldiv", "v9",
	355	"ultra3", "blkinit", "n2",
	356
	357	/* These strings are as they appear in the machine description
	358	* 'hwcap-list' property for cpu nodes.
	359	*/
	360	"mul32", "div32", "fsmuld", "v8plus", "popc", "vis", "vis2",
	361	"ASIBlkInit", "fmaf", "vis3", "hpc", "random", "trans", "fjfmau",
6f859c0e DM	362	"ima", "cspare", "pause", "cbcond",
	363	};
	364
	365	static const char *crypto_hwcaps[] = {
	366	"aes", "des", "kasumi", "camellia", "md5", "sha1", "sha256",
	367	"sha512", "mpmul", "montmul", "montsqr", "crc32c",
ac85fe8b DM	368	};
	369
	370	void cpucap_info(struct seq_file *m)
	371	{
	372	unsigned long caps = sparc64_elf_hwcap;
	373	int i, printed = 0;
	374
	375	seq_puts(m, "cpucaps\t\t: ");
	376	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	377	unsigned long bit = 1UL << i;
	378	if (caps & bit) {
	379	seq_printf(m, "%s%s",
	380	printed ? "," : "", hwcaps[i]);
	381	printed++;
	382	}
	383	}
6f859c0e DM	384	if (caps & HWCAP_SPARC_CRYPTO) {
	385	unsigned long cfr;
	386
	387	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	388	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	389	unsigned long bit = 1UL << i;
	390	if (cfr & bit) {
	391	seq_printf(m, "%s%s",
	392	printed ? "," : "", crypto_hwcaps[i]);
	393	printed++;
	394	}
	395	}
	396	}
ac85fe8b DM	397	seq_putc(m, '\n');
	398	}
	399
6f859c0e DM	400	static void __init report_one_hwcap(int printed, const char name)
	401	{
	402	if ((*printed) == 0)
	403	printk(KERN_INFO "CPU CAPS: [");
	404	printk(KERN_CONT "%s%s",
	405	(*printed) ? "," : "", name);
	406	if (++(*printed) == 8) {
	407	printk(KERN_CONT "]\n");
	408	*printed = 0;
	409	}
	410	}
	411
	412	static void __init report_crypto_hwcaps(int *printed)
	413	{
	414	unsigned long cfr;
	415	int i;
	416
	417	__asm__ __volatile__("rd %%asr26, %0" : "=r" (cfr));
	418
	419	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	420	unsigned long bit = 1UL << i;
	421	if (cfr & bit)
	422	report_one_hwcap(printed, crypto_hwcaps[i]);
	423	}
	424	}
	425
ac85fe8b DM	426	static void __init report_hwcaps(unsigned long caps)
	427	{
	428	int i, printed = 0;
	429
ac85fe8b DM	430	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
ac85fe8b DM	431	unsigned long bit = 1UL << i;
6f859c0e DM	432	if (caps & bit)
6f859c0e DM	433	report_one_hwcap(&printed, hwcaps[i]);
ac85fe8b	434	}
6f859c0e DM	435	if (caps & HWCAP_SPARC_CRYPTO)
	436	report_crypto_hwcaps(&printed);
	437	if (printed != 0)
	438	printk(KERN_CONT "]\n");
ac85fe8b DM	439	}
	440
	441	static unsigned long __init mdesc_cpu_hwcap_list(void)
	442	{
	443	struct mdesc_handle *hp;
	444	unsigned long caps = 0;
	445	const char *prop;
	446	int len;
	447	u64 pn;
	448
	449	hp = mdesc_grab();
	450	if (!hp)
	451	return 0;
	452
	453	pn = mdesc_node_by_name(hp, MDESC_NODE_NULL, "cpu");
	454	if (pn == MDESC_NODE_NULL)
	455	goto out;
	456
	457	prop = mdesc_get_property(hp, pn, "hwcap-list", &len);
	458	if (!prop)
	459	goto out;
	460
	461	while (len) {
	462	int i, plen;
	463
	464	for (i = 0; i < ARRAY_SIZE(hwcaps); i++) {
	465	unsigned long bit = 1UL << i;
	466
	467	if (!strcmp(prop, hwcaps[i])) {
	468	caps \|= bit;
	469	break;
	470	}
	471	}
6f859c0e DM	472	for (i = 0; i < ARRAY_SIZE(crypto_hwcaps); i++) {
	473	if (!strcmp(prop, crypto_hwcaps[i]))
	474	caps \|= HWCAP_SPARC_CRYPTO;
	475	}
ac85fe8b DM	476
	477	plen = strlen(prop) + 1;
	478	prop += plen;
	479	len -= plen;
	480	}
	481
	482	out:
	483	mdesc_release(hp);
	484	return caps;
	485	}
	486
	487	/* This yields a mask that user programs can use to figure out what
	488	* instruction set this cpu supports.
	489	*/
	490	static void __init init_sparc64_elf_hwcap(void)
	491	{
	492	unsigned long cap = sparc64_elf_hwcap;
	493	unsigned long mdesc_caps;
	494
	495	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	496	cap \|= HWCAP_SPARC_ULTRA3;
	497	else if (tlb_type == hypervisor) {
	498	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 \|\|
	499	sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	500	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	501	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	502	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	503	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	504	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
4e963779	505	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	506	cap \|= HWCAP_SPARC_BLKINIT;
ac85fe8b DM	507	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	508	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	509	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	510	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	511	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	512	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
4e963779	513	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	514	cap \|= HWCAP_SPARC_N2;
	515	}
	516
	517	cap \|= (AV_SPARC_MUL32 \| AV_SPARC_DIV32 \| AV_SPARC_V8PLUS);
	518
	519	mdesc_caps = mdesc_cpu_hwcap_list();
	520	if (!mdesc_caps) {
	521	if (tlb_type == spitfire)
	522	cap \|= AV_SPARC_VIS;
	523	if (tlb_type == cheetah \|\| tlb_type == cheetah_plus)
	524	cap \|= AV_SPARC_VIS \| AV_SPARC_VIS2;
1a8e0da5 DM	525	if (tlb_type == cheetah_plus) {
	526	unsigned long impl, ver;
	527
	528	__asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
	529	impl = ((ver >> 32) & 0xffff);
	530	if (impl == PANTHER_IMPL)
	531	cap \|= AV_SPARC_POPC;
	532	}
ac85fe8b DM	533	if (tlb_type == hypervisor) {
	534	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA1)
	535	cap \|= AV_SPARC_ASI_BLK_INIT;
	536	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA2 \|\|
08cefa9f DM	537	sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	538	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	539	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	540	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	541	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
4e963779	542	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	543	cap \|= (AV_SPARC_VIS \| AV_SPARC_VIS2 \|
	544	AV_SPARC_ASI_BLK_INIT \|
	545	AV_SPARC_POPC);
08cefa9f DM	546	if (sun4v_chip_type == SUN4V_CHIP_NIAGARA3 \|\|
08cefa9f DM	547	sun4v_chip_type == SUN4V_CHIP_NIAGARA4 \|\|
4e963779	548	sun4v_chip_type == SUN4V_CHIP_NIAGARA5 \|\|
40831625 AP	549	sun4v_chip_type == SUN4V_CHIP_SPARC_M6 \|\|
40831625 AP	550	sun4v_chip_type == SUN4V_CHIP_SPARC_M7 \|\|
4e963779	551	sun4v_chip_type == SUN4V_CHIP_SPARC64X)
ac85fe8b DM	552	cap \|= (AV_SPARC_VIS3 \| AV_SPARC_HPC \|
	553	AV_SPARC_FMAF);
	554	}
	555	}
	556	sparc64_elf_hwcap = cap \| mdesc_caps;
	557
	558	report_hwcaps(sparc64_elf_hwcap);
ef7c4d46 DM	559
	560	if (sparc64_elf_hwcap & AV_SPARC_POPC)
	561	popc_patch();
e9b9eb59 DM	562	if (sparc64_elf_hwcap & AV_SPARC_PAUSE)
e9b9eb59 DM	563	pause_patch();
ac85fe8b DM	564	}
ac85fe8b DM	565
1da177e4 LT	566	void __init setup_arch(char **cmdline_p)
1da177e4 LT	567	{
1da177e4 LT	568	/* Initialize PROM console and command line. */
1da177e4 LT	569	*cmdline_p = prom_getbootargs();
117a0c5f	570	strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
ce3b1d47	571	parse_early_param();
1da177e4	572
3c62a2d3	573	boot_flags_init(*cmdline_p);
c57ec52f DM	574	#ifdef CONFIG_EARLYFB
	575	if (btext_find_display())
	576	#endif
	577	register_console(&prom_early_console);
3c62a2d3	578
3a8c069d DM	579	if (tlb_type == hypervisor)
	580	printk("ARCH: SUN4V\n");
	581	else
	582	printk("ARCH: SUN4U\n");
1da177e4 LT	583
	584	#ifdef CONFIG_DUMMY_CONSOLE
	585	conswitchp = &dummy_con;
1da177e4 LT	586	#endif
1da177e4 LT	587
1da177e4	588	idprom_init();
1da177e4 LT	589
	590	if (!root_flags)
	591	root_mountflags &= ~MS_RDONLY;
	592	ROOT_DEV = old_decode_dev(root_dev);
467418f3	593	#ifdef CONFIG_BLK_DEV_RAM
1da177e4 LT	594	rd_image_start = ram_flags & RAMDISK_IMAGE_START_MASK;
	595	rd_prompt = ((ram_flags & RAMDISK_PROMPT_FLAG) != 0);
	596	rd_doload = ((ram_flags & RAMDISK_LOAD_FLAG) != 0);
	597	#endif
	598
f3169641	599	task_thread_info(&init_task)->kregs = &fake_swapper_regs;
1da177e4 LT	600
	601	#ifdef CONFIG_IP_PNP
	602	if (!ic_set_manually) {
8d125562	603	phandle chosen = prom_finddevice("/chosen");
1da177e4 LT	604	u32 cl, sv, gw;
	605
	606	cl = prom_getintdefault (chosen, "client-ip", 0);
	607	sv = prom_getintdefault (chosen, "server-ip", 0);
	608	gw = prom_getintdefault (chosen, "gateway-ip", 0);
	609	if (cl && sv) {
	610	ic_myaddr = cl;
	611	ic_servaddr = sv;
	612	if (gw)
	613	ic_gateway = gw;
	614	#if defined(CONFIG_IP_PNP_BOOTP) \|\| defined(CONFIG_IP_PNP_RARP)
	615	ic_proto_enabled = 0;
	616	#endif
	617	}
	618	}
	619	#endif
	620
56fb4df6	621	/* Get boot processor trap_block[] setup. */
72aff53f	622	init_cur_cpu_trap(current_thread_info());
52845cdb DM	623
52845cdb DM	624	paging_init();
ac85fe8b	625	init_sparc64_elf_hwcap();
1da177e4 LT	626	}
1da177e4 LT	627
1da177e4 LT	628	extern int stop_a_enabled;
	629
	630	void sun_do_break(void)
	631	{
	632	if (!stop_a_enabled)
	633	return;
	634
	635	prom_printf("\n");
	636	flush_user_windows();
	637
	638	prom_cmdline();
	639	}
917c3660	640	EXPORT_SYMBOL(sun_do_break);
1da177e4	641
1da177e4	642	int stop_a_enabled = 1;
917c3660	643	EXPORT_SYMBOL(stop_a_enabled);