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Commit | Line | Data |
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1da177e4 LT |
1 | /* smp.c: Sparc64 SMP support. |
2 | * | |
cf3d7c1e | 3 | * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | */ |
5 | ||
066bcaca | 6 | #include <linux/export.h> |
1da177e4 LT |
7 | #include <linux/kernel.h> |
8 | #include <linux/sched.h> | |
9 | #include <linux/mm.h> | |
10 | #include <linux/pagemap.h> | |
11 | #include <linux/threads.h> | |
12 | #include <linux/smp.h> | |
1da177e4 LT |
13 | #include <linux/interrupt.h> |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/seq_file.h> | |
20 | #include <linux/cache.h> | |
21 | #include <linux/jiffies.h> | |
22 | #include <linux/profile.h> | |
73fffc03 | 23 | #include <linux/bootmem.h> |
4fd78a5f | 24 | #include <linux/vmalloc.h> |
9960e9e8 | 25 | #include <linux/ftrace.h> |
82960b85 | 26 | #include <linux/cpu.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
1da177e4 LT |
28 | |
29 | #include <asm/head.h> | |
30 | #include <asm/ptrace.h> | |
60063497 | 31 | #include <linux/atomic.h> |
1da177e4 LT |
32 | #include <asm/tlbflush.h> |
33 | #include <asm/mmu_context.h> | |
34 | #include <asm/cpudata.h> | |
27a2ef38 DM |
35 | #include <asm/hvtramp.h> |
36 | #include <asm/io.h> | |
cf3d7c1e | 37 | #include <asm/timer.h> |
1da177e4 LT |
38 | |
39 | #include <asm/irq.h> | |
6d24c8dc | 40 | #include <asm/irq_regs.h> |
1da177e4 LT |
41 | #include <asm/page.h> |
42 | #include <asm/pgtable.h> | |
43 | #include <asm/oplib.h> | |
44 | #include <asm/uaccess.h> | |
1da177e4 LT |
45 | #include <asm/starfire.h> |
46 | #include <asm/tlb.h> | |
56fb4df6 | 47 | #include <asm/sections.h> |
07f8e5f3 | 48 | #include <asm/prom.h> |
5cbc3073 | 49 | #include <asm/mdesc.h> |
4f0234f4 | 50 | #include <asm/ldc.h> |
e0204409 | 51 | #include <asm/hypervisor.h> |
b62818e5 | 52 | #include <asm/pcr.h> |
1da177e4 | 53 | |
280ff974 | 54 | #include "cpumap.h" |
a0c54a21 | 55 | #include "kernel.h" |
280ff974 | 56 | |
d5a7430d | 57 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE; |
f78eae2e DM |
58 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly = |
59 | { [0 ... NR_CPUS-1] = CPU_MASK_NONE }; | |
4f0234f4 | 60 | |
d5a7430d | 61 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
4f0234f4 DM |
62 | EXPORT_SYMBOL(cpu_core_map); |
63 | ||
1da177e4 | 64 | static cpumask_t smp_commenced_mask; |
1da177e4 LT |
65 | |
66 | void smp_info(struct seq_file *m) | |
67 | { | |
68 | int i; | |
69 | ||
70 | seq_printf(m, "State:\n"); | |
394e3902 AM |
71 | for_each_online_cpu(i) |
72 | seq_printf(m, "CPU%d:\t\tonline\n", i); | |
1da177e4 LT |
73 | } |
74 | ||
75 | void smp_bogo(struct seq_file *m) | |
76 | { | |
77 | int i; | |
78 | ||
394e3902 AM |
79 | for_each_online_cpu(i) |
80 | seq_printf(m, | |
394e3902 | 81 | "Cpu%dClkTck\t: %016lx\n", |
394e3902 | 82 | i, cpu_data(i).clock_tick); |
1da177e4 LT |
83 | } |
84 | ||
112f4871 | 85 | extern void setup_sparc64_timer(void); |
1da177e4 LT |
86 | |
87 | static volatile unsigned long callin_flag = 0; | |
88 | ||
2066aadd | 89 | void smp_callin(void) |
1da177e4 LT |
90 | { |
91 | int cpuid = hard_smp_processor_id(); | |
92 | ||
56fb4df6 | 93 | __local_per_cpu_offset = __per_cpu_offset(cpuid); |
1da177e4 | 94 | |
4a07e646 | 95 | if (tlb_type == hypervisor) |
490384e7 | 96 | sun4v_ktsb_register(); |
481295f9 | 97 | |
56fb4df6 | 98 | __flush_tlb_all(); |
1da177e4 | 99 | |
112f4871 | 100 | setup_sparc64_timer(); |
1da177e4 | 101 | |
816242da DM |
102 | if (cheetah_pcache_forced_on) |
103 | cheetah_enable_pcache(); | |
104 | ||
1da177e4 LT |
105 | callin_flag = 1; |
106 | __asm__ __volatile__("membar #Sync\n\t" | |
107 | "flush %%g6" : : : "memory"); | |
108 | ||
109 | /* Clear this or we will die instantly when we | |
110 | * schedule back to this idler... | |
111 | */ | |
db7d9a4e | 112 | current_thread_info()->new_child = 0; |
1da177e4 LT |
113 | |
114 | /* Attach to the address space of init_task. */ | |
115 | atomic_inc(&init_mm.mm_count); | |
116 | current->active_mm = &init_mm; | |
117 | ||
82960b85 DM |
118 | /* inform the notifiers about the new cpu */ |
119 | notify_cpu_starting(cpuid); | |
120 | ||
fb1fece5 | 121 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
4f07118f | 122 | rmb(); |
1da177e4 | 123 | |
fb1fece5 | 124 | set_cpu_online(cpuid, true); |
5bfb5d69 NP |
125 | |
126 | /* idle thread is expected to have preempt disabled */ | |
127 | preempt_disable(); | |
87fa05ae | 128 | |
ce2521bf KT |
129 | local_irq_enable(); |
130 | ||
87fa05ae | 131 | cpu_startup_entry(CPUHP_ONLINE); |
1da177e4 LT |
132 | } |
133 | ||
134 | void cpu_panic(void) | |
135 | { | |
136 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
137 | panic("SMP bolixed\n"); | |
138 | } | |
139 | ||
1da177e4 LT |
140 | /* This tick register synchronization scheme is taken entirely from |
141 | * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit. | |
142 | * | |
143 | * The only change I've made is to rework it so that the master | |
144 | * initiates the synchonization instead of the slave. -DaveM | |
145 | */ | |
146 | ||
147 | #define MASTER 0 | |
148 | #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long)) | |
149 | ||
150 | #define NUM_ROUNDS 64 /* magic value */ | |
151 | #define NUM_ITERS 5 /* likewise */ | |
152 | ||
153 | static DEFINE_SPINLOCK(itc_sync_lock); | |
154 | static unsigned long go[SLAVE + 1]; | |
155 | ||
156 | #define DEBUG_TICK_SYNC 0 | |
157 | ||
158 | static inline long get_delta (long *rt, long *master) | |
159 | { | |
160 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; | |
161 | unsigned long tcenter, t0, t1, tm; | |
162 | unsigned long i; | |
163 | ||
164 | for (i = 0; i < NUM_ITERS; i++) { | |
165 | t0 = tick_ops->get_tick(); | |
166 | go[MASTER] = 1; | |
293666b7 | 167 | membar_safe("#StoreLoad"); |
1da177e4 | 168 | while (!(tm = go[SLAVE])) |
4f07118f | 169 | rmb(); |
1da177e4 | 170 | go[SLAVE] = 0; |
4f07118f | 171 | wmb(); |
1da177e4 LT |
172 | t1 = tick_ops->get_tick(); |
173 | ||
174 | if (t1 - t0 < best_t1 - best_t0) | |
175 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
176 | } | |
177 | ||
178 | *rt = best_t1 - best_t0; | |
179 | *master = best_tm - best_t0; | |
180 | ||
181 | /* average best_t0 and best_t1 without overflow: */ | |
182 | tcenter = (best_t0/2 + best_t1/2); | |
183 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
184 | tcenter++; | |
185 | return tcenter - best_tm; | |
186 | } | |
187 | ||
188 | void smp_synchronize_tick_client(void) | |
189 | { | |
190 | long i, delta, adj, adjust_latency = 0, done = 0; | |
c6fee081 | 191 | unsigned long flags, rt, master_time_stamp; |
1da177e4 LT |
192 | #if DEBUG_TICK_SYNC |
193 | struct { | |
194 | long rt; /* roundtrip time */ | |
195 | long master; /* master's timestamp */ | |
196 | long diff; /* difference between midpoint and master's timestamp */ | |
197 | long lat; /* estimate of itc adjustment latency */ | |
198 | } t[NUM_ROUNDS]; | |
199 | #endif | |
200 | ||
201 | go[MASTER] = 1; | |
202 | ||
203 | while (go[MASTER]) | |
4f07118f | 204 | rmb(); |
1da177e4 LT |
205 | |
206 | local_irq_save(flags); | |
207 | { | |
208 | for (i = 0; i < NUM_ROUNDS; i++) { | |
209 | delta = get_delta(&rt, &master_time_stamp); | |
c6fee081 | 210 | if (delta == 0) |
1da177e4 | 211 | done = 1; /* let's lock on to this... */ |
1da177e4 LT |
212 | |
213 | if (!done) { | |
214 | if (i > 0) { | |
215 | adjust_latency += -delta; | |
216 | adj = -delta + adjust_latency/4; | |
217 | } else | |
218 | adj = -delta; | |
219 | ||
112f4871 | 220 | tick_ops->add_tick(adj); |
1da177e4 LT |
221 | } |
222 | #if DEBUG_TICK_SYNC | |
223 | t[i].rt = rt; | |
224 | t[i].master = master_time_stamp; | |
225 | t[i].diff = delta; | |
226 | t[i].lat = adjust_latency/4; | |
227 | #endif | |
228 | } | |
229 | } | |
230 | local_irq_restore(flags); | |
231 | ||
232 | #if DEBUG_TICK_SYNC | |
233 | for (i = 0; i < NUM_ROUNDS; i++) | |
234 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
235 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
236 | #endif | |
237 | ||
519c4d2d JP |
238 | printk(KERN_INFO "CPU %d: synchronized TICK with master CPU " |
239 | "(last diff %ld cycles, maxerr %lu cycles)\n", | |
240 | smp_processor_id(), delta, rt); | |
1da177e4 LT |
241 | } |
242 | ||
243 | static void smp_start_sync_tick_client(int cpu); | |
244 | ||
245 | static void smp_synchronize_one_tick(int cpu) | |
246 | { | |
247 | unsigned long flags, i; | |
248 | ||
249 | go[MASTER] = 0; | |
250 | ||
251 | smp_start_sync_tick_client(cpu); | |
252 | ||
253 | /* wait for client to be ready */ | |
254 | while (!go[MASTER]) | |
4f07118f | 255 | rmb(); |
1da177e4 LT |
256 | |
257 | /* now let the client proceed into his loop */ | |
258 | go[MASTER] = 0; | |
293666b7 | 259 | membar_safe("#StoreLoad"); |
1da177e4 LT |
260 | |
261 | spin_lock_irqsave(&itc_sync_lock, flags); | |
262 | { | |
263 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) { | |
264 | while (!go[MASTER]) | |
4f07118f | 265 | rmb(); |
1da177e4 | 266 | go[MASTER] = 0; |
4f07118f | 267 | wmb(); |
1da177e4 | 268 | go[SLAVE] = tick_ops->get_tick(); |
293666b7 | 269 | membar_safe("#StoreLoad"); |
1da177e4 LT |
270 | } |
271 | } | |
272 | spin_unlock_irqrestore(&itc_sync_lock, flags); | |
273 | } | |
274 | ||
b14f5c10 | 275 | #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU) |
2066aadd PG |
276 | static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg, |
277 | void **descrp) | |
b14f5c10 DM |
278 | { |
279 | extern unsigned long sparc64_ttable_tl0; | |
280 | extern unsigned long kern_locked_tte_data; | |
b14f5c10 DM |
281 | struct hvtramp_descr *hdesc; |
282 | unsigned long trampoline_ra; | |
283 | struct trap_per_cpu *tb; | |
284 | u64 tte_vaddr, tte_data; | |
285 | unsigned long hv_err; | |
64658743 | 286 | int i; |
b14f5c10 | 287 | |
64658743 DM |
288 | hdesc = kzalloc(sizeof(*hdesc) + |
289 | (sizeof(struct hvtramp_mapping) * | |
290 | num_kernel_image_mappings - 1), | |
291 | GFP_KERNEL); | |
b14f5c10 | 292 | if (!hdesc) { |
27a2ef38 | 293 | printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate " |
b14f5c10 DM |
294 | "hvtramp_descr.\n"); |
295 | return; | |
296 | } | |
557fe0e8 | 297 | *descrp = hdesc; |
b14f5c10 DM |
298 | |
299 | hdesc->cpu = cpu; | |
64658743 | 300 | hdesc->num_mappings = num_kernel_image_mappings; |
b14f5c10 DM |
301 | |
302 | tb = &trap_block[cpu]; | |
b14f5c10 DM |
303 | |
304 | hdesc->fault_info_va = (unsigned long) &tb->fault_info; | |
305 | hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info); | |
306 | ||
307 | hdesc->thread_reg = thread_reg; | |
308 | ||
309 | tte_vaddr = (unsigned long) KERNBASE; | |
310 | tte_data = kern_locked_tte_data; | |
311 | ||
64658743 DM |
312 | for (i = 0; i < hdesc->num_mappings; i++) { |
313 | hdesc->maps[i].vaddr = tte_vaddr; | |
314 | hdesc->maps[i].tte = tte_data; | |
b14f5c10 DM |
315 | tte_vaddr += 0x400000; |
316 | tte_data += 0x400000; | |
b14f5c10 DM |
317 | } |
318 | ||
319 | trampoline_ra = kimage_addr_to_ra(hv_cpu_startup); | |
320 | ||
321 | hv_err = sun4v_cpu_start(cpu, trampoline_ra, | |
322 | kimage_addr_to_ra(&sparc64_ttable_tl0), | |
323 | __pa(hdesc)); | |
e0204409 DM |
324 | if (hv_err) |
325 | printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() " | |
326 | "gives error %lu\n", hv_err); | |
b14f5c10 DM |
327 | } |
328 | #endif | |
329 | ||
1da177e4 LT |
330 | extern unsigned long sparc64_cpu_startup; |
331 | ||
332 | /* The OBP cpu startup callback truncates the 3rd arg cookie to | |
333 | * 32-bits (I think) so to be safe we have it read the pointer | |
334 | * contained here so we work on >4GB machines. -DaveM | |
335 | */ | |
336 | static struct thread_info *cpu_new_thread = NULL; | |
337 | ||
2066aadd | 338 | static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle) |
1da177e4 LT |
339 | { |
340 | unsigned long entry = | |
341 | (unsigned long)(&sparc64_cpu_startup); | |
342 | unsigned long cookie = | |
343 | (unsigned long)(&cpu_new_thread); | |
557fe0e8 | 344 | void *descr = NULL; |
7890f794 | 345 | int timeout, ret; |
1da177e4 | 346 | |
1da177e4 | 347 | callin_flag = 0; |
f0a2bc7e | 348 | cpu_new_thread = task_thread_info(idle); |
1da177e4 | 349 | |
7890f794 | 350 | if (tlb_type == hypervisor) { |
b14f5c10 | 351 | #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU) |
4f0234f4 DM |
352 | if (ldom_domaining_enabled) |
353 | ldom_startcpu_cpuid(cpu, | |
557fe0e8 DM |
354 | (unsigned long) cpu_new_thread, |
355 | &descr); | |
4f0234f4 DM |
356 | else |
357 | #endif | |
358 | prom_startcpu_cpuid(cpu, entry, cookie); | |
7890f794 | 359 | } else { |
5cbc3073 | 360 | struct device_node *dp = of_find_node_by_cpuid(cpu); |
7890f794 | 361 | |
6016a363 | 362 | prom_startcpu(dp->phandle, entry, cookie); |
7890f794 | 363 | } |
1da177e4 | 364 | |
4f0234f4 | 365 | for (timeout = 0; timeout < 50000; timeout++) { |
1da177e4 LT |
366 | if (callin_flag) |
367 | break; | |
368 | udelay(100); | |
369 | } | |
72aff53f | 370 | |
1da177e4 LT |
371 | if (callin_flag) { |
372 | ret = 0; | |
373 | } else { | |
374 | printk("Processor %d is stuck.\n", cpu); | |
1da177e4 LT |
375 | ret = -ENODEV; |
376 | } | |
377 | cpu_new_thread = NULL; | |
378 | ||
557fe0e8 | 379 | kfree(descr); |
b37d40d1 | 380 | |
1da177e4 LT |
381 | return ret; |
382 | } | |
383 | ||
384 | static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) | |
385 | { | |
386 | u64 result, target; | |
387 | int stuck, tmp; | |
388 | ||
389 | if (this_is_starfire) { | |
390 | /* map to real upaid */ | |
391 | cpu = (((cpu & 0x3c) << 1) | | |
392 | ((cpu & 0x40) >> 4) | | |
393 | (cpu & 0x3)); | |
394 | } | |
395 | ||
396 | target = (cpu << 14) | 0x70; | |
397 | again: | |
398 | /* Ok, this is the real Spitfire Errata #54. | |
399 | * One must read back from a UDB internal register | |
400 | * after writes to the UDB interrupt dispatch, but | |
401 | * before the membar Sync for that write. | |
402 | * So we use the high UDB control register (ASI 0x7f, | |
403 | * ADDR 0x20) for the dummy read. -DaveM | |
404 | */ | |
405 | tmp = 0x40; | |
406 | __asm__ __volatile__( | |
407 | "wrpr %1, %2, %%pstate\n\t" | |
408 | "stxa %4, [%0] %3\n\t" | |
409 | "stxa %5, [%0+%8] %3\n\t" | |
410 | "add %0, %8, %0\n\t" | |
411 | "stxa %6, [%0+%8] %3\n\t" | |
412 | "membar #Sync\n\t" | |
413 | "stxa %%g0, [%7] %3\n\t" | |
414 | "membar #Sync\n\t" | |
415 | "mov 0x20, %%g1\n\t" | |
416 | "ldxa [%%g1] 0x7f, %%g0\n\t" | |
417 | "membar #Sync" | |
418 | : "=r" (tmp) | |
419 | : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), | |
420 | "r" (data0), "r" (data1), "r" (data2), "r" (target), | |
421 | "r" (0x10), "0" (tmp) | |
422 | : "g1"); | |
423 | ||
424 | /* NOTE: PSTATE_IE is still clear. */ | |
425 | stuck = 100000; | |
426 | do { | |
427 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
428 | : "=r" (result) | |
429 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
430 | if (result == 0) { | |
431 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
432 | : : "r" (pstate)); | |
433 | return; | |
434 | } | |
435 | stuck -= 1; | |
436 | if (stuck == 0) | |
437 | break; | |
438 | } while (result & 0x1); | |
439 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
440 | : : "r" (pstate)); | |
441 | if (stuck == 0) { | |
90181136 | 442 | printk("CPU[%d]: mondo stuckage result[%016llx]\n", |
1da177e4 LT |
443 | smp_processor_id(), result); |
444 | } else { | |
445 | udelay(2); | |
446 | goto again; | |
447 | } | |
448 | } | |
449 | ||
90f7ae8a | 450 | static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
1da177e4 | 451 | { |
90f7ae8a DM |
452 | u64 *mondo, data0, data1, data2; |
453 | u16 *cpu_list; | |
1da177e4 LT |
454 | u64 pstate; |
455 | int i; | |
456 | ||
457 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
90f7ae8a DM |
458 | cpu_list = __va(tb->cpu_list_pa); |
459 | mondo = __va(tb->cpu_mondo_block_pa); | |
460 | data0 = mondo[0]; | |
461 | data1 = mondo[1]; | |
462 | data2 = mondo[2]; | |
463 | for (i = 0; i < cnt; i++) | |
464 | spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]); | |
1da177e4 LT |
465 | } |
466 | ||
467 | /* Cheetah now allows to send the whole 64-bytes of data in the interrupt | |
468 | * packet, but we have no use for that. However we do take advantage of | |
469 | * the new pipelining feature (ie. dispatch to multiple cpus simultaneously). | |
470 | */ | |
90f7ae8a | 471 | static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
1da177e4 | 472 | { |
22adb358 | 473 | int nack_busy_id, is_jbus, need_more; |
90f7ae8a DM |
474 | u64 *mondo, pstate, ver, busy_mask; |
475 | u16 *cpu_list; | |
1da177e4 | 476 | |
90f7ae8a DM |
477 | cpu_list = __va(tb->cpu_list_pa); |
478 | mondo = __va(tb->cpu_mondo_block_pa); | |
cd5bc89d | 479 | |
1da177e4 LT |
480 | /* Unfortunately, someone at Sun had the brilliant idea to make the |
481 | * busy/nack fields hard-coded by ITID number for this Ultra-III | |
482 | * derivative processor. | |
483 | */ | |
484 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
92704a1c DM |
485 | is_jbus = ((ver >> 32) == __JALAPENO_ID || |
486 | (ver >> 32) == __SERRANO_ID); | |
1da177e4 LT |
487 | |
488 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
489 | ||
490 | retry: | |
22adb358 | 491 | need_more = 0; |
1da177e4 LT |
492 | __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t" |
493 | : : "r" (pstate), "i" (PSTATE_IE)); | |
494 | ||
495 | /* Setup the dispatch data registers. */ | |
496 | __asm__ __volatile__("stxa %0, [%3] %6\n\t" | |
497 | "stxa %1, [%4] %6\n\t" | |
498 | "stxa %2, [%5] %6\n\t" | |
499 | "membar #Sync\n\t" | |
500 | : /* no outputs */ | |
90f7ae8a | 501 | : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]), |
1da177e4 LT |
502 | "r" (0x40), "r" (0x50), "r" (0x60), |
503 | "i" (ASI_INTR_W)); | |
504 | ||
505 | nack_busy_id = 0; | |
0de56d1a | 506 | busy_mask = 0; |
1da177e4 LT |
507 | { |
508 | int i; | |
509 | ||
90f7ae8a DM |
510 | for (i = 0; i < cnt; i++) { |
511 | u64 target, nr; | |
512 | ||
513 | nr = cpu_list[i]; | |
514 | if (nr == 0xffff) | |
515 | continue; | |
1da177e4 | 516 | |
90f7ae8a | 517 | target = (nr << 14) | 0x70; |
0de56d1a | 518 | if (is_jbus) { |
90f7ae8a | 519 | busy_mask |= (0x1UL << (nr * 2)); |
0de56d1a | 520 | } else { |
1da177e4 | 521 | target |= (nack_busy_id << 24); |
0de56d1a DM |
522 | busy_mask |= (0x1UL << |
523 | (nack_busy_id * 2)); | |
524 | } | |
1da177e4 LT |
525 | __asm__ __volatile__( |
526 | "stxa %%g0, [%0] %1\n\t" | |
527 | "membar #Sync\n\t" | |
528 | : /* no outputs */ | |
529 | : "r" (target), "i" (ASI_INTR_W)); | |
530 | nack_busy_id++; | |
22adb358 DM |
531 | if (nack_busy_id == 32) { |
532 | need_more = 1; | |
533 | break; | |
534 | } | |
1da177e4 LT |
535 | } |
536 | } | |
537 | ||
538 | /* Now, poll for completion. */ | |
539 | { | |
0de56d1a | 540 | u64 dispatch_stat, nack_mask; |
1da177e4 LT |
541 | long stuck; |
542 | ||
543 | stuck = 100000 * nack_busy_id; | |
0de56d1a | 544 | nack_mask = busy_mask << 1; |
1da177e4 LT |
545 | do { |
546 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
547 | : "=r" (dispatch_stat) | |
548 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
0de56d1a | 549 | if (!(dispatch_stat & (busy_mask | nack_mask))) { |
1da177e4 LT |
550 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" |
551 | : : "r" (pstate)); | |
22adb358 | 552 | if (unlikely(need_more)) { |
90f7ae8a DM |
553 | int i, this_cnt = 0; |
554 | for (i = 0; i < cnt; i++) { | |
555 | if (cpu_list[i] == 0xffff) | |
556 | continue; | |
557 | cpu_list[i] = 0xffff; | |
558 | this_cnt++; | |
559 | if (this_cnt == 32) | |
22adb358 DM |
560 | break; |
561 | } | |
562 | goto retry; | |
563 | } | |
1da177e4 LT |
564 | return; |
565 | } | |
566 | if (!--stuck) | |
567 | break; | |
0de56d1a | 568 | } while (dispatch_stat & busy_mask); |
1da177e4 LT |
569 | |
570 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
571 | : : "r" (pstate)); | |
572 | ||
0de56d1a | 573 | if (dispatch_stat & busy_mask) { |
1da177e4 LT |
574 | /* Busy bits will not clear, continue instead |
575 | * of freezing up on this cpu. | |
576 | */ | |
90181136 | 577 | printk("CPU[%d]: mondo stuckage result[%016llx]\n", |
1da177e4 LT |
578 | smp_processor_id(), dispatch_stat); |
579 | } else { | |
580 | int i, this_busy_nack = 0; | |
581 | ||
582 | /* Delay some random time with interrupts enabled | |
583 | * to prevent deadlock. | |
584 | */ | |
585 | udelay(2 * nack_busy_id); | |
586 | ||
587 | /* Clear out the mask bits for cpus which did not | |
588 | * NACK us. | |
589 | */ | |
90f7ae8a DM |
590 | for (i = 0; i < cnt; i++) { |
591 | u64 check_mask, nr; | |
592 | ||
593 | nr = cpu_list[i]; | |
594 | if (nr == 0xffff) | |
595 | continue; | |
1da177e4 | 596 | |
92704a1c | 597 | if (is_jbus) |
90f7ae8a | 598 | check_mask = (0x2UL << (2*nr)); |
1da177e4 LT |
599 | else |
600 | check_mask = (0x2UL << | |
601 | this_busy_nack); | |
602 | if ((dispatch_stat & check_mask) == 0) | |
90f7ae8a | 603 | cpu_list[i] = 0xffff; |
1da177e4 | 604 | this_busy_nack += 2; |
22adb358 DM |
605 | if (this_busy_nack == 64) |
606 | break; | |
1da177e4 LT |
607 | } |
608 | ||
609 | goto retry; | |
610 | } | |
611 | } | |
612 | } | |
613 | ||
1d2f1f90 | 614 | /* Multi-cpu list version. */ |
90f7ae8a | 615 | static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
a43fe0e7 | 616 | { |
ed4d9c66 | 617 | int retries, this_cpu, prev_sent, i, saw_cpu_error; |
c02a5119 | 618 | unsigned long status; |
b830ab66 | 619 | u16 *cpu_list; |
17f34f0e | 620 | |
b830ab66 | 621 | this_cpu = smp_processor_id(); |
1d2f1f90 | 622 | |
b830ab66 DM |
623 | cpu_list = __va(tb->cpu_list_pa); |
624 | ||
ed4d9c66 | 625 | saw_cpu_error = 0; |
1d2f1f90 | 626 | retries = 0; |
3cab0c3e | 627 | prev_sent = 0; |
1d2f1f90 | 628 | do { |
3cab0c3e | 629 | int forward_progress, n_sent; |
1d2f1f90 | 630 | |
b830ab66 DM |
631 | status = sun4v_cpu_mondo_send(cnt, |
632 | tb->cpu_list_pa, | |
633 | tb->cpu_mondo_block_pa); | |
634 | ||
635 | /* HV_EOK means all cpus received the xcall, we're done. */ | |
636 | if (likely(status == HV_EOK)) | |
1d2f1f90 | 637 | break; |
b830ab66 | 638 | |
3cab0c3e DM |
639 | /* First, see if we made any forward progress. |
640 | * | |
641 | * The hypervisor indicates successful sends by setting | |
642 | * cpu list entries to the value 0xffff. | |
b830ab66 | 643 | */ |
3cab0c3e | 644 | n_sent = 0; |
b830ab66 | 645 | for (i = 0; i < cnt; i++) { |
3cab0c3e DM |
646 | if (likely(cpu_list[i] == 0xffff)) |
647 | n_sent++; | |
1d2f1f90 DM |
648 | } |
649 | ||
3cab0c3e DM |
650 | forward_progress = 0; |
651 | if (n_sent > prev_sent) | |
652 | forward_progress = 1; | |
653 | ||
654 | prev_sent = n_sent; | |
655 | ||
b830ab66 DM |
656 | /* If we get a HV_ECPUERROR, then one or more of the cpus |
657 | * in the list are in error state. Use the cpu_state() | |
658 | * hypervisor call to find out which cpus are in error state. | |
659 | */ | |
660 | if (unlikely(status == HV_ECPUERROR)) { | |
661 | for (i = 0; i < cnt; i++) { | |
662 | long err; | |
663 | u16 cpu; | |
664 | ||
665 | cpu = cpu_list[i]; | |
666 | if (cpu == 0xffff) | |
667 | continue; | |
668 | ||
669 | err = sun4v_cpu_state(cpu); | |
ed4d9c66 DM |
670 | if (err == HV_CPU_STATE_ERROR) { |
671 | saw_cpu_error = (cpu + 1); | |
3cab0c3e | 672 | cpu_list[i] = 0xffff; |
b830ab66 DM |
673 | } |
674 | } | |
675 | } else if (unlikely(status != HV_EWOULDBLOCK)) | |
676 | goto fatal_mondo_error; | |
677 | ||
3cab0c3e DM |
678 | /* Don't bother rewriting the CPU list, just leave the |
679 | * 0xffff and non-0xffff entries in there and the | |
680 | * hypervisor will do the right thing. | |
681 | * | |
682 | * Only advance timeout state if we didn't make any | |
683 | * forward progress. | |
684 | */ | |
b830ab66 DM |
685 | if (unlikely(!forward_progress)) { |
686 | if (unlikely(++retries > 10000)) | |
687 | goto fatal_mondo_timeout; | |
688 | ||
689 | /* Delay a little bit to let other cpus catch up | |
690 | * on their cpu mondo queue work. | |
691 | */ | |
692 | udelay(2 * cnt); | |
693 | } | |
1d2f1f90 DM |
694 | } while (1); |
695 | ||
ed4d9c66 | 696 | if (unlikely(saw_cpu_error)) |
b830ab66 DM |
697 | goto fatal_mondo_cpu_error; |
698 | ||
699 | return; | |
700 | ||
701 | fatal_mondo_cpu_error: | |
702 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus " | |
ed4d9c66 DM |
703 | "(including %d) were in error state\n", |
704 | this_cpu, saw_cpu_error - 1); | |
b830ab66 DM |
705 | return; |
706 | ||
707 | fatal_mondo_timeout: | |
b830ab66 DM |
708 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward " |
709 | " progress after %d retries.\n", | |
710 | this_cpu, retries); | |
711 | goto dump_cpu_list_and_out; | |
712 | ||
713 | fatal_mondo_error: | |
b830ab66 DM |
714 | printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n", |
715 | this_cpu, status); | |
716 | printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) " | |
717 | "mondo_block_pa(%lx)\n", | |
718 | this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa); | |
719 | ||
720 | dump_cpu_list_and_out: | |
721 | printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu); | |
722 | for (i = 0; i < cnt; i++) | |
723 | printk("%u ", cpu_list[i]); | |
724 | printk("]\n"); | |
1d2f1f90 | 725 | } |
a43fe0e7 | 726 | |
90f7ae8a | 727 | static void (*xcall_deliver_impl)(struct trap_per_cpu *, int); |
deb16999 DM |
728 | |
729 | static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask) | |
730 | { | |
90f7ae8a DM |
731 | struct trap_per_cpu *tb; |
732 | int this_cpu, i, cnt; | |
c02a5119 | 733 | unsigned long flags; |
90f7ae8a DM |
734 | u16 *cpu_list; |
735 | u64 *mondo; | |
c02a5119 DM |
736 | |
737 | /* We have to do this whole thing with interrupts fully disabled. | |
738 | * Otherwise if we send an xcall from interrupt context it will | |
739 | * corrupt both our mondo block and cpu list state. | |
740 | * | |
741 | * One consequence of this is that we cannot use timeout mechanisms | |
742 | * that depend upon interrupts being delivered locally. So, for | |
743 | * example, we cannot sample jiffies and expect it to advance. | |
744 | * | |
745 | * Fortunately, udelay() uses %stick/%tick so we can use that. | |
746 | */ | |
747 | local_irq_save(flags); | |
90f7ae8a DM |
748 | |
749 | this_cpu = smp_processor_id(); | |
750 | tb = &trap_block[this_cpu]; | |
751 | ||
752 | mondo = __va(tb->cpu_mondo_block_pa); | |
753 | mondo[0] = data0; | |
754 | mondo[1] = data1; | |
755 | mondo[2] = data2; | |
756 | wmb(); | |
757 | ||
758 | cpu_list = __va(tb->cpu_list_pa); | |
759 | ||
760 | /* Setup the initial cpu list. */ | |
761 | cnt = 0; | |
8e757281 | 762 | for_each_cpu(i, mask) { |
90f7ae8a DM |
763 | if (i == this_cpu || !cpu_online(i)) |
764 | continue; | |
765 | cpu_list[cnt++] = i; | |
766 | } | |
767 | ||
768 | if (cnt) | |
769 | xcall_deliver_impl(tb, cnt); | |
770 | ||
c02a5119 | 771 | local_irq_restore(flags); |
deb16999 | 772 | } |
5e0797e5 | 773 | |
91a4231c DM |
774 | /* Send cross call to all processors mentioned in MASK_P |
775 | * except self. Really, there are only two cases currently, | |
fb1fece5 | 776 | * "cpu_online_mask" and "mm_cpumask(mm)". |
1da177e4 | 777 | */ |
ae583885 | 778 | static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask) |
1da177e4 LT |
779 | { |
780 | u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff)); | |
1da177e4 | 781 | |
ae583885 DM |
782 | xcall_deliver(data0, data1, data2, mask); |
783 | } | |
1da177e4 | 784 | |
ae583885 DM |
785 | /* Send cross call to all processors except self. */ |
786 | static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2) | |
787 | { | |
fb1fece5 | 788 | smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask); |
1da177e4 LT |
789 | } |
790 | ||
791 | extern unsigned long xcall_sync_tick; | |
792 | ||
793 | static void smp_start_sync_tick_client(int cpu) | |
794 | { | |
24445a4a | 795 | xcall_deliver((u64) &xcall_sync_tick, 0, 0, |
fb1fece5 | 796 | cpumask_of(cpu)); |
1da177e4 LT |
797 | } |
798 | ||
1da177e4 LT |
799 | extern unsigned long xcall_call_function; |
800 | ||
f46df02a | 801 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 802 | { |
f46df02a | 803 | xcall_deliver((u64) &xcall_call_function, 0, 0, mask); |
d172ad18 | 804 | } |
1da177e4 | 805 | |
d172ad18 | 806 | extern unsigned long xcall_call_function_single; |
1da177e4 | 807 | |
d172ad18 DM |
808 | void arch_send_call_function_single_ipi(int cpu) |
809 | { | |
19926630 | 810 | xcall_deliver((u64) &xcall_call_function_single, 0, 0, |
fb1fece5 | 811 | cpumask_of(cpu)); |
1da177e4 LT |
812 | } |
813 | ||
9960e9e8 | 814 | void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs) |
1da177e4 | 815 | { |
d172ad18 DM |
816 | clear_softint(1 << irq); |
817 | generic_smp_call_function_interrupt(); | |
818 | } | |
1da177e4 | 819 | |
9960e9e8 | 820 | void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs) |
d172ad18 | 821 | { |
1da177e4 | 822 | clear_softint(1 << irq); |
d172ad18 | 823 | generic_smp_call_function_single_interrupt(); |
1da177e4 LT |
824 | } |
825 | ||
bd40791e DM |
826 | static void tsb_sync(void *info) |
827 | { | |
6f25f398 | 828 | struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()]; |
bd40791e DM |
829 | struct mm_struct *mm = info; |
830 | ||
42b2aa86 | 831 | /* It is not valid to test "current->active_mm == mm" here. |
6f25f398 DM |
832 | * |
833 | * The value of "current" is not changed atomically with | |
834 | * switch_mm(). But that's OK, we just need to check the | |
835 | * current cpu's trap block PGD physical address. | |
836 | */ | |
837 | if (tp->pgd_paddr == __pa(mm->pgd)) | |
bd40791e DM |
838 | tsb_context_switch(mm); |
839 | } | |
840 | ||
841 | void smp_tsb_sync(struct mm_struct *mm) | |
842 | { | |
81f1adf0 | 843 | smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1); |
bd40791e DM |
844 | } |
845 | ||
1da177e4 | 846 | extern unsigned long xcall_flush_tlb_mm; |
f36391d2 | 847 | extern unsigned long xcall_flush_tlb_page; |
1da177e4 | 848 | extern unsigned long xcall_flush_tlb_kernel_range; |
93dae5b7 | 849 | extern unsigned long xcall_fetch_glob_regs; |
916ca14a DM |
850 | extern unsigned long xcall_fetch_glob_pmu; |
851 | extern unsigned long xcall_fetch_glob_pmu_n4; | |
1da177e4 | 852 | extern unsigned long xcall_receive_signal; |
ee29074d | 853 | extern unsigned long xcall_new_mmu_context_version; |
e2fdd7fd DM |
854 | #ifdef CONFIG_KGDB |
855 | extern unsigned long xcall_kgdb_capture; | |
856 | #endif | |
1da177e4 LT |
857 | |
858 | #ifdef DCACHE_ALIASING_POSSIBLE | |
859 | extern unsigned long xcall_flush_dcache_page_cheetah; | |
860 | #endif | |
861 | extern unsigned long xcall_flush_dcache_page_spitfire; | |
862 | ||
863 | #ifdef CONFIG_DEBUG_DCFLUSH | |
864 | extern atomic_t dcpage_flushes; | |
865 | extern atomic_t dcpage_flushes_xcall; | |
866 | #endif | |
867 | ||
d979f179 | 868 | static inline void __local_flush_dcache_page(struct page *page) |
1da177e4 LT |
869 | { |
870 | #ifdef DCACHE_ALIASING_POSSIBLE | |
871 | __flush_dcache_page(page_address(page), | |
872 | ((tlb_type == spitfire) && | |
873 | page_mapping(page) != NULL)); | |
874 | #else | |
875 | if (page_mapping(page) != NULL && | |
876 | tlb_type == spitfire) | |
877 | __flush_icache_page(__pa(page_address(page))); | |
878 | #endif | |
879 | } | |
880 | ||
881 | void smp_flush_dcache_page_impl(struct page *page, int cpu) | |
882 | { | |
a43fe0e7 DM |
883 | int this_cpu; |
884 | ||
885 | if (tlb_type == hypervisor) | |
886 | return; | |
1da177e4 LT |
887 | |
888 | #ifdef CONFIG_DEBUG_DCFLUSH | |
889 | atomic_inc(&dcpage_flushes); | |
890 | #endif | |
a43fe0e7 DM |
891 | |
892 | this_cpu = get_cpu(); | |
893 | ||
1da177e4 LT |
894 | if (cpu == this_cpu) { |
895 | __local_flush_dcache_page(page); | |
896 | } else if (cpu_online(cpu)) { | |
897 | void *pg_addr = page_address(page); | |
622824db | 898 | u64 data0 = 0; |
1da177e4 LT |
899 | |
900 | if (tlb_type == spitfire) { | |
622824db | 901 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); |
1da177e4 LT |
902 | if (page_mapping(page) != NULL) |
903 | data0 |= ((u64)1 << 32); | |
a43fe0e7 | 904 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 | 905 | #ifdef DCACHE_ALIASING_POSSIBLE |
622824db | 906 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); |
1da177e4 LT |
907 | #endif |
908 | } | |
622824db DM |
909 | if (data0) { |
910 | xcall_deliver(data0, __pa(pg_addr), | |
fb1fece5 | 911 | (u64) pg_addr, cpumask_of(cpu)); |
1da177e4 | 912 | #ifdef CONFIG_DEBUG_DCFLUSH |
622824db | 913 | atomic_inc(&dcpage_flushes_xcall); |
1da177e4 | 914 | #endif |
622824db | 915 | } |
1da177e4 LT |
916 | } |
917 | ||
918 | put_cpu(); | |
919 | } | |
920 | ||
921 | void flush_dcache_page_all(struct mm_struct *mm, struct page *page) | |
922 | { | |
622824db | 923 | void *pg_addr; |
622824db | 924 | u64 data0; |
a43fe0e7 DM |
925 | |
926 | if (tlb_type == hypervisor) | |
927 | return; | |
928 | ||
c6fee081 | 929 | preempt_disable(); |
1da177e4 | 930 | |
1da177e4 LT |
931 | #ifdef CONFIG_DEBUG_DCFLUSH |
932 | atomic_inc(&dcpage_flushes); | |
933 | #endif | |
622824db DM |
934 | data0 = 0; |
935 | pg_addr = page_address(page); | |
1da177e4 LT |
936 | if (tlb_type == spitfire) { |
937 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); | |
938 | if (page_mapping(page) != NULL) | |
939 | data0 |= ((u64)1 << 32); | |
a43fe0e7 | 940 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
941 | #ifdef DCACHE_ALIASING_POSSIBLE |
942 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); | |
1da177e4 LT |
943 | #endif |
944 | } | |
622824db DM |
945 | if (data0) { |
946 | xcall_deliver(data0, __pa(pg_addr), | |
fb1fece5 | 947 | (u64) pg_addr, cpu_online_mask); |
1da177e4 | 948 | #ifdef CONFIG_DEBUG_DCFLUSH |
622824db | 949 | atomic_inc(&dcpage_flushes_xcall); |
1da177e4 | 950 | #endif |
622824db | 951 | } |
1da177e4 LT |
952 | __local_flush_dcache_page(page); |
953 | ||
c6fee081 | 954 | preempt_enable(); |
1da177e4 LT |
955 | } |
956 | ||
9960e9e8 | 957 | void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs) |
1da177e4 | 958 | { |
a0663a79 | 959 | struct mm_struct *mm; |
ee29074d | 960 | unsigned long flags; |
a0663a79 | 961 | |
1da177e4 | 962 | clear_softint(1 << irq); |
a0663a79 DM |
963 | |
964 | /* See if we need to allocate a new TLB context because | |
965 | * the version of the one we are using is now out of date. | |
966 | */ | |
967 | mm = current->active_mm; | |
ee29074d DM |
968 | if (unlikely(!mm || (mm == &init_mm))) |
969 | return; | |
a0663a79 | 970 | |
ee29074d | 971 | spin_lock_irqsave(&mm->context.lock, flags); |
aac0aadf | 972 | |
ee29074d DM |
973 | if (unlikely(!CTX_VALID(mm->context))) |
974 | get_new_mmu_context(mm); | |
aac0aadf | 975 | |
ee29074d | 976 | spin_unlock_irqrestore(&mm->context.lock, flags); |
aac0aadf | 977 | |
ee29074d DM |
978 | load_secondary_context(mm); |
979 | __flush_tlb_mm(CTX_HWBITS(mm->context), | |
980 | SECONDARY_CONTEXT); | |
a0663a79 DM |
981 | } |
982 | ||
983 | void smp_new_mmu_context_version(void) | |
984 | { | |
ee29074d | 985 | smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0); |
1da177e4 LT |
986 | } |
987 | ||
e2fdd7fd DM |
988 | #ifdef CONFIG_KGDB |
989 | void kgdb_roundup_cpus(unsigned long flags) | |
990 | { | |
991 | smp_cross_call(&xcall_kgdb_capture, 0, 0, 0); | |
992 | } | |
993 | #endif | |
994 | ||
93dae5b7 DM |
995 | void smp_fetch_global_regs(void) |
996 | { | |
997 | smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0); | |
998 | } | |
93dae5b7 | 999 | |
916ca14a DM |
1000 | void smp_fetch_global_pmu(void) |
1001 | { | |
1002 | if (tlb_type == hypervisor && | |
1003 | sun4v_chip_type >= SUN4V_CHIP_NIAGARA4) | |
1004 | smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0); | |
1005 | else | |
1006 | smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0); | |
1007 | } | |
1008 | ||
1da177e4 LT |
1009 | /* We know that the window frames of the user have been flushed |
1010 | * to the stack before we get here because all callers of us | |
1011 | * are flush_tlb_*() routines, and these run after flush_cache_*() | |
1012 | * which performs the flushw. | |
1013 | * | |
1014 | * The SMP TLB coherency scheme we use works as follows: | |
1015 | * | |
1016 | * 1) mm->cpu_vm_mask is a bit mask of which cpus an address | |
1017 | * space has (potentially) executed on, this is the heuristic | |
1018 | * we use to avoid doing cross calls. | |
1019 | * | |
1020 | * Also, for flushing from kswapd and also for clones, we | |
1021 | * use cpu_vm_mask as the list of cpus to make run the TLB. | |
1022 | * | |
1023 | * 2) TLB context numbers are shared globally across all processors | |
1024 | * in the system, this allows us to play several games to avoid | |
1025 | * cross calls. | |
1026 | * | |
1027 | * One invariant is that when a cpu switches to a process, and | |
1028 | * that processes tsk->active_mm->cpu_vm_mask does not have the | |
1029 | * current cpu's bit set, that tlb context is flushed locally. | |
1030 | * | |
1031 | * If the address space is non-shared (ie. mm->count == 1) we avoid | |
1032 | * cross calls when we want to flush the currently running process's | |
1033 | * tlb state. This is done by clearing all cpu bits except the current | |
f9384d41 | 1034 | * processor's in current->mm->cpu_vm_mask and performing the |
1da177e4 LT |
1035 | * flush locally only. This will force any subsequent cpus which run |
1036 | * this task to flush the context from the local tlb if the process | |
1037 | * migrates to another cpu (again). | |
1038 | * | |
1039 | * 3) For shared address spaces (threads) and swapping we bite the | |
1040 | * bullet for most cases and perform the cross call (but only to | |
1041 | * the cpus listed in cpu_vm_mask). | |
1042 | * | |
1043 | * The performance gain from "optimizing" away the cross call for threads is | |
1044 | * questionable (in theory the big win for threads is the massive sharing of | |
1045 | * address space state across processors). | |
1046 | */ | |
62dbec78 DM |
1047 | |
1048 | /* This currently is only used by the hugetlb arch pre-fault | |
1049 | * hook on UltraSPARC-III+ and later when changing the pagesize | |
1050 | * bits of the context register for an address space. | |
1051 | */ | |
1da177e4 LT |
1052 | void smp_flush_tlb_mm(struct mm_struct *mm) |
1053 | { | |
62dbec78 DM |
1054 | u32 ctx = CTX_HWBITS(mm->context); |
1055 | int cpu = get_cpu(); | |
1da177e4 | 1056 | |
62dbec78 | 1057 | if (atomic_read(&mm->mm_users) == 1) { |
81f1adf0 | 1058 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); |
62dbec78 DM |
1059 | goto local_flush_and_out; |
1060 | } | |
1da177e4 | 1061 | |
62dbec78 DM |
1062 | smp_cross_call_masked(&xcall_flush_tlb_mm, |
1063 | ctx, 0, 0, | |
81f1adf0 | 1064 | mm_cpumask(mm)); |
1da177e4 | 1065 | |
62dbec78 DM |
1066 | local_flush_and_out: |
1067 | __flush_tlb_mm(ctx, SECONDARY_CONTEXT); | |
1da177e4 | 1068 | |
62dbec78 | 1069 | put_cpu(); |
1da177e4 LT |
1070 | } |
1071 | ||
f36391d2 DM |
1072 | struct tlb_pending_info { |
1073 | unsigned long ctx; | |
1074 | unsigned long nr; | |
1075 | unsigned long *vaddrs; | |
1076 | }; | |
1077 | ||
1078 | static void tlb_pending_func(void *info) | |
1079 | { | |
1080 | struct tlb_pending_info *t = info; | |
1081 | ||
1082 | __flush_tlb_pending(t->ctx, t->nr, t->vaddrs); | |
1083 | } | |
1084 | ||
1da177e4 LT |
1085 | void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs) |
1086 | { | |
1087 | u32 ctx = CTX_HWBITS(mm->context); | |
f36391d2 | 1088 | struct tlb_pending_info info; |
1da177e4 LT |
1089 | int cpu = get_cpu(); |
1090 | ||
f36391d2 DM |
1091 | info.ctx = ctx; |
1092 | info.nr = nr; | |
1093 | info.vaddrs = vaddrs; | |
1094 | ||
f9384d41 | 1095 | if (mm == current->mm && atomic_read(&mm->mm_users) == 1) |
81f1adf0 | 1096 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); |
dedeb002 | 1097 | else |
f36391d2 DM |
1098 | smp_call_function_many(mm_cpumask(mm), tlb_pending_func, |
1099 | &info, 1); | |
1da177e4 | 1100 | |
1da177e4 LT |
1101 | __flush_tlb_pending(ctx, nr, vaddrs); |
1102 | ||
1103 | put_cpu(); | |
1104 | } | |
1105 | ||
f36391d2 DM |
1106 | void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr) |
1107 | { | |
1108 | unsigned long context = CTX_HWBITS(mm->context); | |
1109 | int cpu = get_cpu(); | |
1110 | ||
1111 | if (mm == current->mm && atomic_read(&mm->mm_users) == 1) | |
1112 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); | |
1113 | else | |
1114 | smp_cross_call_masked(&xcall_flush_tlb_page, | |
1115 | context, vaddr, 0, | |
1116 | mm_cpumask(mm)); | |
1117 | __flush_tlb_page(context, vaddr); | |
1118 | ||
1119 | put_cpu(); | |
1120 | } | |
1121 | ||
1da177e4 LT |
1122 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end) |
1123 | { | |
1124 | start &= PAGE_MASK; | |
1125 | end = PAGE_ALIGN(end); | |
1126 | if (start != end) { | |
1127 | smp_cross_call(&xcall_flush_tlb_kernel_range, | |
1128 | 0, start, end); | |
1129 | ||
1130 | __flush_tlb_kernel_range(start, end); | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | /* CPU capture. */ | |
1135 | /* #define CAPTURE_DEBUG */ | |
1136 | extern unsigned long xcall_capture; | |
1137 | ||
1138 | static atomic_t smp_capture_depth = ATOMIC_INIT(0); | |
1139 | static atomic_t smp_capture_registry = ATOMIC_INIT(0); | |
1140 | static unsigned long penguins_are_doing_time; | |
1141 | ||
1142 | void smp_capture(void) | |
1143 | { | |
1144 | int result = atomic_add_ret(1, &smp_capture_depth); | |
1145 | ||
1146 | if (result == 1) { | |
1147 | int ncpus = num_online_cpus(); | |
1148 | ||
1149 | #ifdef CAPTURE_DEBUG | |
1150 | printk("CPU[%d]: Sending penguins to jail...", | |
1151 | smp_processor_id()); | |
1152 | #endif | |
1153 | penguins_are_doing_time = 1; | |
1da177e4 LT |
1154 | atomic_inc(&smp_capture_registry); |
1155 | smp_cross_call(&xcall_capture, 0, 0, 0); | |
1156 | while (atomic_read(&smp_capture_registry) != ncpus) | |
4f07118f | 1157 | rmb(); |
1da177e4 LT |
1158 | #ifdef CAPTURE_DEBUG |
1159 | printk("done\n"); | |
1160 | #endif | |
1161 | } | |
1162 | } | |
1163 | ||
1164 | void smp_release(void) | |
1165 | { | |
1166 | if (atomic_dec_and_test(&smp_capture_depth)) { | |
1167 | #ifdef CAPTURE_DEBUG | |
1168 | printk("CPU[%d]: Giving pardon to " | |
1169 | "imprisoned penguins\n", | |
1170 | smp_processor_id()); | |
1171 | #endif | |
1172 | penguins_are_doing_time = 0; | |
293666b7 | 1173 | membar_safe("#StoreLoad"); |
1da177e4 LT |
1174 | atomic_dec(&smp_capture_registry); |
1175 | } | |
1176 | } | |
1177 | ||
b4f4372f DM |
1178 | /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE |
1179 | * set, so they can service tlb flush xcalls... | |
1da177e4 LT |
1180 | */ |
1181 | extern void prom_world(int); | |
96c6e0d8 | 1182 | |
9960e9e8 | 1183 | void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs) |
1da177e4 | 1184 | { |
1da177e4 LT |
1185 | clear_softint(1 << irq); |
1186 | ||
1187 | preempt_disable(); | |
1188 | ||
1189 | __asm__ __volatile__("flushw"); | |
1da177e4 LT |
1190 | prom_world(1); |
1191 | atomic_inc(&smp_capture_registry); | |
293666b7 | 1192 | membar_safe("#StoreLoad"); |
1da177e4 | 1193 | while (penguins_are_doing_time) |
4f07118f | 1194 | rmb(); |
1da177e4 LT |
1195 | atomic_dec(&smp_capture_registry); |
1196 | prom_world(0); | |
1197 | ||
1198 | preempt_enable(); | |
1199 | } | |
1200 | ||
1da177e4 | 1201 | /* /proc/profile writes can call this, don't __init it please. */ |
1da177e4 LT |
1202 | int setup_profiling_timer(unsigned int multiplier) |
1203 | { | |
777a4475 | 1204 | return -EINVAL; |
1da177e4 LT |
1205 | } |
1206 | ||
1207 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1208 | { | |
1da177e4 LT |
1209 | } |
1210 | ||
7c9503b8 | 1211 | void smp_prepare_boot_cpu(void) |
7abea921 | 1212 | { |
7abea921 DM |
1213 | } |
1214 | ||
5e0797e5 DM |
1215 | void __init smp_setup_processor_id(void) |
1216 | { | |
1217 | if (tlb_type == spitfire) | |
deb16999 | 1218 | xcall_deliver_impl = spitfire_xcall_deliver; |
5e0797e5 | 1219 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
deb16999 | 1220 | xcall_deliver_impl = cheetah_xcall_deliver; |
5e0797e5 | 1221 | else |
deb16999 | 1222 | xcall_deliver_impl = hypervisor_xcall_deliver; |
5e0797e5 DM |
1223 | } |
1224 | ||
7c9503b8 | 1225 | void smp_fill_in_sib_core_maps(void) |
1da177e4 | 1226 | { |
5cbc3073 DM |
1227 | unsigned int i; |
1228 | ||
e0204409 | 1229 | for_each_present_cpu(i) { |
5cbc3073 DM |
1230 | unsigned int j; |
1231 | ||
fb1fece5 | 1232 | cpumask_clear(&cpu_core_map[i]); |
5cbc3073 | 1233 | if (cpu_data(i).core_id == 0) { |
fb1fece5 | 1234 | cpumask_set_cpu(i, &cpu_core_map[i]); |
5cbc3073 DM |
1235 | continue; |
1236 | } | |
1237 | ||
e0204409 | 1238 | for_each_present_cpu(j) { |
5cbc3073 DM |
1239 | if (cpu_data(i).core_id == |
1240 | cpu_data(j).core_id) | |
fb1fece5 | 1241 | cpumask_set_cpu(j, &cpu_core_map[i]); |
f78eae2e DM |
1242 | } |
1243 | } | |
1244 | ||
e0204409 | 1245 | for_each_present_cpu(i) { |
f78eae2e DM |
1246 | unsigned int j; |
1247 | ||
fb1fece5 | 1248 | cpumask_clear(&per_cpu(cpu_sibling_map, i)); |
f78eae2e | 1249 | if (cpu_data(i).proc_id == -1) { |
fb1fece5 | 1250 | cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i)); |
f78eae2e DM |
1251 | continue; |
1252 | } | |
1253 | ||
e0204409 | 1254 | for_each_present_cpu(j) { |
f78eae2e DM |
1255 | if (cpu_data(i).proc_id == |
1256 | cpu_data(j).proc_id) | |
fb1fece5 | 1257 | cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i)); |
5cbc3073 DM |
1258 | } |
1259 | } | |
1da177e4 LT |
1260 | } |
1261 | ||
2066aadd | 1262 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 1263 | { |
f0a2bc7e | 1264 | int ret = smp_boot_one_cpu(cpu, tidle); |
1da177e4 LT |
1265 | |
1266 | if (!ret) { | |
fb1fece5 KM |
1267 | cpumask_set_cpu(cpu, &smp_commenced_mask); |
1268 | while (!cpu_online(cpu)) | |
1da177e4 | 1269 | mb(); |
fb1fece5 | 1270 | if (!cpu_online(cpu)) { |
1da177e4 LT |
1271 | ret = -ENODEV; |
1272 | } else { | |
02fead75 DM |
1273 | /* On SUN4V, writes to %tick and %stick are |
1274 | * not allowed. | |
1275 | */ | |
1276 | if (tlb_type != hypervisor) | |
1277 | smp_synchronize_one_tick(cpu); | |
1da177e4 LT |
1278 | } |
1279 | } | |
1280 | return ret; | |
1281 | } | |
1282 | ||
4f0234f4 | 1283 | #ifdef CONFIG_HOTPLUG_CPU |
e0204409 DM |
1284 | void cpu_play_dead(void) |
1285 | { | |
1286 | int cpu = smp_processor_id(); | |
1287 | unsigned long pstate; | |
1288 | ||
1289 | idle_task_exit(); | |
1290 | ||
1291 | if (tlb_type == hypervisor) { | |
1292 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1293 | ||
1294 | sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO, | |
1295 | tb->cpu_mondo_pa, 0); | |
1296 | sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO, | |
1297 | tb->dev_mondo_pa, 0); | |
1298 | sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR, | |
1299 | tb->resum_mondo_pa, 0); | |
1300 | sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR, | |
1301 | tb->nonresum_mondo_pa, 0); | |
1302 | } | |
1303 | ||
fb1fece5 | 1304 | cpumask_clear_cpu(cpu, &smp_commenced_mask); |
e0204409 DM |
1305 | membar_safe("#Sync"); |
1306 | ||
1307 | local_irq_disable(); | |
1308 | ||
1309 | __asm__ __volatile__( | |
1310 | "rdpr %%pstate, %0\n\t" | |
1311 | "wrpr %0, %1, %%pstate" | |
1312 | : "=r" (pstate) | |
1313 | : "i" (PSTATE_IE)); | |
1314 | ||
1315 | while (1) | |
1316 | barrier(); | |
1317 | } | |
1318 | ||
4f0234f4 DM |
1319 | int __cpu_disable(void) |
1320 | { | |
e0204409 DM |
1321 | int cpu = smp_processor_id(); |
1322 | cpuinfo_sparc *c; | |
1323 | int i; | |
1324 | ||
fb1fece5 KM |
1325 | for_each_cpu(i, &cpu_core_map[cpu]) |
1326 | cpumask_clear_cpu(cpu, &cpu_core_map[i]); | |
1327 | cpumask_clear(&cpu_core_map[cpu]); | |
e0204409 | 1328 | |
fb1fece5 KM |
1329 | for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu)) |
1330 | cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i)); | |
1331 | cpumask_clear(&per_cpu(cpu_sibling_map, cpu)); | |
e0204409 DM |
1332 | |
1333 | c = &cpu_data(cpu); | |
1334 | ||
1335 | c->core_id = 0; | |
1336 | c->proc_id = -1; | |
1337 | ||
e0204409 DM |
1338 | smp_wmb(); |
1339 | ||
1340 | /* Make sure no interrupts point to this cpu. */ | |
1341 | fixup_irqs(); | |
1342 | ||
1343 | local_irq_enable(); | |
1344 | mdelay(1); | |
1345 | local_irq_disable(); | |
1346 | ||
fb1fece5 | 1347 | set_cpu_online(cpu, false); |
4d084617 | 1348 | |
280ff974 HP |
1349 | cpu_map_rebuild(); |
1350 | ||
e0204409 | 1351 | return 0; |
4f0234f4 DM |
1352 | } |
1353 | ||
1354 | void __cpu_die(unsigned int cpu) | |
1355 | { | |
e0204409 DM |
1356 | int i; |
1357 | ||
1358 | for (i = 0; i < 100; i++) { | |
1359 | smp_rmb(); | |
fb1fece5 | 1360 | if (!cpumask_test_cpu(cpu, &smp_commenced_mask)) |
e0204409 DM |
1361 | break; |
1362 | msleep(100); | |
1363 | } | |
fb1fece5 | 1364 | if (cpumask_test_cpu(cpu, &smp_commenced_mask)) { |
e0204409 DM |
1365 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1366 | } else { | |
1367 | #if defined(CONFIG_SUN_LDOMS) | |
1368 | unsigned long hv_err; | |
1369 | int limit = 100; | |
1370 | ||
1371 | do { | |
1372 | hv_err = sun4v_cpu_stop(cpu); | |
1373 | if (hv_err == HV_EOK) { | |
fb1fece5 | 1374 | set_cpu_present(cpu, false); |
e0204409 DM |
1375 | break; |
1376 | } | |
1377 | } while (--limit > 0); | |
1378 | if (limit <= 0) { | |
1379 | printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n", | |
1380 | hv_err); | |
1381 | } | |
1382 | #endif | |
1383 | } | |
4f0234f4 DM |
1384 | } |
1385 | #endif | |
1386 | ||
1da177e4 LT |
1387 | void __init smp_cpus_done(unsigned int max_cpus) |
1388 | { | |
b62818e5 | 1389 | pcr_arch_init(); |
1da177e4 LT |
1390 | } |
1391 | ||
1da177e4 LT |
1392 | void smp_send_reschedule(int cpu) |
1393 | { | |
1a36265b KT |
1394 | if (cpu == smp_processor_id()) { |
1395 | WARN_ON_ONCE(preemptible()); | |
1396 | set_softint(1 << PIL_SMP_RECEIVE_SIGNAL); | |
1397 | } else { | |
1398 | xcall_deliver((u64) &xcall_receive_signal, | |
1399 | 0, 0, cpumask_of(cpu)); | |
1400 | } | |
19926630 DM |
1401 | } |
1402 | ||
9960e9e8 | 1403 | void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs) |
19926630 DM |
1404 | { |
1405 | clear_softint(1 << irq); | |
184748cc | 1406 | scheduler_ipi(); |
1da177e4 LT |
1407 | } |
1408 | ||
1409 | /* This is a nop because we capture all other cpus | |
1410 | * anyways when making the PROM active. | |
1411 | */ | |
1412 | void smp_send_stop(void) | |
1413 | { | |
1414 | } | |
1415 | ||
4fd78a5f DM |
1416 | /** |
1417 | * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu | |
1418 | * @cpu: cpu to allocate for | |
1419 | * @size: size allocation in bytes | |
1420 | * @align: alignment | |
1421 | * | |
1422 | * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper | |
1423 | * does the right thing for NUMA regardless of the current | |
1424 | * configuration. | |
1425 | * | |
1426 | * RETURNS: | |
1427 | * Pointer to the allocated area on success, NULL on failure. | |
1428 | */ | |
bcb2107f TH |
1429 | static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size, |
1430 | size_t align) | |
4fd78a5f DM |
1431 | { |
1432 | const unsigned long goal = __pa(MAX_DMA_ADDRESS); | |
1433 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
1434 | int node = cpu_to_node(cpu); | |
1435 | void *ptr; | |
1436 | ||
1437 | if (!node_online(node) || !NODE_DATA(node)) { | |
1438 | ptr = __alloc_bootmem(size, align, goal); | |
1439 | pr_info("cpu %d has no node %d or node-local memory\n", | |
1440 | cpu, node); | |
1441 | pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n", | |
1442 | cpu, size, __pa(ptr)); | |
1443 | } else { | |
1444 | ptr = __alloc_bootmem_node(NODE_DATA(node), | |
1445 | size, align, goal); | |
1446 | pr_debug("per cpu data for cpu%d %lu bytes on node%d at " | |
1447 | "%016lx\n", cpu, size, node, __pa(ptr)); | |
1448 | } | |
1449 | return ptr; | |
1450 | #else | |
1451 | return __alloc_bootmem(size, align, goal); | |
1452 | #endif | |
1453 | } | |
1454 | ||
bcb2107f | 1455 | static void __init pcpu_free_bootmem(void *ptr, size_t size) |
4fd78a5f | 1456 | { |
bcb2107f TH |
1457 | free_bootmem(__pa(ptr), size); |
1458 | } | |
4fd78a5f | 1459 | |
a70c6913 | 1460 | static int __init pcpu_cpu_distance(unsigned int from, unsigned int to) |
bcb2107f TH |
1461 | { |
1462 | if (cpu_to_node(from) == cpu_to_node(to)) | |
1463 | return LOCAL_DISTANCE; | |
1464 | else | |
1465 | return REMOTE_DISTANCE; | |
4fd78a5f DM |
1466 | } |
1467 | ||
a70c6913 TH |
1468 | static void __init pcpu_populate_pte(unsigned long addr) |
1469 | { | |
1470 | pgd_t *pgd = pgd_offset_k(addr); | |
1471 | pud_t *pud; | |
1472 | pmd_t *pmd; | |
1473 | ||
1474 | pud = pud_offset(pgd, addr); | |
1475 | if (pud_none(*pud)) { | |
1476 | pmd_t *new; | |
1477 | ||
1478 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1479 | pud_populate(&init_mm, pud, new); | |
1480 | } | |
1481 | ||
1482 | pmd = pmd_offset(pud, addr); | |
1483 | if (!pmd_present(*pmd)) { | |
1484 | pte_t *new; | |
1485 | ||
1486 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1487 | pmd_populate_kernel(&init_mm, pmd, new); | |
1488 | } | |
1489 | } | |
1490 | ||
73fffc03 | 1491 | void __init setup_per_cpu_areas(void) |
1da177e4 | 1492 | { |
bcb2107f TH |
1493 | unsigned long delta; |
1494 | unsigned int cpu; | |
a70c6913 TH |
1495 | int rc = -EINVAL; |
1496 | ||
1497 | if (pcpu_chosen_fc != PCPU_FC_PAGE) { | |
1498 | rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE, | |
1499 | PERCPU_DYNAMIC_RESERVE, 4 << 20, | |
1500 | pcpu_cpu_distance, | |
1501 | pcpu_alloc_bootmem, | |
1502 | pcpu_free_bootmem); | |
1503 | if (rc) | |
1504 | pr_warning("PERCPU: %s allocator failed (%d), " | |
1505 | "falling back to page size\n", | |
1506 | pcpu_fc_names[pcpu_chosen_fc], rc); | |
1507 | } | |
1508 | if (rc < 0) | |
1509 | rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE, | |
1510 | pcpu_alloc_bootmem, | |
1511 | pcpu_free_bootmem, | |
1512 | pcpu_populate_pte); | |
1513 | if (rc < 0) | |
1514 | panic("cannot initialize percpu area (err=%d)", rc); | |
5a089006 | 1515 | |
4fd78a5f | 1516 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; |
fb435d52 TH |
1517 | for_each_possible_cpu(cpu) |
1518 | __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu]; | |
951bc82c DM |
1519 | |
1520 | /* Setup %g5 for the boot cpu. */ | |
1521 | __local_per_cpu_offset = __per_cpu_offset(smp_processor_id()); | |
b696fdc2 DM |
1522 | |
1523 | of_fill_in_cpu_data(); | |
1524 | if (tlb_type == hypervisor) | |
6ac5c610 | 1525 | mdesc_fill_in_cpu_data(cpu_all_mask); |
1da177e4 | 1526 | } |