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Commit | Line | Data |
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1da177e4 LT |
1 | /* smp.c: Sparc64 SMP support. |
2 | * | |
cf3d7c1e | 3 | * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | */ |
5 | ||
066bcaca | 6 | #include <linux/export.h> |
1da177e4 | 7 | #include <linux/kernel.h> |
68e21be2 | 8 | #include <linux/sched/mm.h> |
ef8bd77f | 9 | #include <linux/sched/hotplug.h> |
1da177e4 LT |
10 | #include <linux/mm.h> |
11 | #include <linux/pagemap.h> | |
12 | #include <linux/threads.h> | |
13 | #include <linux/smp.h> | |
1da177e4 LT |
14 | #include <linux/interrupt.h> |
15 | #include <linux/kernel_stat.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/spinlock.h> | |
19 | #include <linux/fs.h> | |
20 | #include <linux/seq_file.h> | |
21 | #include <linux/cache.h> | |
22 | #include <linux/jiffies.h> | |
23 | #include <linux/profile.h> | |
73fffc03 | 24 | #include <linux/bootmem.h> |
4fd78a5f | 25 | #include <linux/vmalloc.h> |
9960e9e8 | 26 | #include <linux/ftrace.h> |
82960b85 | 27 | #include <linux/cpu.h> |
5a0e3ad6 | 28 | #include <linux/slab.h> |
d3091298 | 29 | #include <linux/kgdb.h> |
1da177e4 LT |
30 | |
31 | #include <asm/head.h> | |
32 | #include <asm/ptrace.h> | |
60063497 | 33 | #include <linux/atomic.h> |
1da177e4 LT |
34 | #include <asm/tlbflush.h> |
35 | #include <asm/mmu_context.h> | |
36 | #include <asm/cpudata.h> | |
27a2ef38 DM |
37 | #include <asm/hvtramp.h> |
38 | #include <asm/io.h> | |
cf3d7c1e | 39 | #include <asm/timer.h> |
59dec13b | 40 | #include <asm/setup.h> |
1da177e4 LT |
41 | |
42 | #include <asm/irq.h> | |
6d24c8dc | 43 | #include <asm/irq_regs.h> |
1da177e4 LT |
44 | #include <asm/page.h> |
45 | #include <asm/pgtable.h> | |
46 | #include <asm/oplib.h> | |
7c0f6ba6 | 47 | #include <linux/uaccess.h> |
1da177e4 LT |
48 | #include <asm/starfire.h> |
49 | #include <asm/tlb.h> | |
56fb4df6 | 50 | #include <asm/sections.h> |
07f8e5f3 | 51 | #include <asm/prom.h> |
5cbc3073 | 52 | #include <asm/mdesc.h> |
4f0234f4 | 53 | #include <asm/ldc.h> |
e0204409 | 54 | #include <asm/hypervisor.h> |
b62818e5 | 55 | #include <asm/pcr.h> |
1da177e4 | 56 | |
280ff974 | 57 | #include "cpumap.h" |
a0c54a21 | 58 | #include "kernel.h" |
280ff974 | 59 | |
d5a7430d | 60 | DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE; |
f78eae2e DM |
61 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly = |
62 | { [0 ... NR_CPUS-1] = CPU_MASK_NONE }; | |
4f0234f4 | 63 | |
acc455cf | 64 | cpumask_t cpu_core_sib_map[NR_CPUS] __read_mostly = { |
65 | [0 ... NR_CPUS-1] = CPU_MASK_NONE }; | |
66 | ||
d624716b AP |
67 | cpumask_t cpu_core_sib_cache_map[NR_CPUS] __read_mostly = { |
68 | [0 ... NR_CPUS - 1] = CPU_MASK_NONE }; | |
69 | ||
d5a7430d | 70 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
4f0234f4 | 71 | EXPORT_SYMBOL(cpu_core_map); |
acc455cf | 72 | EXPORT_SYMBOL(cpu_core_sib_map); |
d624716b | 73 | EXPORT_SYMBOL(cpu_core_sib_cache_map); |
4f0234f4 | 74 | |
1da177e4 | 75 | static cpumask_t smp_commenced_mask; |
1da177e4 LT |
76 | |
77 | void smp_info(struct seq_file *m) | |
78 | { | |
79 | int i; | |
80 | ||
81 | seq_printf(m, "State:\n"); | |
394e3902 AM |
82 | for_each_online_cpu(i) |
83 | seq_printf(m, "CPU%d:\t\tonline\n", i); | |
1da177e4 LT |
84 | } |
85 | ||
86 | void smp_bogo(struct seq_file *m) | |
87 | { | |
88 | int i; | |
89 | ||
394e3902 AM |
90 | for_each_online_cpu(i) |
91 | seq_printf(m, | |
394e3902 | 92 | "Cpu%dClkTck\t: %016lx\n", |
394e3902 | 93 | i, cpu_data(i).clock_tick); |
1da177e4 LT |
94 | } |
95 | ||
112f4871 | 96 | extern void setup_sparc64_timer(void); |
1da177e4 LT |
97 | |
98 | static volatile unsigned long callin_flag = 0; | |
99 | ||
2066aadd | 100 | void smp_callin(void) |
1da177e4 LT |
101 | { |
102 | int cpuid = hard_smp_processor_id(); | |
103 | ||
56fb4df6 | 104 | __local_per_cpu_offset = __per_cpu_offset(cpuid); |
1da177e4 | 105 | |
4a07e646 | 106 | if (tlb_type == hypervisor) |
490384e7 | 107 | sun4v_ktsb_register(); |
481295f9 | 108 | |
56fb4df6 | 109 | __flush_tlb_all(); |
1da177e4 | 110 | |
112f4871 | 111 | setup_sparc64_timer(); |
1da177e4 | 112 | |
816242da DM |
113 | if (cheetah_pcache_forced_on) |
114 | cheetah_enable_pcache(); | |
115 | ||
1da177e4 LT |
116 | callin_flag = 1; |
117 | __asm__ __volatile__("membar #Sync\n\t" | |
118 | "flush %%g6" : : : "memory"); | |
119 | ||
120 | /* Clear this or we will die instantly when we | |
121 | * schedule back to this idler... | |
122 | */ | |
db7d9a4e | 123 | current_thread_info()->new_child = 0; |
1da177e4 LT |
124 | |
125 | /* Attach to the address space of init_task. */ | |
f1f10076 | 126 | mmgrab(&init_mm); |
1da177e4 LT |
127 | current->active_mm = &init_mm; |
128 | ||
82960b85 DM |
129 | /* inform the notifiers about the new cpu */ |
130 | notify_cpu_starting(cpuid); | |
131 | ||
fb1fece5 | 132 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
4f07118f | 133 | rmb(); |
1da177e4 | 134 | |
fb1fece5 | 135 | set_cpu_online(cpuid, true); |
5bfb5d69 NP |
136 | |
137 | /* idle thread is expected to have preempt disabled */ | |
138 | preempt_disable(); | |
87fa05ae | 139 | |
ce2521bf KT |
140 | local_irq_enable(); |
141 | ||
fc6d73d6 | 142 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
1da177e4 LT |
143 | } |
144 | ||
145 | void cpu_panic(void) | |
146 | { | |
147 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
148 | panic("SMP bolixed\n"); | |
149 | } | |
150 | ||
1da177e4 LT |
151 | /* This tick register synchronization scheme is taken entirely from |
152 | * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit. | |
153 | * | |
154 | * The only change I've made is to rework it so that the master | |
155 | * initiates the synchonization instead of the slave. -DaveM | |
156 | */ | |
157 | ||
158 | #define MASTER 0 | |
159 | #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long)) | |
160 | ||
161 | #define NUM_ROUNDS 64 /* magic value */ | |
162 | #define NUM_ITERS 5 /* likewise */ | |
163 | ||
49b6c01f | 164 | static DEFINE_RAW_SPINLOCK(itc_sync_lock); |
1da177e4 LT |
165 | static unsigned long go[SLAVE + 1]; |
166 | ||
167 | #define DEBUG_TICK_SYNC 0 | |
168 | ||
169 | static inline long get_delta (long *rt, long *master) | |
170 | { | |
171 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; | |
172 | unsigned long tcenter, t0, t1, tm; | |
173 | unsigned long i; | |
174 | ||
175 | for (i = 0; i < NUM_ITERS; i++) { | |
176 | t0 = tick_ops->get_tick(); | |
177 | go[MASTER] = 1; | |
293666b7 | 178 | membar_safe("#StoreLoad"); |
1da177e4 | 179 | while (!(tm = go[SLAVE])) |
4f07118f | 180 | rmb(); |
1da177e4 | 181 | go[SLAVE] = 0; |
4f07118f | 182 | wmb(); |
1da177e4 LT |
183 | t1 = tick_ops->get_tick(); |
184 | ||
185 | if (t1 - t0 < best_t1 - best_t0) | |
186 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
187 | } | |
188 | ||
189 | *rt = best_t1 - best_t0; | |
190 | *master = best_tm - best_t0; | |
191 | ||
192 | /* average best_t0 and best_t1 without overflow: */ | |
193 | tcenter = (best_t0/2 + best_t1/2); | |
194 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
195 | tcenter++; | |
196 | return tcenter - best_tm; | |
197 | } | |
198 | ||
199 | void smp_synchronize_tick_client(void) | |
200 | { | |
201 | long i, delta, adj, adjust_latency = 0, done = 0; | |
c6fee081 | 202 | unsigned long flags, rt, master_time_stamp; |
1da177e4 LT |
203 | #if DEBUG_TICK_SYNC |
204 | struct { | |
205 | long rt; /* roundtrip time */ | |
206 | long master; /* master's timestamp */ | |
207 | long diff; /* difference between midpoint and master's timestamp */ | |
208 | long lat; /* estimate of itc adjustment latency */ | |
209 | } t[NUM_ROUNDS]; | |
210 | #endif | |
211 | ||
212 | go[MASTER] = 1; | |
213 | ||
214 | while (go[MASTER]) | |
4f07118f | 215 | rmb(); |
1da177e4 LT |
216 | |
217 | local_irq_save(flags); | |
218 | { | |
219 | for (i = 0; i < NUM_ROUNDS; i++) { | |
220 | delta = get_delta(&rt, &master_time_stamp); | |
c6fee081 | 221 | if (delta == 0) |
1da177e4 | 222 | done = 1; /* let's lock on to this... */ |
1da177e4 LT |
223 | |
224 | if (!done) { | |
225 | if (i > 0) { | |
226 | adjust_latency += -delta; | |
227 | adj = -delta + adjust_latency/4; | |
228 | } else | |
229 | adj = -delta; | |
230 | ||
112f4871 | 231 | tick_ops->add_tick(adj); |
1da177e4 LT |
232 | } |
233 | #if DEBUG_TICK_SYNC | |
234 | t[i].rt = rt; | |
235 | t[i].master = master_time_stamp; | |
236 | t[i].diff = delta; | |
237 | t[i].lat = adjust_latency/4; | |
238 | #endif | |
239 | } | |
240 | } | |
241 | local_irq_restore(flags); | |
242 | ||
243 | #if DEBUG_TICK_SYNC | |
244 | for (i = 0; i < NUM_ROUNDS; i++) | |
245 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
246 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
247 | #endif | |
248 | ||
519c4d2d JP |
249 | printk(KERN_INFO "CPU %d: synchronized TICK with master CPU " |
250 | "(last diff %ld cycles, maxerr %lu cycles)\n", | |
251 | smp_processor_id(), delta, rt); | |
1da177e4 LT |
252 | } |
253 | ||
254 | static void smp_start_sync_tick_client(int cpu); | |
255 | ||
256 | static void smp_synchronize_one_tick(int cpu) | |
257 | { | |
258 | unsigned long flags, i; | |
259 | ||
260 | go[MASTER] = 0; | |
261 | ||
262 | smp_start_sync_tick_client(cpu); | |
263 | ||
264 | /* wait for client to be ready */ | |
265 | while (!go[MASTER]) | |
4f07118f | 266 | rmb(); |
1da177e4 LT |
267 | |
268 | /* now let the client proceed into his loop */ | |
269 | go[MASTER] = 0; | |
293666b7 | 270 | membar_safe("#StoreLoad"); |
1da177e4 | 271 | |
49b6c01f | 272 | raw_spin_lock_irqsave(&itc_sync_lock, flags); |
1da177e4 LT |
273 | { |
274 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) { | |
275 | while (!go[MASTER]) | |
4f07118f | 276 | rmb(); |
1da177e4 | 277 | go[MASTER] = 0; |
4f07118f | 278 | wmb(); |
1da177e4 | 279 | go[SLAVE] = tick_ops->get_tick(); |
293666b7 | 280 | membar_safe("#StoreLoad"); |
1da177e4 LT |
281 | } |
282 | } | |
49b6c01f | 283 | raw_spin_unlock_irqrestore(&itc_sync_lock, flags); |
1da177e4 LT |
284 | } |
285 | ||
b14f5c10 | 286 | #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU) |
2066aadd PG |
287 | static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg, |
288 | void **descrp) | |
b14f5c10 DM |
289 | { |
290 | extern unsigned long sparc64_ttable_tl0; | |
291 | extern unsigned long kern_locked_tte_data; | |
b14f5c10 DM |
292 | struct hvtramp_descr *hdesc; |
293 | unsigned long trampoline_ra; | |
294 | struct trap_per_cpu *tb; | |
295 | u64 tte_vaddr, tte_data; | |
296 | unsigned long hv_err; | |
64658743 | 297 | int i; |
b14f5c10 | 298 | |
64658743 DM |
299 | hdesc = kzalloc(sizeof(*hdesc) + |
300 | (sizeof(struct hvtramp_mapping) * | |
301 | num_kernel_image_mappings - 1), | |
302 | GFP_KERNEL); | |
b14f5c10 | 303 | if (!hdesc) { |
27a2ef38 | 304 | printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate " |
b14f5c10 DM |
305 | "hvtramp_descr.\n"); |
306 | return; | |
307 | } | |
557fe0e8 | 308 | *descrp = hdesc; |
b14f5c10 DM |
309 | |
310 | hdesc->cpu = cpu; | |
64658743 | 311 | hdesc->num_mappings = num_kernel_image_mappings; |
b14f5c10 DM |
312 | |
313 | tb = &trap_block[cpu]; | |
b14f5c10 DM |
314 | |
315 | hdesc->fault_info_va = (unsigned long) &tb->fault_info; | |
316 | hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info); | |
317 | ||
318 | hdesc->thread_reg = thread_reg; | |
319 | ||
320 | tte_vaddr = (unsigned long) KERNBASE; | |
321 | tte_data = kern_locked_tte_data; | |
322 | ||
64658743 DM |
323 | for (i = 0; i < hdesc->num_mappings; i++) { |
324 | hdesc->maps[i].vaddr = tte_vaddr; | |
325 | hdesc->maps[i].tte = tte_data; | |
b14f5c10 DM |
326 | tte_vaddr += 0x400000; |
327 | tte_data += 0x400000; | |
b14f5c10 DM |
328 | } |
329 | ||
330 | trampoline_ra = kimage_addr_to_ra(hv_cpu_startup); | |
331 | ||
332 | hv_err = sun4v_cpu_start(cpu, trampoline_ra, | |
333 | kimage_addr_to_ra(&sparc64_ttable_tl0), | |
334 | __pa(hdesc)); | |
e0204409 DM |
335 | if (hv_err) |
336 | printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() " | |
337 | "gives error %lu\n", hv_err); | |
b14f5c10 DM |
338 | } |
339 | #endif | |
340 | ||
1da177e4 LT |
341 | extern unsigned long sparc64_cpu_startup; |
342 | ||
343 | /* The OBP cpu startup callback truncates the 3rd arg cookie to | |
344 | * 32-bits (I think) so to be safe we have it read the pointer | |
345 | * contained here so we work on >4GB machines. -DaveM | |
346 | */ | |
347 | static struct thread_info *cpu_new_thread = NULL; | |
348 | ||
2066aadd | 349 | static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle) |
1da177e4 LT |
350 | { |
351 | unsigned long entry = | |
352 | (unsigned long)(&sparc64_cpu_startup); | |
353 | unsigned long cookie = | |
354 | (unsigned long)(&cpu_new_thread); | |
557fe0e8 | 355 | void *descr = NULL; |
7890f794 | 356 | int timeout, ret; |
1da177e4 | 357 | |
1da177e4 | 358 | callin_flag = 0; |
f0a2bc7e | 359 | cpu_new_thread = task_thread_info(idle); |
1da177e4 | 360 | |
7890f794 | 361 | if (tlb_type == hypervisor) { |
b14f5c10 | 362 | #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU) |
4f0234f4 DM |
363 | if (ldom_domaining_enabled) |
364 | ldom_startcpu_cpuid(cpu, | |
557fe0e8 DM |
365 | (unsigned long) cpu_new_thread, |
366 | &descr); | |
4f0234f4 DM |
367 | else |
368 | #endif | |
369 | prom_startcpu_cpuid(cpu, entry, cookie); | |
7890f794 | 370 | } else { |
5cbc3073 | 371 | struct device_node *dp = of_find_node_by_cpuid(cpu); |
7890f794 | 372 | |
6016a363 | 373 | prom_startcpu(dp->phandle, entry, cookie); |
7890f794 | 374 | } |
1da177e4 | 375 | |
4f0234f4 | 376 | for (timeout = 0; timeout < 50000; timeout++) { |
1da177e4 LT |
377 | if (callin_flag) |
378 | break; | |
379 | udelay(100); | |
380 | } | |
72aff53f | 381 | |
1da177e4 LT |
382 | if (callin_flag) { |
383 | ret = 0; | |
384 | } else { | |
385 | printk("Processor %d is stuck.\n", cpu); | |
1da177e4 LT |
386 | ret = -ENODEV; |
387 | } | |
388 | cpu_new_thread = NULL; | |
389 | ||
557fe0e8 | 390 | kfree(descr); |
b37d40d1 | 391 | |
1da177e4 LT |
392 | return ret; |
393 | } | |
394 | ||
395 | static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) | |
396 | { | |
397 | u64 result, target; | |
398 | int stuck, tmp; | |
399 | ||
400 | if (this_is_starfire) { | |
401 | /* map to real upaid */ | |
402 | cpu = (((cpu & 0x3c) << 1) | | |
403 | ((cpu & 0x40) >> 4) | | |
404 | (cpu & 0x3)); | |
405 | } | |
406 | ||
407 | target = (cpu << 14) | 0x70; | |
408 | again: | |
409 | /* Ok, this is the real Spitfire Errata #54. | |
410 | * One must read back from a UDB internal register | |
411 | * after writes to the UDB interrupt dispatch, but | |
412 | * before the membar Sync for that write. | |
413 | * So we use the high UDB control register (ASI 0x7f, | |
414 | * ADDR 0x20) for the dummy read. -DaveM | |
415 | */ | |
416 | tmp = 0x40; | |
417 | __asm__ __volatile__( | |
418 | "wrpr %1, %2, %%pstate\n\t" | |
419 | "stxa %4, [%0] %3\n\t" | |
420 | "stxa %5, [%0+%8] %3\n\t" | |
421 | "add %0, %8, %0\n\t" | |
422 | "stxa %6, [%0+%8] %3\n\t" | |
423 | "membar #Sync\n\t" | |
424 | "stxa %%g0, [%7] %3\n\t" | |
425 | "membar #Sync\n\t" | |
426 | "mov 0x20, %%g1\n\t" | |
427 | "ldxa [%%g1] 0x7f, %%g0\n\t" | |
428 | "membar #Sync" | |
429 | : "=r" (tmp) | |
430 | : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), | |
431 | "r" (data0), "r" (data1), "r" (data2), "r" (target), | |
432 | "r" (0x10), "0" (tmp) | |
433 | : "g1"); | |
434 | ||
435 | /* NOTE: PSTATE_IE is still clear. */ | |
436 | stuck = 100000; | |
437 | do { | |
438 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
439 | : "=r" (result) | |
440 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
441 | if (result == 0) { | |
442 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
443 | : : "r" (pstate)); | |
444 | return; | |
445 | } | |
446 | stuck -= 1; | |
447 | if (stuck == 0) | |
448 | break; | |
449 | } while (result & 0x1); | |
450 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
451 | : : "r" (pstate)); | |
452 | if (stuck == 0) { | |
90181136 | 453 | printk("CPU[%d]: mondo stuckage result[%016llx]\n", |
1da177e4 LT |
454 | smp_processor_id(), result); |
455 | } else { | |
456 | udelay(2); | |
457 | goto again; | |
458 | } | |
459 | } | |
460 | ||
90f7ae8a | 461 | static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
1da177e4 | 462 | { |
90f7ae8a DM |
463 | u64 *mondo, data0, data1, data2; |
464 | u16 *cpu_list; | |
1da177e4 LT |
465 | u64 pstate; |
466 | int i; | |
467 | ||
468 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
90f7ae8a DM |
469 | cpu_list = __va(tb->cpu_list_pa); |
470 | mondo = __va(tb->cpu_mondo_block_pa); | |
471 | data0 = mondo[0]; | |
472 | data1 = mondo[1]; | |
473 | data2 = mondo[2]; | |
474 | for (i = 0; i < cnt; i++) | |
475 | spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]); | |
1da177e4 LT |
476 | } |
477 | ||
478 | /* Cheetah now allows to send the whole 64-bytes of data in the interrupt | |
479 | * packet, but we have no use for that. However we do take advantage of | |
480 | * the new pipelining feature (ie. dispatch to multiple cpus simultaneously). | |
481 | */ | |
90f7ae8a | 482 | static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
1da177e4 | 483 | { |
22adb358 | 484 | int nack_busy_id, is_jbus, need_more; |
90f7ae8a DM |
485 | u64 *mondo, pstate, ver, busy_mask; |
486 | u16 *cpu_list; | |
1da177e4 | 487 | |
90f7ae8a DM |
488 | cpu_list = __va(tb->cpu_list_pa); |
489 | mondo = __va(tb->cpu_mondo_block_pa); | |
cd5bc89d | 490 | |
1da177e4 LT |
491 | /* Unfortunately, someone at Sun had the brilliant idea to make the |
492 | * busy/nack fields hard-coded by ITID number for this Ultra-III | |
493 | * derivative processor. | |
494 | */ | |
495 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
92704a1c DM |
496 | is_jbus = ((ver >> 32) == __JALAPENO_ID || |
497 | (ver >> 32) == __SERRANO_ID); | |
1da177e4 LT |
498 | |
499 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
500 | ||
501 | retry: | |
22adb358 | 502 | need_more = 0; |
1da177e4 LT |
503 | __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t" |
504 | : : "r" (pstate), "i" (PSTATE_IE)); | |
505 | ||
506 | /* Setup the dispatch data registers. */ | |
507 | __asm__ __volatile__("stxa %0, [%3] %6\n\t" | |
508 | "stxa %1, [%4] %6\n\t" | |
509 | "stxa %2, [%5] %6\n\t" | |
510 | "membar #Sync\n\t" | |
511 | : /* no outputs */ | |
90f7ae8a | 512 | : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]), |
1da177e4 LT |
513 | "r" (0x40), "r" (0x50), "r" (0x60), |
514 | "i" (ASI_INTR_W)); | |
515 | ||
516 | nack_busy_id = 0; | |
0de56d1a | 517 | busy_mask = 0; |
1da177e4 LT |
518 | { |
519 | int i; | |
520 | ||
90f7ae8a DM |
521 | for (i = 0; i < cnt; i++) { |
522 | u64 target, nr; | |
523 | ||
524 | nr = cpu_list[i]; | |
525 | if (nr == 0xffff) | |
526 | continue; | |
1da177e4 | 527 | |
90f7ae8a | 528 | target = (nr << 14) | 0x70; |
0de56d1a | 529 | if (is_jbus) { |
90f7ae8a | 530 | busy_mask |= (0x1UL << (nr * 2)); |
0de56d1a | 531 | } else { |
1da177e4 | 532 | target |= (nack_busy_id << 24); |
0de56d1a DM |
533 | busy_mask |= (0x1UL << |
534 | (nack_busy_id * 2)); | |
535 | } | |
1da177e4 LT |
536 | __asm__ __volatile__( |
537 | "stxa %%g0, [%0] %1\n\t" | |
538 | "membar #Sync\n\t" | |
539 | : /* no outputs */ | |
540 | : "r" (target), "i" (ASI_INTR_W)); | |
541 | nack_busy_id++; | |
22adb358 DM |
542 | if (nack_busy_id == 32) { |
543 | need_more = 1; | |
544 | break; | |
545 | } | |
1da177e4 LT |
546 | } |
547 | } | |
548 | ||
549 | /* Now, poll for completion. */ | |
550 | { | |
0de56d1a | 551 | u64 dispatch_stat, nack_mask; |
1da177e4 LT |
552 | long stuck; |
553 | ||
554 | stuck = 100000 * nack_busy_id; | |
0de56d1a | 555 | nack_mask = busy_mask << 1; |
1da177e4 LT |
556 | do { |
557 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
558 | : "=r" (dispatch_stat) | |
559 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
0de56d1a | 560 | if (!(dispatch_stat & (busy_mask | nack_mask))) { |
1da177e4 LT |
561 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" |
562 | : : "r" (pstate)); | |
22adb358 | 563 | if (unlikely(need_more)) { |
90f7ae8a DM |
564 | int i, this_cnt = 0; |
565 | for (i = 0; i < cnt; i++) { | |
566 | if (cpu_list[i] == 0xffff) | |
567 | continue; | |
568 | cpu_list[i] = 0xffff; | |
569 | this_cnt++; | |
570 | if (this_cnt == 32) | |
22adb358 DM |
571 | break; |
572 | } | |
573 | goto retry; | |
574 | } | |
1da177e4 LT |
575 | return; |
576 | } | |
577 | if (!--stuck) | |
578 | break; | |
0de56d1a | 579 | } while (dispatch_stat & busy_mask); |
1da177e4 LT |
580 | |
581 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
582 | : : "r" (pstate)); | |
583 | ||
0de56d1a | 584 | if (dispatch_stat & busy_mask) { |
1da177e4 LT |
585 | /* Busy bits will not clear, continue instead |
586 | * of freezing up on this cpu. | |
587 | */ | |
90181136 | 588 | printk("CPU[%d]: mondo stuckage result[%016llx]\n", |
1da177e4 LT |
589 | smp_processor_id(), dispatch_stat); |
590 | } else { | |
591 | int i, this_busy_nack = 0; | |
592 | ||
593 | /* Delay some random time with interrupts enabled | |
594 | * to prevent deadlock. | |
595 | */ | |
596 | udelay(2 * nack_busy_id); | |
597 | ||
598 | /* Clear out the mask bits for cpus which did not | |
599 | * NACK us. | |
600 | */ | |
90f7ae8a DM |
601 | for (i = 0; i < cnt; i++) { |
602 | u64 check_mask, nr; | |
603 | ||
604 | nr = cpu_list[i]; | |
605 | if (nr == 0xffff) | |
606 | continue; | |
1da177e4 | 607 | |
92704a1c | 608 | if (is_jbus) |
90f7ae8a | 609 | check_mask = (0x2UL << (2*nr)); |
1da177e4 LT |
610 | else |
611 | check_mask = (0x2UL << | |
612 | this_busy_nack); | |
613 | if ((dispatch_stat & check_mask) == 0) | |
90f7ae8a | 614 | cpu_list[i] = 0xffff; |
1da177e4 | 615 | this_busy_nack += 2; |
22adb358 DM |
616 | if (this_busy_nack == 64) |
617 | break; | |
1da177e4 LT |
618 | } |
619 | ||
620 | goto retry; | |
621 | } | |
622 | } | |
623 | } | |
624 | ||
1d2f1f90 | 625 | /* Multi-cpu list version. */ |
90f7ae8a | 626 | static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt) |
a43fe0e7 | 627 | { |
ed4d9c66 | 628 | int retries, this_cpu, prev_sent, i, saw_cpu_error; |
c02a5119 | 629 | unsigned long status; |
b830ab66 | 630 | u16 *cpu_list; |
17f34f0e | 631 | |
b830ab66 | 632 | this_cpu = smp_processor_id(); |
1d2f1f90 | 633 | |
b830ab66 DM |
634 | cpu_list = __va(tb->cpu_list_pa); |
635 | ||
ed4d9c66 | 636 | saw_cpu_error = 0; |
1d2f1f90 | 637 | retries = 0; |
3cab0c3e | 638 | prev_sent = 0; |
1d2f1f90 | 639 | do { |
3cab0c3e | 640 | int forward_progress, n_sent; |
1d2f1f90 | 641 | |
b830ab66 DM |
642 | status = sun4v_cpu_mondo_send(cnt, |
643 | tb->cpu_list_pa, | |
644 | tb->cpu_mondo_block_pa); | |
645 | ||
646 | /* HV_EOK means all cpus received the xcall, we're done. */ | |
647 | if (likely(status == HV_EOK)) | |
1d2f1f90 | 648 | break; |
b830ab66 | 649 | |
3cab0c3e DM |
650 | /* First, see if we made any forward progress. |
651 | * | |
652 | * The hypervisor indicates successful sends by setting | |
653 | * cpu list entries to the value 0xffff. | |
b830ab66 | 654 | */ |
3cab0c3e | 655 | n_sent = 0; |
b830ab66 | 656 | for (i = 0; i < cnt; i++) { |
3cab0c3e DM |
657 | if (likely(cpu_list[i] == 0xffff)) |
658 | n_sent++; | |
1d2f1f90 DM |
659 | } |
660 | ||
3cab0c3e DM |
661 | forward_progress = 0; |
662 | if (n_sent > prev_sent) | |
663 | forward_progress = 1; | |
664 | ||
665 | prev_sent = n_sent; | |
666 | ||
b830ab66 DM |
667 | /* If we get a HV_ECPUERROR, then one or more of the cpus |
668 | * in the list are in error state. Use the cpu_state() | |
669 | * hypervisor call to find out which cpus are in error state. | |
670 | */ | |
671 | if (unlikely(status == HV_ECPUERROR)) { | |
672 | for (i = 0; i < cnt; i++) { | |
673 | long err; | |
674 | u16 cpu; | |
675 | ||
676 | cpu = cpu_list[i]; | |
677 | if (cpu == 0xffff) | |
678 | continue; | |
679 | ||
680 | err = sun4v_cpu_state(cpu); | |
ed4d9c66 DM |
681 | if (err == HV_CPU_STATE_ERROR) { |
682 | saw_cpu_error = (cpu + 1); | |
3cab0c3e | 683 | cpu_list[i] = 0xffff; |
b830ab66 DM |
684 | } |
685 | } | |
686 | } else if (unlikely(status != HV_EWOULDBLOCK)) | |
687 | goto fatal_mondo_error; | |
688 | ||
3cab0c3e DM |
689 | /* Don't bother rewriting the CPU list, just leave the |
690 | * 0xffff and non-0xffff entries in there and the | |
691 | * hypervisor will do the right thing. | |
692 | * | |
693 | * Only advance timeout state if we didn't make any | |
694 | * forward progress. | |
695 | */ | |
b830ab66 DM |
696 | if (unlikely(!forward_progress)) { |
697 | if (unlikely(++retries > 10000)) | |
698 | goto fatal_mondo_timeout; | |
699 | ||
700 | /* Delay a little bit to let other cpus catch up | |
701 | * on their cpu mondo queue work. | |
702 | */ | |
703 | udelay(2 * cnt); | |
704 | } | |
1d2f1f90 DM |
705 | } while (1); |
706 | ||
ed4d9c66 | 707 | if (unlikely(saw_cpu_error)) |
b830ab66 DM |
708 | goto fatal_mondo_cpu_error; |
709 | ||
710 | return; | |
711 | ||
712 | fatal_mondo_cpu_error: | |
713 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus " | |
ed4d9c66 DM |
714 | "(including %d) were in error state\n", |
715 | this_cpu, saw_cpu_error - 1); | |
b830ab66 DM |
716 | return; |
717 | ||
718 | fatal_mondo_timeout: | |
b830ab66 DM |
719 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward " |
720 | " progress after %d retries.\n", | |
721 | this_cpu, retries); | |
722 | goto dump_cpu_list_and_out; | |
723 | ||
724 | fatal_mondo_error: | |
b830ab66 DM |
725 | printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n", |
726 | this_cpu, status); | |
727 | printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) " | |
728 | "mondo_block_pa(%lx)\n", | |
729 | this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa); | |
730 | ||
731 | dump_cpu_list_and_out: | |
732 | printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu); | |
733 | for (i = 0; i < cnt; i++) | |
734 | printk("%u ", cpu_list[i]); | |
735 | printk("]\n"); | |
1d2f1f90 | 736 | } |
a43fe0e7 | 737 | |
90f7ae8a | 738 | static void (*xcall_deliver_impl)(struct trap_per_cpu *, int); |
deb16999 DM |
739 | |
740 | static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask) | |
741 | { | |
90f7ae8a DM |
742 | struct trap_per_cpu *tb; |
743 | int this_cpu, i, cnt; | |
c02a5119 | 744 | unsigned long flags; |
90f7ae8a DM |
745 | u16 *cpu_list; |
746 | u64 *mondo; | |
c02a5119 DM |
747 | |
748 | /* We have to do this whole thing with interrupts fully disabled. | |
749 | * Otherwise if we send an xcall from interrupt context it will | |
750 | * corrupt both our mondo block and cpu list state. | |
751 | * | |
752 | * One consequence of this is that we cannot use timeout mechanisms | |
753 | * that depend upon interrupts being delivered locally. So, for | |
754 | * example, we cannot sample jiffies and expect it to advance. | |
755 | * | |
756 | * Fortunately, udelay() uses %stick/%tick so we can use that. | |
757 | */ | |
758 | local_irq_save(flags); | |
90f7ae8a DM |
759 | |
760 | this_cpu = smp_processor_id(); | |
761 | tb = &trap_block[this_cpu]; | |
762 | ||
763 | mondo = __va(tb->cpu_mondo_block_pa); | |
764 | mondo[0] = data0; | |
765 | mondo[1] = data1; | |
766 | mondo[2] = data2; | |
767 | wmb(); | |
768 | ||
769 | cpu_list = __va(tb->cpu_list_pa); | |
770 | ||
771 | /* Setup the initial cpu list. */ | |
772 | cnt = 0; | |
8e757281 | 773 | for_each_cpu(i, mask) { |
90f7ae8a DM |
774 | if (i == this_cpu || !cpu_online(i)) |
775 | continue; | |
776 | cpu_list[cnt++] = i; | |
777 | } | |
778 | ||
779 | if (cnt) | |
780 | xcall_deliver_impl(tb, cnt); | |
781 | ||
c02a5119 | 782 | local_irq_restore(flags); |
deb16999 | 783 | } |
5e0797e5 | 784 | |
91a4231c DM |
785 | /* Send cross call to all processors mentioned in MASK_P |
786 | * except self. Really, there are only two cases currently, | |
fb1fece5 | 787 | * "cpu_online_mask" and "mm_cpumask(mm)". |
1da177e4 | 788 | */ |
ae583885 | 789 | static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask) |
1da177e4 LT |
790 | { |
791 | u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff)); | |
1da177e4 | 792 | |
ae583885 DM |
793 | xcall_deliver(data0, data1, data2, mask); |
794 | } | |
1da177e4 | 795 | |
ae583885 DM |
796 | /* Send cross call to all processors except self. */ |
797 | static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2) | |
798 | { | |
fb1fece5 | 799 | smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask); |
1da177e4 LT |
800 | } |
801 | ||
802 | extern unsigned long xcall_sync_tick; | |
803 | ||
804 | static void smp_start_sync_tick_client(int cpu) | |
805 | { | |
24445a4a | 806 | xcall_deliver((u64) &xcall_sync_tick, 0, 0, |
fb1fece5 | 807 | cpumask_of(cpu)); |
1da177e4 LT |
808 | } |
809 | ||
1da177e4 LT |
810 | extern unsigned long xcall_call_function; |
811 | ||
f46df02a | 812 | void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
1da177e4 | 813 | { |
f46df02a | 814 | xcall_deliver((u64) &xcall_call_function, 0, 0, mask); |
d172ad18 | 815 | } |
1da177e4 | 816 | |
d172ad18 | 817 | extern unsigned long xcall_call_function_single; |
1da177e4 | 818 | |
d172ad18 DM |
819 | void arch_send_call_function_single_ipi(int cpu) |
820 | { | |
19926630 | 821 | xcall_deliver((u64) &xcall_call_function_single, 0, 0, |
fb1fece5 | 822 | cpumask_of(cpu)); |
1da177e4 LT |
823 | } |
824 | ||
9960e9e8 | 825 | void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs) |
1da177e4 | 826 | { |
d172ad18 | 827 | clear_softint(1 << irq); |
ab5c7809 | 828 | irq_enter(); |
d172ad18 | 829 | generic_smp_call_function_interrupt(); |
ab5c7809 | 830 | irq_exit(); |
d172ad18 | 831 | } |
1da177e4 | 832 | |
9960e9e8 | 833 | void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs) |
d172ad18 | 834 | { |
1da177e4 | 835 | clear_softint(1 << irq); |
ab5c7809 | 836 | irq_enter(); |
d172ad18 | 837 | generic_smp_call_function_single_interrupt(); |
ab5c7809 | 838 | irq_exit(); |
1da177e4 LT |
839 | } |
840 | ||
bd40791e DM |
841 | static void tsb_sync(void *info) |
842 | { | |
6f25f398 | 843 | struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()]; |
bd40791e DM |
844 | struct mm_struct *mm = info; |
845 | ||
42b2aa86 | 846 | /* It is not valid to test "current->active_mm == mm" here. |
6f25f398 DM |
847 | * |
848 | * The value of "current" is not changed atomically with | |
849 | * switch_mm(). But that's OK, we just need to check the | |
850 | * current cpu's trap block PGD physical address. | |
851 | */ | |
852 | if (tp->pgd_paddr == __pa(mm->pgd)) | |
bd40791e DM |
853 | tsb_context_switch(mm); |
854 | } | |
855 | ||
856 | void smp_tsb_sync(struct mm_struct *mm) | |
857 | { | |
81f1adf0 | 858 | smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1); |
bd40791e DM |
859 | } |
860 | ||
1da177e4 | 861 | extern unsigned long xcall_flush_tlb_mm; |
f36391d2 | 862 | extern unsigned long xcall_flush_tlb_page; |
1da177e4 | 863 | extern unsigned long xcall_flush_tlb_kernel_range; |
93dae5b7 | 864 | extern unsigned long xcall_fetch_glob_regs; |
916ca14a DM |
865 | extern unsigned long xcall_fetch_glob_pmu; |
866 | extern unsigned long xcall_fetch_glob_pmu_n4; | |
1da177e4 | 867 | extern unsigned long xcall_receive_signal; |
ee29074d | 868 | extern unsigned long xcall_new_mmu_context_version; |
e2fdd7fd DM |
869 | #ifdef CONFIG_KGDB |
870 | extern unsigned long xcall_kgdb_capture; | |
871 | #endif | |
1da177e4 LT |
872 | |
873 | #ifdef DCACHE_ALIASING_POSSIBLE | |
874 | extern unsigned long xcall_flush_dcache_page_cheetah; | |
875 | #endif | |
876 | extern unsigned long xcall_flush_dcache_page_spitfire; | |
877 | ||
d979f179 | 878 | static inline void __local_flush_dcache_page(struct page *page) |
1da177e4 LT |
879 | { |
880 | #ifdef DCACHE_ALIASING_POSSIBLE | |
881 | __flush_dcache_page(page_address(page), | |
882 | ((tlb_type == spitfire) && | |
883 | page_mapping(page) != NULL)); | |
884 | #else | |
885 | if (page_mapping(page) != NULL && | |
886 | tlb_type == spitfire) | |
887 | __flush_icache_page(__pa(page_address(page))); | |
888 | #endif | |
889 | } | |
890 | ||
891 | void smp_flush_dcache_page_impl(struct page *page, int cpu) | |
892 | { | |
a43fe0e7 DM |
893 | int this_cpu; |
894 | ||
895 | if (tlb_type == hypervisor) | |
896 | return; | |
1da177e4 LT |
897 | |
898 | #ifdef CONFIG_DEBUG_DCFLUSH | |
899 | atomic_inc(&dcpage_flushes); | |
900 | #endif | |
a43fe0e7 DM |
901 | |
902 | this_cpu = get_cpu(); | |
903 | ||
1da177e4 LT |
904 | if (cpu == this_cpu) { |
905 | __local_flush_dcache_page(page); | |
906 | } else if (cpu_online(cpu)) { | |
907 | void *pg_addr = page_address(page); | |
622824db | 908 | u64 data0 = 0; |
1da177e4 LT |
909 | |
910 | if (tlb_type == spitfire) { | |
622824db | 911 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); |
1da177e4 LT |
912 | if (page_mapping(page) != NULL) |
913 | data0 |= ((u64)1 << 32); | |
a43fe0e7 | 914 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 | 915 | #ifdef DCACHE_ALIASING_POSSIBLE |
622824db | 916 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); |
1da177e4 LT |
917 | #endif |
918 | } | |
622824db DM |
919 | if (data0) { |
920 | xcall_deliver(data0, __pa(pg_addr), | |
fb1fece5 | 921 | (u64) pg_addr, cpumask_of(cpu)); |
1da177e4 | 922 | #ifdef CONFIG_DEBUG_DCFLUSH |
622824db | 923 | atomic_inc(&dcpage_flushes_xcall); |
1da177e4 | 924 | #endif |
622824db | 925 | } |
1da177e4 LT |
926 | } |
927 | ||
928 | put_cpu(); | |
929 | } | |
930 | ||
931 | void flush_dcache_page_all(struct mm_struct *mm, struct page *page) | |
932 | { | |
622824db | 933 | void *pg_addr; |
622824db | 934 | u64 data0; |
a43fe0e7 DM |
935 | |
936 | if (tlb_type == hypervisor) | |
937 | return; | |
938 | ||
c6fee081 | 939 | preempt_disable(); |
1da177e4 | 940 | |
1da177e4 LT |
941 | #ifdef CONFIG_DEBUG_DCFLUSH |
942 | atomic_inc(&dcpage_flushes); | |
943 | #endif | |
622824db DM |
944 | data0 = 0; |
945 | pg_addr = page_address(page); | |
1da177e4 LT |
946 | if (tlb_type == spitfire) { |
947 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); | |
948 | if (page_mapping(page) != NULL) | |
949 | data0 |= ((u64)1 << 32); | |
a43fe0e7 | 950 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
951 | #ifdef DCACHE_ALIASING_POSSIBLE |
952 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); | |
1da177e4 LT |
953 | #endif |
954 | } | |
622824db DM |
955 | if (data0) { |
956 | xcall_deliver(data0, __pa(pg_addr), | |
fb1fece5 | 957 | (u64) pg_addr, cpu_online_mask); |
1da177e4 | 958 | #ifdef CONFIG_DEBUG_DCFLUSH |
622824db | 959 | atomic_inc(&dcpage_flushes_xcall); |
1da177e4 | 960 | #endif |
622824db | 961 | } |
1da177e4 LT |
962 | __local_flush_dcache_page(page); |
963 | ||
c6fee081 | 964 | preempt_enable(); |
1da177e4 LT |
965 | } |
966 | ||
e2fdd7fd DM |
967 | #ifdef CONFIG_KGDB |
968 | void kgdb_roundup_cpus(unsigned long flags) | |
969 | { | |
970 | smp_cross_call(&xcall_kgdb_capture, 0, 0, 0); | |
971 | } | |
972 | #endif | |
973 | ||
93dae5b7 DM |
974 | void smp_fetch_global_regs(void) |
975 | { | |
976 | smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0); | |
977 | } | |
93dae5b7 | 978 | |
916ca14a DM |
979 | void smp_fetch_global_pmu(void) |
980 | { | |
981 | if (tlb_type == hypervisor && | |
982 | sun4v_chip_type >= SUN4V_CHIP_NIAGARA4) | |
983 | smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0); | |
984 | else | |
985 | smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0); | |
986 | } | |
987 | ||
1da177e4 LT |
988 | /* We know that the window frames of the user have been flushed |
989 | * to the stack before we get here because all callers of us | |
990 | * are flush_tlb_*() routines, and these run after flush_cache_*() | |
991 | * which performs the flushw. | |
992 | * | |
993 | * The SMP TLB coherency scheme we use works as follows: | |
994 | * | |
995 | * 1) mm->cpu_vm_mask is a bit mask of which cpus an address | |
996 | * space has (potentially) executed on, this is the heuristic | |
997 | * we use to avoid doing cross calls. | |
998 | * | |
999 | * Also, for flushing from kswapd and also for clones, we | |
1000 | * use cpu_vm_mask as the list of cpus to make run the TLB. | |
1001 | * | |
1002 | * 2) TLB context numbers are shared globally across all processors | |
1003 | * in the system, this allows us to play several games to avoid | |
1004 | * cross calls. | |
1005 | * | |
1006 | * One invariant is that when a cpu switches to a process, and | |
1007 | * that processes tsk->active_mm->cpu_vm_mask does not have the | |
1008 | * current cpu's bit set, that tlb context is flushed locally. | |
1009 | * | |
1010 | * If the address space is non-shared (ie. mm->count == 1) we avoid | |
1011 | * cross calls when we want to flush the currently running process's | |
1012 | * tlb state. This is done by clearing all cpu bits except the current | |
f9384d41 | 1013 | * processor's in current->mm->cpu_vm_mask and performing the |
1da177e4 LT |
1014 | * flush locally only. This will force any subsequent cpus which run |
1015 | * this task to flush the context from the local tlb if the process | |
1016 | * migrates to another cpu (again). | |
1017 | * | |
1018 | * 3) For shared address spaces (threads) and swapping we bite the | |
1019 | * bullet for most cases and perform the cross call (but only to | |
1020 | * the cpus listed in cpu_vm_mask). | |
1021 | * | |
1022 | * The performance gain from "optimizing" away the cross call for threads is | |
1023 | * questionable (in theory the big win for threads is the massive sharing of | |
1024 | * address space state across processors). | |
1025 | */ | |
62dbec78 DM |
1026 | |
1027 | /* This currently is only used by the hugetlb arch pre-fault | |
1028 | * hook on UltraSPARC-III+ and later when changing the pagesize | |
1029 | * bits of the context register for an address space. | |
1030 | */ | |
1da177e4 LT |
1031 | void smp_flush_tlb_mm(struct mm_struct *mm) |
1032 | { | |
62dbec78 DM |
1033 | u32 ctx = CTX_HWBITS(mm->context); |
1034 | int cpu = get_cpu(); | |
1da177e4 | 1035 | |
62dbec78 | 1036 | if (atomic_read(&mm->mm_users) == 1) { |
81f1adf0 | 1037 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); |
62dbec78 DM |
1038 | goto local_flush_and_out; |
1039 | } | |
1da177e4 | 1040 | |
62dbec78 DM |
1041 | smp_cross_call_masked(&xcall_flush_tlb_mm, |
1042 | ctx, 0, 0, | |
81f1adf0 | 1043 | mm_cpumask(mm)); |
1da177e4 | 1044 | |
62dbec78 DM |
1045 | local_flush_and_out: |
1046 | __flush_tlb_mm(ctx, SECONDARY_CONTEXT); | |
1da177e4 | 1047 | |
62dbec78 | 1048 | put_cpu(); |
1da177e4 LT |
1049 | } |
1050 | ||
f36391d2 DM |
1051 | struct tlb_pending_info { |
1052 | unsigned long ctx; | |
1053 | unsigned long nr; | |
1054 | unsigned long *vaddrs; | |
1055 | }; | |
1056 | ||
1057 | static void tlb_pending_func(void *info) | |
1058 | { | |
1059 | struct tlb_pending_info *t = info; | |
1060 | ||
1061 | __flush_tlb_pending(t->ctx, t->nr, t->vaddrs); | |
1062 | } | |
1063 | ||
1da177e4 LT |
1064 | void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs) |
1065 | { | |
1066 | u32 ctx = CTX_HWBITS(mm->context); | |
f36391d2 | 1067 | struct tlb_pending_info info; |
1da177e4 LT |
1068 | int cpu = get_cpu(); |
1069 | ||
f36391d2 DM |
1070 | info.ctx = ctx; |
1071 | info.nr = nr; | |
1072 | info.vaddrs = vaddrs; | |
1073 | ||
f9384d41 | 1074 | if (mm == current->mm && atomic_read(&mm->mm_users) == 1) |
81f1adf0 | 1075 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); |
dedeb002 | 1076 | else |
f36391d2 DM |
1077 | smp_call_function_many(mm_cpumask(mm), tlb_pending_func, |
1078 | &info, 1); | |
1da177e4 | 1079 | |
1da177e4 LT |
1080 | __flush_tlb_pending(ctx, nr, vaddrs); |
1081 | ||
1082 | put_cpu(); | |
1083 | } | |
1084 | ||
f36391d2 DM |
1085 | void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr) |
1086 | { | |
1087 | unsigned long context = CTX_HWBITS(mm->context); | |
1088 | int cpu = get_cpu(); | |
1089 | ||
1090 | if (mm == current->mm && atomic_read(&mm->mm_users) == 1) | |
1091 | cpumask_copy(mm_cpumask(mm), cpumask_of(cpu)); | |
1092 | else | |
1093 | smp_cross_call_masked(&xcall_flush_tlb_page, | |
1094 | context, vaddr, 0, | |
1095 | mm_cpumask(mm)); | |
1096 | __flush_tlb_page(context, vaddr); | |
1097 | ||
1098 | put_cpu(); | |
1099 | } | |
1100 | ||
1da177e4 LT |
1101 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end) |
1102 | { | |
1103 | start &= PAGE_MASK; | |
1104 | end = PAGE_ALIGN(end); | |
1105 | if (start != end) { | |
1106 | smp_cross_call(&xcall_flush_tlb_kernel_range, | |
1107 | 0, start, end); | |
1108 | ||
1109 | __flush_tlb_kernel_range(start, end); | |
1110 | } | |
1111 | } | |
1112 | ||
1113 | /* CPU capture. */ | |
1114 | /* #define CAPTURE_DEBUG */ | |
1115 | extern unsigned long xcall_capture; | |
1116 | ||
1117 | static atomic_t smp_capture_depth = ATOMIC_INIT(0); | |
1118 | static atomic_t smp_capture_registry = ATOMIC_INIT(0); | |
1119 | static unsigned long penguins_are_doing_time; | |
1120 | ||
1121 | void smp_capture(void) | |
1122 | { | |
4f3316c2 | 1123 | int result = atomic_add_return(1, &smp_capture_depth); |
1da177e4 LT |
1124 | |
1125 | if (result == 1) { | |
1126 | int ncpus = num_online_cpus(); | |
1127 | ||
1128 | #ifdef CAPTURE_DEBUG | |
1129 | printk("CPU[%d]: Sending penguins to jail...", | |
1130 | smp_processor_id()); | |
1131 | #endif | |
1132 | penguins_are_doing_time = 1; | |
1da177e4 LT |
1133 | atomic_inc(&smp_capture_registry); |
1134 | smp_cross_call(&xcall_capture, 0, 0, 0); | |
1135 | while (atomic_read(&smp_capture_registry) != ncpus) | |
4f07118f | 1136 | rmb(); |
1da177e4 LT |
1137 | #ifdef CAPTURE_DEBUG |
1138 | printk("done\n"); | |
1139 | #endif | |
1140 | } | |
1141 | } | |
1142 | ||
1143 | void smp_release(void) | |
1144 | { | |
1145 | if (atomic_dec_and_test(&smp_capture_depth)) { | |
1146 | #ifdef CAPTURE_DEBUG | |
1147 | printk("CPU[%d]: Giving pardon to " | |
1148 | "imprisoned penguins\n", | |
1149 | smp_processor_id()); | |
1150 | #endif | |
1151 | penguins_are_doing_time = 0; | |
293666b7 | 1152 | membar_safe("#StoreLoad"); |
1da177e4 LT |
1153 | atomic_dec(&smp_capture_registry); |
1154 | } | |
1155 | } | |
1156 | ||
b4f4372f DM |
1157 | /* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE |
1158 | * set, so they can service tlb flush xcalls... | |
1da177e4 LT |
1159 | */ |
1160 | extern void prom_world(int); | |
96c6e0d8 | 1161 | |
9960e9e8 | 1162 | void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs) |
1da177e4 | 1163 | { |
1da177e4 LT |
1164 | clear_softint(1 << irq); |
1165 | ||
1166 | preempt_disable(); | |
1167 | ||
1168 | __asm__ __volatile__("flushw"); | |
1da177e4 LT |
1169 | prom_world(1); |
1170 | atomic_inc(&smp_capture_registry); | |
293666b7 | 1171 | membar_safe("#StoreLoad"); |
1da177e4 | 1172 | while (penguins_are_doing_time) |
4f07118f | 1173 | rmb(); |
1da177e4 LT |
1174 | atomic_dec(&smp_capture_registry); |
1175 | prom_world(0); | |
1176 | ||
1177 | preempt_enable(); | |
1178 | } | |
1179 | ||
1da177e4 | 1180 | /* /proc/profile writes can call this, don't __init it please. */ |
1da177e4 LT |
1181 | int setup_profiling_timer(unsigned int multiplier) |
1182 | { | |
777a4475 | 1183 | return -EINVAL; |
1da177e4 LT |
1184 | } |
1185 | ||
1186 | void __init smp_prepare_cpus(unsigned int max_cpus) | |
1187 | { | |
1da177e4 LT |
1188 | } |
1189 | ||
7c9503b8 | 1190 | void smp_prepare_boot_cpu(void) |
7abea921 | 1191 | { |
7abea921 DM |
1192 | } |
1193 | ||
5e0797e5 DM |
1194 | void __init smp_setup_processor_id(void) |
1195 | { | |
1196 | if (tlb_type == spitfire) | |
deb16999 | 1197 | xcall_deliver_impl = spitfire_xcall_deliver; |
5e0797e5 | 1198 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
deb16999 | 1199 | xcall_deliver_impl = cheetah_xcall_deliver; |
5e0797e5 | 1200 | else |
deb16999 | 1201 | xcall_deliver_impl = hypervisor_xcall_deliver; |
5e0797e5 DM |
1202 | } |
1203 | ||
9b2f753e AP |
1204 | void __init smp_fill_in_cpu_possible_map(void) |
1205 | { | |
1206 | int possible_cpus = num_possible_cpus(); | |
1207 | int i; | |
1208 | ||
1209 | if (possible_cpus > nr_cpu_ids) | |
1210 | possible_cpus = nr_cpu_ids; | |
1211 | ||
1212 | for (i = 0; i < possible_cpus; i++) | |
1213 | set_cpu_possible(i, true); | |
1214 | for (; i < NR_CPUS; i++) | |
1215 | set_cpu_possible(i, false); | |
1216 | } | |
1217 | ||
7c9503b8 | 1218 | void smp_fill_in_sib_core_maps(void) |
1da177e4 | 1219 | { |
5cbc3073 DM |
1220 | unsigned int i; |
1221 | ||
e0204409 | 1222 | for_each_present_cpu(i) { |
5cbc3073 DM |
1223 | unsigned int j; |
1224 | ||
fb1fece5 | 1225 | cpumask_clear(&cpu_core_map[i]); |
5cbc3073 | 1226 | if (cpu_data(i).core_id == 0) { |
fb1fece5 | 1227 | cpumask_set_cpu(i, &cpu_core_map[i]); |
5cbc3073 DM |
1228 | continue; |
1229 | } | |
1230 | ||
e0204409 | 1231 | for_each_present_cpu(j) { |
5cbc3073 DM |
1232 | if (cpu_data(i).core_id == |
1233 | cpu_data(j).core_id) | |
fb1fece5 | 1234 | cpumask_set_cpu(j, &cpu_core_map[i]); |
f78eae2e DM |
1235 | } |
1236 | } | |
1237 | ||
acc455cf | 1238 | for_each_present_cpu(i) { |
1239 | unsigned int j; | |
1240 | ||
1241 | for_each_present_cpu(j) { | |
d624716b AP |
1242 | if (cpu_data(i).max_cache_id == |
1243 | cpu_data(j).max_cache_id) | |
1244 | cpumask_set_cpu(j, &cpu_core_sib_cache_map[i]); | |
1245 | ||
acc455cf | 1246 | if (cpu_data(i).sock_id == cpu_data(j).sock_id) |
1247 | cpumask_set_cpu(j, &cpu_core_sib_map[i]); | |
1248 | } | |
1249 | } | |
1250 | ||
e0204409 | 1251 | for_each_present_cpu(i) { |
f78eae2e DM |
1252 | unsigned int j; |
1253 | ||
fb1fece5 | 1254 | cpumask_clear(&per_cpu(cpu_sibling_map, i)); |
f78eae2e | 1255 | if (cpu_data(i).proc_id == -1) { |
fb1fece5 | 1256 | cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i)); |
f78eae2e DM |
1257 | continue; |
1258 | } | |
1259 | ||
e0204409 | 1260 | for_each_present_cpu(j) { |
f78eae2e DM |
1261 | if (cpu_data(i).proc_id == |
1262 | cpu_data(j).proc_id) | |
fb1fece5 | 1263 | cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i)); |
5cbc3073 DM |
1264 | } |
1265 | } | |
1da177e4 LT |
1266 | } |
1267 | ||
2066aadd | 1268 | int __cpu_up(unsigned int cpu, struct task_struct *tidle) |
1da177e4 | 1269 | { |
f0a2bc7e | 1270 | int ret = smp_boot_one_cpu(cpu, tidle); |
1da177e4 LT |
1271 | |
1272 | if (!ret) { | |
fb1fece5 KM |
1273 | cpumask_set_cpu(cpu, &smp_commenced_mask); |
1274 | while (!cpu_online(cpu)) | |
1da177e4 | 1275 | mb(); |
fb1fece5 | 1276 | if (!cpu_online(cpu)) { |
1da177e4 LT |
1277 | ret = -ENODEV; |
1278 | } else { | |
02fead75 DM |
1279 | /* On SUN4V, writes to %tick and %stick are |
1280 | * not allowed. | |
1281 | */ | |
1282 | if (tlb_type != hypervisor) | |
1283 | smp_synchronize_one_tick(cpu); | |
1da177e4 LT |
1284 | } |
1285 | } | |
1286 | return ret; | |
1287 | } | |
1288 | ||
4f0234f4 | 1289 | #ifdef CONFIG_HOTPLUG_CPU |
e0204409 DM |
1290 | void cpu_play_dead(void) |
1291 | { | |
1292 | int cpu = smp_processor_id(); | |
1293 | unsigned long pstate; | |
1294 | ||
1295 | idle_task_exit(); | |
1296 | ||
1297 | if (tlb_type == hypervisor) { | |
1298 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1299 | ||
1300 | sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO, | |
1301 | tb->cpu_mondo_pa, 0); | |
1302 | sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO, | |
1303 | tb->dev_mondo_pa, 0); | |
1304 | sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR, | |
1305 | tb->resum_mondo_pa, 0); | |
1306 | sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR, | |
1307 | tb->nonresum_mondo_pa, 0); | |
1308 | } | |
1309 | ||
fb1fece5 | 1310 | cpumask_clear_cpu(cpu, &smp_commenced_mask); |
e0204409 DM |
1311 | membar_safe("#Sync"); |
1312 | ||
1313 | local_irq_disable(); | |
1314 | ||
1315 | __asm__ __volatile__( | |
1316 | "rdpr %%pstate, %0\n\t" | |
1317 | "wrpr %0, %1, %%pstate" | |
1318 | : "=r" (pstate) | |
1319 | : "i" (PSTATE_IE)); | |
1320 | ||
1321 | while (1) | |
1322 | barrier(); | |
1323 | } | |
1324 | ||
4f0234f4 DM |
1325 | int __cpu_disable(void) |
1326 | { | |
e0204409 DM |
1327 | int cpu = smp_processor_id(); |
1328 | cpuinfo_sparc *c; | |
1329 | int i; | |
1330 | ||
fb1fece5 KM |
1331 | for_each_cpu(i, &cpu_core_map[cpu]) |
1332 | cpumask_clear_cpu(cpu, &cpu_core_map[i]); | |
1333 | cpumask_clear(&cpu_core_map[cpu]); | |
e0204409 | 1334 | |
fb1fece5 KM |
1335 | for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu)) |
1336 | cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i)); | |
1337 | cpumask_clear(&per_cpu(cpu_sibling_map, cpu)); | |
e0204409 DM |
1338 | |
1339 | c = &cpu_data(cpu); | |
1340 | ||
1341 | c->core_id = 0; | |
1342 | c->proc_id = -1; | |
1343 | ||
e0204409 DM |
1344 | smp_wmb(); |
1345 | ||
1346 | /* Make sure no interrupts point to this cpu. */ | |
1347 | fixup_irqs(); | |
1348 | ||
1349 | local_irq_enable(); | |
1350 | mdelay(1); | |
1351 | local_irq_disable(); | |
1352 | ||
fb1fece5 | 1353 | set_cpu_online(cpu, false); |
4d084617 | 1354 | |
280ff974 HP |
1355 | cpu_map_rebuild(); |
1356 | ||
e0204409 | 1357 | return 0; |
4f0234f4 DM |
1358 | } |
1359 | ||
1360 | void __cpu_die(unsigned int cpu) | |
1361 | { | |
e0204409 DM |
1362 | int i; |
1363 | ||
1364 | for (i = 0; i < 100; i++) { | |
1365 | smp_rmb(); | |
fb1fece5 | 1366 | if (!cpumask_test_cpu(cpu, &smp_commenced_mask)) |
e0204409 DM |
1367 | break; |
1368 | msleep(100); | |
1369 | } | |
fb1fece5 | 1370 | if (cpumask_test_cpu(cpu, &smp_commenced_mask)) { |
e0204409 DM |
1371 | printk(KERN_ERR "CPU %u didn't die...\n", cpu); |
1372 | } else { | |
1373 | #if defined(CONFIG_SUN_LDOMS) | |
1374 | unsigned long hv_err; | |
1375 | int limit = 100; | |
1376 | ||
1377 | do { | |
1378 | hv_err = sun4v_cpu_stop(cpu); | |
1379 | if (hv_err == HV_EOK) { | |
fb1fece5 | 1380 | set_cpu_present(cpu, false); |
e0204409 DM |
1381 | break; |
1382 | } | |
1383 | } while (--limit > 0); | |
1384 | if (limit <= 0) { | |
1385 | printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n", | |
1386 | hv_err); | |
1387 | } | |
1388 | #endif | |
1389 | } | |
4f0234f4 DM |
1390 | } |
1391 | #endif | |
1392 | ||
1da177e4 LT |
1393 | void __init smp_cpus_done(unsigned int max_cpus) |
1394 | { | |
1da177e4 LT |
1395 | } |
1396 | ||
1da177e4 LT |
1397 | void smp_send_reschedule(int cpu) |
1398 | { | |
1a36265b KT |
1399 | if (cpu == smp_processor_id()) { |
1400 | WARN_ON_ONCE(preemptible()); | |
1401 | set_softint(1 << PIL_SMP_RECEIVE_SIGNAL); | |
1402 | } else { | |
1403 | xcall_deliver((u64) &xcall_receive_signal, | |
1404 | 0, 0, cpumask_of(cpu)); | |
1405 | } | |
19926630 DM |
1406 | } |
1407 | ||
9960e9e8 | 1408 | void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs) |
19926630 DM |
1409 | { |
1410 | clear_softint(1 << irq); | |
184748cc | 1411 | scheduler_ipi(); |
1da177e4 LT |
1412 | } |
1413 | ||
94ab5990 DK |
1414 | static void stop_this_cpu(void *dummy) |
1415 | { | |
cffb3e76 | 1416 | set_cpu_online(smp_processor_id(), false); |
94ab5990 DK |
1417 | prom_stopself(); |
1418 | } | |
1419 | ||
1da177e4 LT |
1420 | void smp_send_stop(void) |
1421 | { | |
94ab5990 DK |
1422 | int cpu; |
1423 | ||
1424 | if (tlb_type == hypervisor) { | |
7dd4fcf5 VK |
1425 | int this_cpu = smp_processor_id(); |
1426 | #ifdef CONFIG_SERIAL_SUNHV | |
1427 | sunhv_migrate_hvcons_irq(this_cpu); | |
1428 | #endif | |
94ab5990 | 1429 | for_each_online_cpu(cpu) { |
7dd4fcf5 | 1430 | if (cpu == this_cpu) |
94ab5990 | 1431 | continue; |
cffb3e76 VK |
1432 | |
1433 | set_cpu_online(cpu, false); | |
94ab5990 DK |
1434 | #ifdef CONFIG_SUN_LDOMS |
1435 | if (ldom_domaining_enabled) { | |
1436 | unsigned long hv_err; | |
1437 | hv_err = sun4v_cpu_stop(cpu); | |
1438 | if (hv_err) | |
1439 | printk(KERN_ERR "sun4v_cpu_stop() " | |
1440 | "failed err=%lu\n", hv_err); | |
1441 | } else | |
1442 | #endif | |
1443 | prom_stopcpu_cpuid(cpu); | |
1444 | } | |
1445 | } else | |
1446 | smp_call_function(stop_this_cpu, NULL, 0); | |
1da177e4 LT |
1447 | } |
1448 | ||
4fd78a5f DM |
1449 | /** |
1450 | * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu | |
1451 | * @cpu: cpu to allocate for | |
1452 | * @size: size allocation in bytes | |
1453 | * @align: alignment | |
1454 | * | |
1455 | * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper | |
1456 | * does the right thing for NUMA regardless of the current | |
1457 | * configuration. | |
1458 | * | |
1459 | * RETURNS: | |
1460 | * Pointer to the allocated area on success, NULL on failure. | |
1461 | */ | |
bcb2107f TH |
1462 | static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size, |
1463 | size_t align) | |
4fd78a5f DM |
1464 | { |
1465 | const unsigned long goal = __pa(MAX_DMA_ADDRESS); | |
1466 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
1467 | int node = cpu_to_node(cpu); | |
1468 | void *ptr; | |
1469 | ||
1470 | if (!node_online(node) || !NODE_DATA(node)) { | |
1471 | ptr = __alloc_bootmem(size, align, goal); | |
1472 | pr_info("cpu %d has no node %d or node-local memory\n", | |
1473 | cpu, node); | |
1474 | pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n", | |
1475 | cpu, size, __pa(ptr)); | |
1476 | } else { | |
1477 | ptr = __alloc_bootmem_node(NODE_DATA(node), | |
1478 | size, align, goal); | |
1479 | pr_debug("per cpu data for cpu%d %lu bytes on node%d at " | |
1480 | "%016lx\n", cpu, size, node, __pa(ptr)); | |
1481 | } | |
1482 | return ptr; | |
1483 | #else | |
1484 | return __alloc_bootmem(size, align, goal); | |
1485 | #endif | |
1486 | } | |
1487 | ||
bcb2107f | 1488 | static void __init pcpu_free_bootmem(void *ptr, size_t size) |
4fd78a5f | 1489 | { |
bcb2107f TH |
1490 | free_bootmem(__pa(ptr), size); |
1491 | } | |
4fd78a5f | 1492 | |
a70c6913 | 1493 | static int __init pcpu_cpu_distance(unsigned int from, unsigned int to) |
bcb2107f TH |
1494 | { |
1495 | if (cpu_to_node(from) == cpu_to_node(to)) | |
1496 | return LOCAL_DISTANCE; | |
1497 | else | |
1498 | return REMOTE_DISTANCE; | |
4fd78a5f DM |
1499 | } |
1500 | ||
a70c6913 TH |
1501 | static void __init pcpu_populate_pte(unsigned long addr) |
1502 | { | |
1503 | pgd_t *pgd = pgd_offset_k(addr); | |
1504 | pud_t *pud; | |
1505 | pmd_t *pmd; | |
1506 | ||
ac55c768 DM |
1507 | if (pgd_none(*pgd)) { |
1508 | pud_t *new; | |
1509 | ||
1510 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1511 | pgd_populate(&init_mm, pgd, new); | |
1512 | } | |
1513 | ||
a70c6913 TH |
1514 | pud = pud_offset(pgd, addr); |
1515 | if (pud_none(*pud)) { | |
1516 | pmd_t *new; | |
1517 | ||
1518 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1519 | pud_populate(&init_mm, pud, new); | |
1520 | } | |
1521 | ||
1522 | pmd = pmd_offset(pud, addr); | |
1523 | if (!pmd_present(*pmd)) { | |
1524 | pte_t *new; | |
1525 | ||
1526 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1527 | pmd_populate_kernel(&init_mm, pmd, new); | |
1528 | } | |
1529 | } | |
1530 | ||
73fffc03 | 1531 | void __init setup_per_cpu_areas(void) |
1da177e4 | 1532 | { |
bcb2107f TH |
1533 | unsigned long delta; |
1534 | unsigned int cpu; | |
a70c6913 TH |
1535 | int rc = -EINVAL; |
1536 | ||
1537 | if (pcpu_chosen_fc != PCPU_FC_PAGE) { | |
1538 | rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE, | |
1539 | PERCPU_DYNAMIC_RESERVE, 4 << 20, | |
1540 | pcpu_cpu_distance, | |
1541 | pcpu_alloc_bootmem, | |
1542 | pcpu_free_bootmem); | |
1543 | if (rc) | |
1544 | pr_warning("PERCPU: %s allocator failed (%d), " | |
1545 | "falling back to page size\n", | |
1546 | pcpu_fc_names[pcpu_chosen_fc], rc); | |
1547 | } | |
1548 | if (rc < 0) | |
1549 | rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE, | |
1550 | pcpu_alloc_bootmem, | |
1551 | pcpu_free_bootmem, | |
1552 | pcpu_populate_pte); | |
1553 | if (rc < 0) | |
1554 | panic("cannot initialize percpu area (err=%d)", rc); | |
5a089006 | 1555 | |
4fd78a5f | 1556 | delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start; |
fb435d52 TH |
1557 | for_each_possible_cpu(cpu) |
1558 | __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu]; | |
951bc82c DM |
1559 | |
1560 | /* Setup %g5 for the boot cpu. */ | |
1561 | __local_per_cpu_offset = __per_cpu_offset(smp_processor_id()); | |
b696fdc2 DM |
1562 | |
1563 | of_fill_in_cpu_data(); | |
1564 | if (tlb_type == hypervisor) | |
6ac5c610 | 1565 | mdesc_fill_in_cpu_data(cpu_all_mask); |
1da177e4 | 1566 | } |