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1da177e4 LT |
1 | /* sun4d_smp.c: Sparc SS1000/SC2000 SMP support. |
2 | * | |
3 | * Copyright (C) 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
4 | * | |
5 | * Based on sun4m's smp.c, which is: | |
6 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
7 | */ | |
8 | ||
9 | #include <asm/head.h> | |
10 | ||
11 | #include <linux/kernel.h> | |
12 | #include <linux/sched.h> | |
13 | #include <linux/threads.h> | |
14 | #include <linux/smp.h> | |
15 | #include <linux/smp_lock.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/kernel_stat.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/mm.h> | |
21 | #include <linux/swap.h> | |
22 | #include <linux/profile.h> | |
23 | ||
24 | #include <asm/ptrace.h> | |
25 | #include <asm/atomic.h> | |
0d84438d | 26 | #include <asm/irq_regs.h> |
1da177e4 LT |
27 | |
28 | #include <asm/delay.h> | |
29 | #include <asm/irq.h> | |
30 | #include <asm/page.h> | |
31 | #include <asm/pgalloc.h> | |
32 | #include <asm/pgtable.h> | |
33 | #include <asm/oplib.h> | |
34 | #include <asm/sbus.h> | |
35 | #include <asm/sbi.h> | |
36 | #include <asm/tlbflush.h> | |
37 | #include <asm/cacheflush.h> | |
38 | #include <asm/cpudata.h> | |
39 | ||
40 | #define IRQ_CROSS_CALL 15 | |
41 | ||
42 | extern ctxd_t *srmmu_ctx_table_phys; | |
43 | ||
44 | extern void calibrate_delay(void); | |
45 | ||
5fec811e | 46 | static volatile int smp_processors_ready = 0; |
1da177e4 LT |
47 | static int smp_highest_cpu; |
48 | extern volatile unsigned long cpu_callin_map[NR_CPUS]; | |
a54123e2 | 49 | extern cpuinfo_sparc cpu_data[NR_CPUS]; |
1da177e4 | 50 | extern unsigned char boot_cpu_id; |
1da177e4 | 51 | extern volatile int smp_process_available; |
a54123e2 BB |
52 | |
53 | extern cpumask_t smp_commenced_mask; | |
54 | ||
1da177e4 LT |
55 | extern int __smp4d_processor_id(void); |
56 | ||
57 | /* #define SMP_DEBUG */ | |
58 | ||
59 | #ifdef SMP_DEBUG | |
60 | #define SMP_PRINTK(x) printk x | |
61 | #else | |
62 | #define SMP_PRINTK(x) | |
63 | #endif | |
64 | ||
65 | static inline unsigned long swap(volatile unsigned long *ptr, unsigned long val) | |
66 | { | |
67 | __asm__ __volatile__("swap [%1], %0\n\t" : | |
68 | "=&r" (val), "=&r" (ptr) : | |
69 | "0" (val), "1" (ptr)); | |
70 | return val; | |
71 | } | |
72 | ||
73 | static void smp_setup_percpu_timer(void); | |
74 | extern void cpu_probe(void); | |
75 | extern void sun4d_distribute_irqs(void); | |
76 | ||
77 | void __init smp4d_callin(void) | |
78 | { | |
79 | int cpuid = hard_smp4d_processor_id(); | |
80 | extern spinlock_t sun4d_imsk_lock; | |
81 | unsigned long flags; | |
82 | ||
83 | /* Show we are alive */ | |
84 | cpu_leds[cpuid] = 0x6; | |
85 | show_leds(cpuid); | |
86 | ||
87 | /* Enable level15 interrupt, disable level14 interrupt for now */ | |
88 | cc_set_imsk((cc_get_imsk() & ~0x8000) | 0x4000); | |
89 | ||
90 | local_flush_cache_all(); | |
91 | local_flush_tlb_all(); | |
92 | ||
93 | /* | |
94 | * Unblock the master CPU _only_ when the scheduler state | |
95 | * of all secondary CPUs will be up-to-date, so after | |
96 | * the SMP initialization the master will be just allowed | |
97 | * to call the scheduler code. | |
98 | */ | |
99 | /* Get our local ticker going. */ | |
100 | smp_setup_percpu_timer(); | |
101 | ||
102 | calibrate_delay(); | |
103 | smp_store_cpu_info(cpuid); | |
104 | local_flush_cache_all(); | |
105 | local_flush_tlb_all(); | |
106 | ||
107 | /* Allow master to continue. */ | |
108 | swap((unsigned long *)&cpu_callin_map[cpuid], 1); | |
109 | local_flush_cache_all(); | |
110 | local_flush_tlb_all(); | |
111 | ||
112 | cpu_probe(); | |
113 | ||
114 | while((unsigned long)current_set[cpuid] < PAGE_OFFSET) | |
115 | barrier(); | |
116 | ||
117 | while(current_set[cpuid]->cpu != cpuid) | |
118 | barrier(); | |
119 | ||
120 | /* Fix idle thread fields. */ | |
121 | __asm__ __volatile__("ld [%0], %%g6\n\t" | |
122 | : : "r" (¤t_set[cpuid]) | |
123 | : "memory" /* paranoid */); | |
124 | ||
125 | cpu_leds[cpuid] = 0x9; | |
126 | show_leds(cpuid); | |
127 | ||
128 | /* Attach to the address space of init_task. */ | |
129 | atomic_inc(&init_mm.mm_count); | |
130 | current->active_mm = &init_mm; | |
131 | ||
132 | local_flush_cache_all(); | |
133 | local_flush_tlb_all(); | |
134 | ||
135 | local_irq_enable(); /* We don't allow PIL 14 yet */ | |
136 | ||
a54123e2 | 137 | while (!cpu_isset(cpuid, smp_commenced_mask)) |
1da177e4 LT |
138 | barrier(); |
139 | ||
140 | spin_lock_irqsave(&sun4d_imsk_lock, flags); | |
141 | cc_set_imsk(cc_get_imsk() & ~0x4000); /* Allow PIL 14 as well */ | |
142 | spin_unlock_irqrestore(&sun4d_imsk_lock, flags); | |
8b3c848c RB |
143 | cpu_set(cpuid, cpu_online_map); |
144 | ||
1da177e4 LT |
145 | } |
146 | ||
147 | extern void init_IRQ(void); | |
148 | extern void cpu_panic(void); | |
149 | ||
150 | /* | |
151 | * Cycle through the processors asking the PROM to start each one. | |
152 | */ | |
153 | ||
154 | extern struct linux_prom_registers smp_penguin_ctable; | |
155 | extern unsigned long trapbase_cpu1[]; | |
156 | extern unsigned long trapbase_cpu2[]; | |
157 | extern unsigned long trapbase_cpu3[]; | |
158 | ||
159 | void __init smp4d_boot_cpus(void) | |
160 | { | |
1da177e4 LT |
161 | if (boot_cpu_id) |
162 | current_set[0] = NULL; | |
1da177e4 LT |
163 | smp_setup_percpu_timer(); |
164 | local_flush_cache_all(); | |
8b3c848c RB |
165 | } |
166 | ||
167 | int smp4d_boot_one_cpu(int i) | |
168 | { | |
1da177e4 LT |
169 | extern unsigned long sun4d_cpu_startup; |
170 | unsigned long *entry = &sun4d_cpu_startup; | |
171 | struct task_struct *p; | |
172 | int timeout; | |
8b3c848c | 173 | int cpu_node; |
1da177e4 | 174 | |
8b3c848c | 175 | cpu_find_by_instance(i, &cpu_node,NULL); |
1da177e4 LT |
176 | /* Cook up an idler for this guy. */ |
177 | p = fork_idle(i); | |
d562ef6a | 178 | current_set[i] = task_thread_info(p); |
1da177e4 LT |
179 | |
180 | /* | |
181 | * Initialize the contexts table | |
182 | * Since the call to prom_startcpu() trashes the structure, | |
183 | * we need to re-initialize it for each cpu | |
184 | */ | |
185 | smp_penguin_ctable.which_io = 0; | |
186 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; | |
187 | smp_penguin_ctable.reg_size = 0; | |
188 | ||
189 | /* whirrr, whirrr, whirrrrrrrrr... */ | |
8b3c848c | 190 | SMP_PRINTK(("Starting CPU %d at %p \n", i, entry)); |
1da177e4 | 191 | local_flush_cache_all(); |
8b3c848c | 192 | prom_startcpu(cpu_node, |
1da177e4 LT |
193 | &smp_penguin_ctable, 0, (char *)entry); |
194 | ||
195 | SMP_PRINTK(("prom_startcpu returned :)\n")); | |
196 | ||
197 | /* wheee... it's going... */ | |
198 | for(timeout = 0; timeout < 10000; timeout++) { | |
199 | if(cpu_callin_map[i]) | |
200 | break; | |
201 | udelay(200); | |
202 | } | |
203 | ||
8b3c848c RB |
204 | if (!(cpu_callin_map[i])) { |
205 | printk("Processor %d is stuck.\n", i); | |
206 | return -ENODEV; | |
207 | ||
1da177e4 LT |
208 | } |
209 | local_flush_cache_all(); | |
8b3c848c RB |
210 | return 0; |
211 | } | |
212 | ||
213 | void __init smp4d_smp_done(void) | |
214 | { | |
215 | int i, first; | |
216 | int *prev; | |
217 | ||
218 | /* setup cpu list for irq rotation */ | |
219 | first = 0; | |
220 | prev = &first; | |
221 | for (i = 0; i < NR_CPUS; i++) | |
222 | if (cpu_online(i)) { | |
223 | *prev = i; | |
224 | prev = &cpu_data(i).next; | |
1da177e4 | 225 | } |
8b3c848c RB |
226 | *prev = first; |
227 | local_flush_cache_all(); | |
1da177e4 LT |
228 | |
229 | /* Free unneeded trap tables */ | |
230 | ClearPageReserved(virt_to_page(trapbase_cpu1)); | |
7835e98b | 231 | init_page_count(virt_to_page(trapbase_cpu1)); |
1da177e4 LT |
232 | free_page((unsigned long)trapbase_cpu1); |
233 | totalram_pages++; | |
234 | num_physpages++; | |
235 | ||
236 | ClearPageReserved(virt_to_page(trapbase_cpu2)); | |
7835e98b | 237 | init_page_count(virt_to_page(trapbase_cpu2)); |
1da177e4 LT |
238 | free_page((unsigned long)trapbase_cpu2); |
239 | totalram_pages++; | |
240 | num_physpages++; | |
241 | ||
242 | ClearPageReserved(virt_to_page(trapbase_cpu3)); | |
7835e98b | 243 | init_page_count(virt_to_page(trapbase_cpu3)); |
1da177e4 LT |
244 | free_page((unsigned long)trapbase_cpu3); |
245 | totalram_pages++; | |
246 | num_physpages++; | |
247 | ||
248 | /* Ok, they are spinning and ready to go. */ | |
249 | smp_processors_ready = 1; | |
250 | sun4d_distribute_irqs(); | |
251 | } | |
252 | ||
253 | static struct smp_funcall { | |
254 | smpfunc_t func; | |
255 | unsigned long arg1; | |
256 | unsigned long arg2; | |
257 | unsigned long arg3; | |
258 | unsigned long arg4; | |
259 | unsigned long arg5; | |
260 | unsigned char processors_in[NR_CPUS]; /* Set when ipi entered. */ | |
261 | unsigned char processors_out[NR_CPUS]; /* Set when ipi exited. */ | |
262 | } ccall_info __attribute__((aligned(8))); | |
263 | ||
264 | static DEFINE_SPINLOCK(cross_call_lock); | |
265 | ||
266 | /* Cross calls must be serialized, at least currently. */ | |
267 | void smp4d_cross_call(smpfunc_t func, unsigned long arg1, unsigned long arg2, | |
268 | unsigned long arg3, unsigned long arg4, unsigned long arg5) | |
269 | { | |
270 | if(smp_processors_ready) { | |
271 | register int high = smp_highest_cpu; | |
272 | unsigned long flags; | |
273 | ||
274 | spin_lock_irqsave(&cross_call_lock, flags); | |
275 | ||
276 | { | |
277 | /* If you make changes here, make sure gcc generates proper code... */ | |
278 | register smpfunc_t f asm("i0") = func; | |
279 | register unsigned long a1 asm("i1") = arg1; | |
280 | register unsigned long a2 asm("i2") = arg2; | |
281 | register unsigned long a3 asm("i3") = arg3; | |
282 | register unsigned long a4 asm("i4") = arg4; | |
283 | register unsigned long a5 asm("i5") = arg5; | |
284 | ||
285 | __asm__ __volatile__( | |
286 | "std %0, [%6]\n\t" | |
287 | "std %2, [%6 + 8]\n\t" | |
288 | "std %4, [%6 + 16]\n\t" : : | |
289 | "r"(f), "r"(a1), "r"(a2), "r"(a3), "r"(a4), "r"(a5), | |
290 | "r" (&ccall_info.func)); | |
291 | } | |
292 | ||
293 | /* Init receive/complete mapping, plus fire the IPI's off. */ | |
294 | { | |
295 | cpumask_t mask; | |
296 | register int i; | |
297 | ||
298 | mask = cpumask_of_cpu(hard_smp4d_processor_id()); | |
8b3c848c | 299 | cpus_andnot(mask, cpu_online_map, mask); |
1da177e4 LT |
300 | for(i = 0; i <= high; i++) { |
301 | if (cpu_isset(i, mask)) { | |
302 | ccall_info.processors_in[i] = 0; | |
303 | ccall_info.processors_out[i] = 0; | |
304 | sun4d_send_ipi(i, IRQ_CROSS_CALL); | |
305 | } | |
306 | } | |
307 | } | |
308 | ||
309 | { | |
310 | register int i; | |
311 | ||
312 | i = 0; | |
313 | do { | |
314 | while(!ccall_info.processors_in[i]) | |
315 | barrier(); | |
316 | } while(++i <= high); | |
317 | ||
318 | i = 0; | |
319 | do { | |
320 | while(!ccall_info.processors_out[i]) | |
321 | barrier(); | |
322 | } while(++i <= high); | |
323 | } | |
324 | ||
325 | spin_unlock_irqrestore(&cross_call_lock, flags); | |
326 | } | |
327 | } | |
328 | ||
329 | /* Running cross calls. */ | |
330 | void smp4d_cross_call_irq(void) | |
331 | { | |
332 | int i = hard_smp4d_processor_id(); | |
333 | ||
334 | ccall_info.processors_in[i] = 1; | |
335 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, | |
336 | ccall_info.arg4, ccall_info.arg5); | |
337 | ccall_info.processors_out[i] = 1; | |
338 | } | |
339 | ||
340 | static int smp4d_stop_cpu_sender; | |
341 | ||
342 | static void smp4d_stop_cpu(void) | |
343 | { | |
344 | int me = hard_smp4d_processor_id(); | |
345 | ||
346 | if (me != smp4d_stop_cpu_sender) | |
347 | while(1) barrier(); | |
348 | } | |
349 | ||
350 | /* Cross calls, in order to work efficiently and atomically do all | |
351 | * the message passing work themselves, only stopcpu and reschedule | |
352 | * messages come through here. | |
353 | */ | |
354 | void smp4d_message_pass(int target, int msg, unsigned long data, int wait) | |
355 | { | |
356 | int me = hard_smp4d_processor_id(); | |
357 | ||
358 | SMP_PRINTK(("smp4d_message_pass %d %d %08lx %d\n", target, msg, data, wait)); | |
359 | if (msg == MSG_STOP_CPU && target == MSG_ALL_BUT_SELF) { | |
360 | unsigned long flags; | |
361 | static DEFINE_SPINLOCK(stop_cpu_lock); | |
362 | spin_lock_irqsave(&stop_cpu_lock, flags); | |
363 | smp4d_stop_cpu_sender = me; | |
364 | smp4d_cross_call((smpfunc_t)smp4d_stop_cpu, 0, 0, 0, 0, 0); | |
365 | spin_unlock_irqrestore(&stop_cpu_lock, flags); | |
366 | } | |
367 | printk("Yeeee, trying to send SMP msg(%d) to %d on cpu %d\n", msg, target, me); | |
368 | panic("Bogon SMP message pass."); | |
369 | } | |
370 | ||
371 | void smp4d_percpu_timer_interrupt(struct pt_regs *regs) | |
372 | { | |
0d84438d | 373 | struct pt_regs *old_regs; |
1da177e4 LT |
374 | int cpu = hard_smp4d_processor_id(); |
375 | static int cpu_tick[NR_CPUS]; | |
376 | static char led_mask[] = { 0xe, 0xd, 0xb, 0x7, 0xb, 0xd }; | |
377 | ||
0d84438d | 378 | old_regs = set_irq_regs(regs); |
1da177e4 LT |
379 | bw_get_prof_limit(cpu); |
380 | bw_clear_intr_mask(0, 1); /* INTR_TABLE[0] & 1 is Profile IRQ */ | |
381 | ||
382 | cpu_tick[cpu]++; | |
383 | if (!(cpu_tick[cpu] & 15)) { | |
384 | if (cpu_tick[cpu] == 0x60) | |
385 | cpu_tick[cpu] = 0; | |
386 | cpu_leds[cpu] = led_mask[cpu_tick[cpu] >> 4]; | |
387 | show_leds(cpu); | |
388 | } | |
389 | ||
0d84438d | 390 | profile_tick(CPU_PROFILING); |
1da177e4 LT |
391 | |
392 | if(!--prof_counter(cpu)) { | |
393 | int user = user_mode(regs); | |
394 | ||
395 | irq_enter(); | |
396 | update_process_times(user); | |
397 | irq_exit(); | |
398 | ||
399 | prof_counter(cpu) = prof_multiplier(cpu); | |
400 | } | |
0d84438d | 401 | set_irq_regs(old_regs); |
1da177e4 LT |
402 | } |
403 | ||
404 | extern unsigned int lvl14_resolution; | |
405 | ||
406 | static void __init smp_setup_percpu_timer(void) | |
407 | { | |
408 | int cpu = hard_smp4d_processor_id(); | |
409 | ||
410 | prof_counter(cpu) = prof_multiplier(cpu) = 1; | |
411 | load_profile_irq(cpu, lvl14_resolution); | |
412 | } | |
413 | ||
414 | void __init smp4d_blackbox_id(unsigned *addr) | |
415 | { | |
416 | int rd = *addr & 0x3e000000; | |
417 | ||
418 | addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ | |
419 | addr[1] = 0x01000000; /* nop */ | |
420 | addr[2] = 0x01000000; /* nop */ | |
421 | } | |
422 | ||
423 | void __init smp4d_blackbox_current(unsigned *addr) | |
424 | { | |
425 | int rd = *addr & 0x3e000000; | |
426 | ||
427 | addr[0] = 0xc0800800 | rd; /* lda [%g0] ASI_M_VIKING_TMP1, reg */ | |
428 | addr[2] = 0x81282002 | rd | (rd >> 11); /* sll reg, 2, reg */ | |
429 | addr[4] = 0x01000000; /* nop */ | |
430 | } | |
431 | ||
432 | void __init sun4d_init_smp(void) | |
433 | { | |
434 | int i; | |
435 | extern unsigned int t_nmi[], linux_trap_ipi15_sun4d[], linux_trap_ipi15_sun4m[]; | |
436 | ||
437 | /* Patch ipi15 trap table */ | |
438 | t_nmi[1] = t_nmi[1] + (linux_trap_ipi15_sun4d - linux_trap_ipi15_sun4m); | |
439 | ||
440 | /* And set btfixup... */ | |
441 | BTFIXUPSET_BLACKBOX(hard_smp_processor_id, smp4d_blackbox_id); | |
442 | BTFIXUPSET_BLACKBOX(load_current, smp4d_blackbox_current); | |
443 | BTFIXUPSET_CALL(smp_cross_call, smp4d_cross_call, BTFIXUPCALL_NORM); | |
444 | BTFIXUPSET_CALL(smp_message_pass, smp4d_message_pass, BTFIXUPCALL_NORM); | |
445 | BTFIXUPSET_CALL(__hard_smp_processor_id, __smp4d_processor_id, BTFIXUPCALL_NORM); | |
446 | ||
447 | for (i = 0; i < NR_CPUS; i++) { | |
448 | ccall_info.processors_in[i] = 1; | |
449 | ccall_info.processors_out[i] = 1; | |
450 | } | |
451 | } |