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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
aba20a82 SR |
2 | /* |
3 | * sun4m SMP support. | |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu) | |
6 | */ | |
7 | ||
62f08283 | 8 | #include <linux/clockchips.h> |
1da177e4 | 9 | #include <linux/interrupt.h> |
1da177e4 | 10 | #include <linux/profile.h> |
6c81c32f | 11 | #include <linux/delay.h> |
68e21be2 | 12 | #include <linux/sched/mm.h> |
4245e59d | 13 | #include <linux/cpu.h> |
6c81c32f | 14 | |
1da177e4 | 15 | #include <asm/cacheflush.h> |
bde4d8b2 | 16 | #include <asm/switch_to.h> |
1da177e4 | 17 | #include <asm/tlbflush.h> |
62f08283 | 18 | #include <asm/timer.h> |
5d83d666 | 19 | #include <asm/oplib.h> |
1da177e4 | 20 | |
32231a66 | 21 | #include "irq.h" |
aba20a82 | 22 | #include "kernel.h" |
32231a66 | 23 | |
ecbc42b7 DH |
24 | #define IRQ_IPI_SINGLE 12 |
25 | #define IRQ_IPI_MASK 13 | |
26 | #define IRQ_IPI_RESCHED 14 | |
1da177e4 LT |
27 | #define IRQ_CROSS_CALL 15 |
28 | ||
1a8a27c9 WF |
29 | static inline unsigned long |
30 | swap_ulong(volatile unsigned long *ptr, unsigned long val) | |
1da177e4 LT |
31 | { |
32 | __asm__ __volatile__("swap [%1], %0\n\t" : | |
33 | "=&r" (val), "=&r" (ptr) : | |
34 | "0" (val), "1" (ptr)); | |
35 | return val; | |
36 | } | |
37 | ||
2066aadd | 38 | void sun4m_cpu_pre_starting(void *arg) |
1da177e4 | 39 | { |
f9fd3488 | 40 | } |
1da177e4 | 41 | |
2066aadd | 42 | void sun4m_cpu_pre_online(void *arg) |
f9fd3488 SR |
43 | { |
44 | int cpuid = hard_smp_processor_id(); | |
1da177e4 | 45 | |
f9fd3488 SR |
46 | /* Allow master to continue. The master will then give us the |
47 | * go-ahead by setting the smp_commenced_mask and will wait without | |
48 | * timeouts until our setup is completed fully (signified by | |
49 | * our bit being set in the cpu_online_mask). | |
1da177e4 | 50 | */ |
1a8a27c9 | 51 | swap_ulong(&cpu_callin_map[cpuid], 1); |
1da177e4 | 52 | |
a54123e2 | 53 | /* XXX: What's up with all the flushes? */ |
5d83d666 DM |
54 | local_ops->cache_all(); |
55 | local_ops->tlb_all(); | |
aba20a82 | 56 | |
1da177e4 LT |
57 | /* Fix idle thread fields. */ |
58 | __asm__ __volatile__("ld [%0], %%g6\n\t" | |
59 | : : "r" (¤t_set[cpuid]) | |
60 | : "memory" /* paranoid */); | |
61 | ||
62 | /* Attach to the address space of init_task. */ | |
f1f10076 | 63 | mmgrab(&init_mm); |
1da177e4 LT |
64 | current->active_mm = &init_mm; |
65 | ||
fb1fece5 | 66 | while (!cpumask_test_cpu(cpuid, &smp_commenced_mask)) |
a54123e2 | 67 | mb(); |
1da177e4 LT |
68 | } |
69 | ||
1da177e4 LT |
70 | /* |
71 | * Cycle through the processors asking the PROM to start each one. | |
72 | */ | |
1da177e4 LT |
73 | void __init smp4m_boot_cpus(void) |
74 | { | |
62f08283 | 75 | sun4m_unmask_profile_irq(); |
5d83d666 | 76 | local_ops->cache_all(); |
a54123e2 | 77 | } |
1da177e4 | 78 | |
2066aadd | 79 | int smp4m_boot_one_cpu(int i, struct task_struct *idle) |
a54123e2 | 80 | { |
a54123e2 | 81 | unsigned long *entry = &sun4m_cpu_startup; |
a54123e2 BB |
82 | int timeout; |
83 | int cpu_node; | |
1da177e4 | 84 | |
a54123e2 | 85 | cpu_find_by_mid(i, &cpu_node); |
f0a2bc7e | 86 | current_set[i] = task_thread_info(idle); |
a54123e2 | 87 | |
a54123e2 | 88 | /* See trampoline.S for details... */ |
aba20a82 | 89 | entry += ((i - 1) * 3); |
1da177e4 | 90 | |
a54123e2 BB |
91 | /* |
92 | * Initialize the contexts table | |
93 | * Since the call to prom_startcpu() trashes the structure, | |
94 | * we need to re-initialize it for each cpu | |
95 | */ | |
96 | smp_penguin_ctable.which_io = 0; | |
97 | smp_penguin_ctable.phys_addr = (unsigned int) srmmu_ctx_table_phys; | |
98 | smp_penguin_ctable.reg_size = 0; | |
1da177e4 | 99 | |
a54123e2 | 100 | /* whirrr, whirrr, whirrrrrrrrr... */ |
aba20a82 | 101 | printk(KERN_INFO "Starting CPU %d at %p\n", i, entry); |
5d83d666 | 102 | local_ops->cache_all(); |
aba20a82 | 103 | prom_startcpu(cpu_node, &smp_penguin_ctable, 0, (char *)entry); |
a54123e2 BB |
104 | |
105 | /* wheee... it's going... */ | |
aba20a82 SR |
106 | for (timeout = 0; timeout < 10000; timeout++) { |
107 | if (cpu_callin_map[i]) | |
a54123e2 BB |
108 | break; |
109 | udelay(200); | |
1da177e4 LT |
110 | } |
111 | ||
a54123e2 | 112 | if (!(cpu_callin_map[i])) { |
aba20a82 | 113 | printk(KERN_ERR "Processor %d is stuck.\n", i); |
a54123e2 BB |
114 | return -ENODEV; |
115 | } | |
1da177e4 | 116 | |
5d83d666 | 117 | local_ops->cache_all(); |
a54123e2 BB |
118 | return 0; |
119 | } | |
120 | ||
121 | void __init smp4m_smp_done(void) | |
122 | { | |
123 | int i, first; | |
124 | int *prev; | |
125 | ||
126 | /* setup cpu list for irq rotation */ | |
127 | first = 0; | |
128 | prev = &first; | |
ec7c14bd RR |
129 | for_each_online_cpu(i) { |
130 | *prev = i; | |
131 | prev = &cpu_data(i).next; | |
1da177e4 | 132 | } |
a54123e2 | 133 | *prev = first; |
5d83d666 | 134 | local_ops->cache_all(); |
1da177e4 | 135 | |
1da177e4 | 136 | /* Ok, they are spinning and ready to go. */ |
1da177e4 LT |
137 | } |
138 | ||
4ba22b16 | 139 | static void sun4m_send_ipi(int cpu, int level) |
ecbc42b7 | 140 | { |
4ba22b16 | 141 | sbus_writel(SUN4M_SOFT_INT(level), &sun4m_irq_percpu[cpu]->set); |
ecbc42b7 DH |
142 | } |
143 | ||
4ba22b16 | 144 | static void sun4m_ipi_resched(int cpu) |
ecbc42b7 | 145 | { |
4ba22b16 | 146 | sun4m_send_ipi(cpu, IRQ_IPI_RESCHED); |
ecbc42b7 DH |
147 | } |
148 | ||
4ba22b16 | 149 | static void sun4m_ipi_single(int cpu) |
ecbc42b7 | 150 | { |
4ba22b16 | 151 | sun4m_send_ipi(cpu, IRQ_IPI_SINGLE); |
ecbc42b7 DH |
152 | } |
153 | ||
4ba22b16 | 154 | static void sun4m_ipi_mask_one(int cpu) |
ecbc42b7 | 155 | { |
4ba22b16 | 156 | sun4m_send_ipi(cpu, IRQ_IPI_MASK); |
ecbc42b7 DH |
157 | } |
158 | ||
1da177e4 LT |
159 | static struct smp_funcall { |
160 | smpfunc_t func; | |
161 | unsigned long arg1; | |
162 | unsigned long arg2; | |
163 | unsigned long arg3; | |
164 | unsigned long arg4; | |
165 | unsigned long arg5; | |
a54123e2 BB |
166 | unsigned long processors_in[SUN4M_NCPUS]; /* Set when ipi entered. */ |
167 | unsigned long processors_out[SUN4M_NCPUS]; /* Set when ipi exited. */ | |
1da177e4 LT |
168 | } ccall_info; |
169 | ||
170 | static DEFINE_SPINLOCK(cross_call_lock); | |
171 | ||
172 | /* Cross calls must be serialized, at least currently. */ | |
4ba22b16 | 173 | static void sun4m_cross_call(smpfunc_t func, cpumask_t mask, unsigned long arg1, |
c61c65cd | 174 | unsigned long arg2, unsigned long arg3, |
66e4f8c0 | 175 | unsigned long arg4) |
1da177e4 | 176 | { |
a54123e2 | 177 | register int ncpus = SUN4M_NCPUS; |
1da177e4 LT |
178 | unsigned long flags; |
179 | ||
180 | spin_lock_irqsave(&cross_call_lock, flags); | |
181 | ||
182 | /* Init function glue. */ | |
183 | ccall_info.func = func; | |
184 | ccall_info.arg1 = arg1; | |
185 | ccall_info.arg2 = arg2; | |
186 | ccall_info.arg3 = arg3; | |
187 | ccall_info.arg4 = arg4; | |
66e4f8c0 | 188 | ccall_info.arg5 = 0; |
1da177e4 LT |
189 | |
190 | /* Init receive/complete mapping, plus fire the IPI's off. */ | |
191 | { | |
1da177e4 LT |
192 | register int i; |
193 | ||
fb1fece5 KM |
194 | cpumask_clear_cpu(smp_processor_id(), &mask); |
195 | cpumask_and(&mask, cpu_online_mask, &mask); | |
aba20a82 | 196 | for (i = 0; i < ncpus; i++) { |
fb1fece5 | 197 | if (cpumask_test_cpu(i, &mask)) { |
1da177e4 LT |
198 | ccall_info.processors_in[i] = 0; |
199 | ccall_info.processors_out[i] = 0; | |
4ba22b16 | 200 | sun4m_send_ipi(i, IRQ_CROSS_CALL); |
1da177e4 LT |
201 | } else { |
202 | ccall_info.processors_in[i] = 1; | |
203 | ccall_info.processors_out[i] = 1; | |
204 | } | |
205 | } | |
206 | } | |
207 | ||
208 | { | |
209 | register int i; | |
210 | ||
211 | i = 0; | |
212 | do { | |
fb1fece5 | 213 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 214 | continue; |
aba20a82 | 215 | while (!ccall_info.processors_in[i]) |
1da177e4 | 216 | barrier(); |
aba20a82 | 217 | } while (++i < ncpus); |
1da177e4 LT |
218 | |
219 | i = 0; | |
220 | do { | |
fb1fece5 | 221 | if (!cpumask_test_cpu(i, &mask)) |
66e4f8c0 | 222 | continue; |
aba20a82 | 223 | while (!ccall_info.processors_out[i]) |
1da177e4 | 224 | barrier(); |
aba20a82 | 225 | } while (++i < ncpus); |
1da177e4 | 226 | } |
1da177e4 | 227 | spin_unlock_irqrestore(&cross_call_lock, flags); |
1da177e4 LT |
228 | } |
229 | ||
230 | /* Running cross calls. */ | |
231 | void smp4m_cross_call_irq(void) | |
232 | { | |
233 | int i = smp_processor_id(); | |
234 | ||
235 | ccall_info.processors_in[i] = 1; | |
236 | ccall_info.func(ccall_info.arg1, ccall_info.arg2, ccall_info.arg3, | |
237 | ccall_info.arg4, ccall_info.arg5); | |
238 | ccall_info.processors_out[i] = 1; | |
239 | } | |
240 | ||
241 | void smp4m_percpu_timer_interrupt(struct pt_regs *regs) | |
242 | { | |
0d84438d | 243 | struct pt_regs *old_regs; |
62f08283 | 244 | struct clock_event_device *ce; |
1da177e4 LT |
245 | int cpu = smp_processor_id(); |
246 | ||
0d84438d AV |
247 | old_regs = set_irq_regs(regs); |
248 | ||
62f08283 | 249 | ce = &per_cpu(sparc32_clockevent, cpu); |
1da177e4 | 250 | |
ff4aea45 | 251 | if (clockevent_state_periodic(ce)) |
62f08283 TK |
252 | sun4m_clear_profile_irq(cpu); |
253 | else | |
08c9388f | 254 | sparc_config.load_profile_irq(cpu, 0); /* Is this needless? */ |
1da177e4 | 255 | |
62f08283 TK |
256 | irq_enter(); |
257 | ce->event_handler(ce); | |
258 | irq_exit(); | |
1da177e4 | 259 | |
0d84438d | 260 | set_irq_regs(old_regs); |
1da177e4 LT |
261 | } |
262 | ||
4ba22b16 SR |
263 | static const struct sparc32_ipi_ops sun4m_ipi_ops = { |
264 | .cross_call = sun4m_cross_call, | |
265 | .resched = sun4m_ipi_resched, | |
266 | .single = sun4m_ipi_single, | |
267 | .mask_one = sun4m_ipi_mask_one, | |
268 | }; | |
269 | ||
1da177e4 LT |
270 | void __init sun4m_init_smp(void) |
271 | { | |
4ba22b16 | 272 | sparc32_ipi_ops = &sun4m_ipi_ops; |
1da177e4 | 273 | } |