[mirror_ubuntu-bionic-kernel.git] / arch / sparc / kernel / sun4v_tlb_miss.S

/* SPDX-License-Identifier: GPL-2.0 */
/* sun4v_tlb_miss.S: Sun4v TLB miss handlers.
 *
 * Copyright (C) 2006 <davem@davemloft.net>
 */

	.text
	.align	32

	/* Load ITLB fault information into VADDR and CTX, using BASE.  */
#define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
	ldx	[BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
	ldx	[BASE + HV_FAULT_I_CTX_OFFSET], CTX;

	/* Load DTLB fault information into VADDR and CTX, using BASE.  */
#define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
	ldx	[BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
	ldx	[BASE + HV_FAULT_D_CTX_OFFSET], CTX;

	/* DEST = (VADDR >> 22)
	 *
	 * Branch to ZERO_CTX_LABEL if context is zero.
	 */
#define	COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \
	srlx	VADDR, 22, DEST; \
	brz,pn	CTX, ZERO_CTX_LABEL; \
	 nop;

	/* Create TSB pointer.  This is something like:
	 *
	 * index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
	 * tsb_base = tsb_reg & ~0x7UL;
	 * tsb_index = ((vaddr >> HASH_SHIFT) & tsb_mask);
	 * tsb_ptr = tsb_base + (tsb_index * 16);
	 */
#define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \
	and	TSB_PTR, 0x7, TMP1;			\
	mov	512, TMP2;				\
	andn	TSB_PTR, 0x7, TSB_PTR;			\
	sllx	TMP2, TMP1, TMP2;			\
	srlx	VADDR, HASH_SHIFT, TMP1;		\
	sub	TMP2, 1, TMP2;				\
	and	TMP1, TMP2, TMP1;			\
	sllx	TMP1, 4, TMP1;				\
	add	TSB_PTR, TMP1, TSB_PTR;

sun4v_itlb_miss:
	/* Load MMU Miss base into %g2.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	
	/* Load UTSB reg into %g1.  */
	mov	SCRATCHPAD_UTSBREG1, %g1
	ldxa	[%g1] ASI_SCRATCHPAD, %g1

	LOAD_ITLB_INFO(%g2, %g4, %g5)
	COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_itlb_4v)
	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)

	/* Load TSB tag/pte into %g2/%g3 and compare the tag.  */
	ldda	[%g1] ASI_QUAD_LDD_PHYS_4V, %g2
	cmp	%g2, %g6
	bne,a,pn %xcc, tsb_miss_page_table_walk
	 mov	FAULT_CODE_ITLB, %g3
	andcc	%g3, _PAGE_EXEC_4V, %g0
	be,a,pn	%xcc, tsb_do_fault
	 mov	FAULT_CODE_ITLB, %g3

	/* We have a valid entry, make hypervisor call to load
	 * I-TLB and return from trap.
	 *
	 * %g3:	PTE
	 * %g4:	vaddr
	 */
sun4v_itlb_load:
	ldxa	[%g0] ASI_SCRATCHPAD, %g6
	mov	%o0, %g1		! save %o0
	mov	%o1, %g2		! save %o1
	mov	%o2, %g5		! save %o2
	mov	%o3, %g7		! save %o3
	mov	%g4, %o0		! vaddr
	ldx	[%g6 + HV_FAULT_I_CTX_OFFSET], %o1	! ctx
	mov	%g3, %o2		! PTE
	mov	HV_MMU_IMMU, %o3	! flags
	ta	HV_MMU_MAP_ADDR_TRAP
	brnz,pn	%o0, sun4v_itlb_error
	 mov	%g2, %o1		! restore %o1
	mov	%g1, %o0		! restore %o0
	mov	%g5, %o2		! restore %o2
	mov	%g7, %o3		! restore %o3

	retry

sun4v_dtlb_miss:
	/* Load MMU Miss base into %g2.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	
	/* Load UTSB reg into %g1.  */
	mov	SCRATCHPAD_UTSBREG1, %g1
	ldxa	[%g1] ASI_SCRATCHPAD, %g1

	LOAD_DTLB_INFO(%g2, %g4, %g5)
	COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_dtlb_4v)
	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)

	/* Load TSB tag/pte into %g2/%g3 and compare the tag.  */
	ldda	[%g1] ASI_QUAD_LDD_PHYS_4V, %g2
	cmp	%g2, %g6
	bne,a,pn %xcc, tsb_miss_page_table_walk
	 mov	FAULT_CODE_DTLB, %g3

	/* We have a valid entry, make hypervisor call to load
	 * D-TLB and return from trap.
	 *
	 * %g3:	PTE
	 * %g4:	vaddr
	 */
sun4v_dtlb_load:
	ldxa	[%g0] ASI_SCRATCHPAD, %g6
	mov	%o0, %g1		! save %o0
	mov	%o1, %g2		! save %o1
	mov	%o2, %g5		! save %o2
	mov	%o3, %g7		! save %o3
	mov	%g4, %o0		! vaddr
	ldx	[%g6 + HV_FAULT_D_CTX_OFFSET], %o1	! ctx
	mov	%g3, %o2		! PTE
	mov	HV_MMU_DMMU, %o3	! flags
	ta	HV_MMU_MAP_ADDR_TRAP
	brnz,pn	%o0, sun4v_dtlb_error
	 mov	%g2, %o1		! restore %o1
	mov	%g1, %o0		! restore %o0
	mov	%g5, %o2		! restore %o2
	mov	%g7, %o3		! restore %o3

	retry

sun4v_dtlb_prot:
	SET_GL(1)

	/* Load MMU Miss base into %g5.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g5
	
	ldx	[%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
	rdpr	%tl, %g1
	cmp	%g1, 1
	bgu,pn	%xcc, winfix_trampoline
	 mov	FAULT_CODE_DTLB | FAULT_CODE_WRITE, %g4
	ba,pt	%xcc, sparc64_realfault_common
	 nop

	/* Called from trap table:
	 * %g4:	vaddr
	 * %g5:	context
	 * %g6: TAG TARGET
	 */
sun4v_itsb_miss:
	mov	SCRATCHPAD_UTSBREG1, %g1
	ldxa	[%g1] ASI_SCRATCHPAD, %g1
	brz,pn	%g5, kvmap_itlb_4v
	 mov	FAULT_CODE_ITLB, %g3
	ba,a,pt	%xcc, sun4v_tsb_miss_common

	/* Called from trap table:
	 * %g4:	vaddr
	 * %g5:	context
	 * %g6: TAG TARGET
	 */
sun4v_dtsb_miss:
	mov	SCRATCHPAD_UTSBREG1, %g1
	ldxa	[%g1] ASI_SCRATCHPAD, %g1
	brz,pn	%g5, kvmap_dtlb_4v
	 mov	FAULT_CODE_DTLB, %g3

	/* fallthrough */

sun4v_tsb_miss_common:
	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g5, %g7)

	sub	%g2, TRAP_PER_CPU_FAULT_INFO, %g2

#if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
	mov	SCRATCHPAD_UTSBREG2, %g5
	ldxa	[%g5] ASI_SCRATCHPAD, %g5
	cmp	%g5, -1
	be,pt	%xcc, 80f
	 nop
	COMPUTE_TSB_PTR(%g5, %g4, REAL_HPAGE_SHIFT, %g2, %g7)

	/* That clobbered %g2, reload it.  */
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	sub	%g2, TRAP_PER_CPU_FAULT_INFO, %g2

80:	stx	%g5, [%g2 + TRAP_PER_CPU_TSB_HUGE_TEMP]
#endif

	ba,pt	%xcc, tsb_miss_page_table_walk_sun4v_fastpath
	 ldx	[%g2 + TRAP_PER_CPU_PGD_PADDR], %g7

sun4v_itlb_error:
	rdpr	%tl, %g1
	cmp	%g1, 1
	ble,pt	%icc, sun4v_bad_ra
	 or	%g0, FAULT_CODE_BAD_RA | FAULT_CODE_ITLB, %g1

	sethi	%hi(sun4v_err_itlb_vaddr), %g1
	stx	%g4, [%g1 + %lo(sun4v_err_itlb_vaddr)]
	sethi	%hi(sun4v_err_itlb_ctx), %g1
	ldxa	[%g0] ASI_SCRATCHPAD, %g6
	ldx	[%g6 + HV_FAULT_I_CTX_OFFSET], %o1
	stx	%o1, [%g1 + %lo(sun4v_err_itlb_ctx)]
	sethi	%hi(sun4v_err_itlb_pte), %g1
	stx	%g3, [%g1 + %lo(sun4v_err_itlb_pte)]
	sethi	%hi(sun4v_err_itlb_error), %g1
	stx	%o0, [%g1 + %lo(sun4v_err_itlb_error)]

	sethi	%hi(1f), %g7
	rdpr	%tl, %g4
	ba,pt	%xcc, etraptl1
1:	 or	%g7, %lo(1f), %g7
	mov	%l4, %o1
	call	sun4v_itlb_error_report
	 add	%sp, PTREGS_OFF, %o0

	/* NOTREACHED */

sun4v_dtlb_error:
	rdpr	%tl, %g1
	cmp	%g1, 1
	ble,pt	%icc, sun4v_bad_ra
	 or	%g0, FAULT_CODE_BAD_RA | FAULT_CODE_DTLB, %g1

	sethi	%hi(sun4v_err_dtlb_vaddr), %g1
	stx	%g4, [%g1 + %lo(sun4v_err_dtlb_vaddr)]
	sethi	%hi(sun4v_err_dtlb_ctx), %g1
	ldxa	[%g0] ASI_SCRATCHPAD, %g6
	ldx	[%g6 + HV_FAULT_D_CTX_OFFSET], %o1
	stx	%o1, [%g1 + %lo(sun4v_err_dtlb_ctx)]
	sethi	%hi(sun4v_err_dtlb_pte), %g1
	stx	%g3, [%g1 + %lo(sun4v_err_dtlb_pte)]
	sethi	%hi(sun4v_err_dtlb_error), %g1
	stx	%o0, [%g1 + %lo(sun4v_err_dtlb_error)]

	sethi	%hi(1f), %g7
	rdpr	%tl, %g4
	ba,pt	%xcc, etraptl1
1:	 or	%g7, %lo(1f), %g7
	mov	%l4, %o1
	call	sun4v_dtlb_error_report
	 add	%sp, PTREGS_OFF, %o0

	/* NOTREACHED */

sun4v_bad_ra:
	or	%g0, %g4, %g5
	ba,pt	%xcc, sparc64_realfault_common
	 or	%g1, %g0, %g4

	/* NOTREACHED */

	/* Instruction Access Exception, tl0. */
sun4v_iacc:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_I_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_insn_access_exception
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap

	/* Instruction Access Exception, tl1. */
sun4v_iacc_tl1:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_I_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etraptl1
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_insn_access_exception_tl1
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap

	/* Data Access Exception, tl0. */
sun4v_dacc:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_data_access_exception
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap

	/* Data Access Exception, tl1. */
sun4v_dacc_tl1:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etraptl1
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_data_access_exception_tl1
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap

	/* Memory Address Unaligned.  */
sun4v_mna:
	/* Window fixup? */
	rdpr	%tl, %g2
	cmp	%g2, 1
	ble,pt	%icc, 1f
	 nop

	SET_GL(1)
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g5
	mov	HV_FAULT_TYPE_UNALIGNED, %g3
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g4
	sllx	%g3, 16, %g3
	or	%g4, %g3, %g4
	ba,pt	%xcc, winfix_mna
	 rdpr	%tpc, %g3
	/* not reached */

1:	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	mov	HV_FAULT_TYPE_UNALIGNED, %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5

	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	sun4v_do_mna
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap
	 nop

	/* Privileged Action.  */
sun4v_privact:
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	call	do_privact
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap

	/* Unaligned ldd float, tl0. */
sun4v_lddfmna:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	handle_lddfmna
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap

	/* Unaligned std float, tl0. */
sun4v_stdfmna:
	ldxa	[%g0] ASI_SCRATCHPAD, %g2
	ldx	[%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	ldx	[%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	ldx	[%g2 + HV_FAULT_D_CTX_OFFSET], %g5
	sllx	%g3, 16, %g3
	or	%g5, %g3, %g5
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	mov	%l4, %o1
	mov	%l5, %o2
	call	handle_stdfmna
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap

#define BRANCH_ALWAYS	0x10680000
#define NOP		0x01000000
#define SUN4V_DO_PATCH(OLD, NEW)	\
	sethi	%hi(NEW), %g1; \
	or	%g1, %lo(NEW), %g1; \
	sethi	%hi(OLD), %g2; \
	or	%g2, %lo(OLD), %g2; \
	sub	%g1, %g2, %g1; \
	sethi	%hi(BRANCH_ALWAYS), %g3; \
	sll	%g1, 11, %g1; \
	srl	%g1, 11 + 2, %g1; \
	or	%g3, %lo(BRANCH_ALWAYS), %g3; \
	or	%g3, %g1, %g3; \
	stw	%g3, [%g2]; \
	sethi	%hi(NOP), %g3; \
	or	%g3, %lo(NOP), %g3; \
	stw	%g3, [%g2 + 0x4]; \
	flush	%g2;

	.globl	sun4v_patch_tlb_handlers
	.type	sun4v_patch_tlb_handlers,#function
sun4v_patch_tlb_handlers:
	SUN4V_DO_PATCH(tl0_iamiss, sun4v_itlb_miss)
	SUN4V_DO_PATCH(tl1_iamiss, sun4v_itlb_miss)
	SUN4V_DO_PATCH(tl0_damiss, sun4v_dtlb_miss)
	SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
	SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
	SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
	SUN4V_DO_PATCH(tl0_iax, sun4v_iacc)
	SUN4V_DO_PATCH(tl1_iax, sun4v_iacc_tl1)
	SUN4V_DO_PATCH(tl0_dax, sun4v_dacc)
	SUN4V_DO_PATCH(tl1_dax, sun4v_dacc_tl1)
	SUN4V_DO_PATCH(tl0_mna, sun4v_mna)
	SUN4V_DO_PATCH(tl1_mna, sun4v_mna)
	SUN4V_DO_PATCH(tl0_lddfmna, sun4v_lddfmna)
	SUN4V_DO_PATCH(tl0_stdfmna, sun4v_stdfmna)
	SUN4V_DO_PATCH(tl0_privact, sun4v_privact)
	retl
	 nop
	.size	sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
d257d5da DM	2	/* sun4v_tlb_miss.S: Sun4v TLB miss handlers.
	3	*
	4	* Copyright (C) 2006 <davem@davemloft.net>
	5	*/
	6
	7	.text
	8	.align 32
	9
36a68e77 DM	10	/* Load ITLB fault information into VADDR and CTX, using BASE. */
	11	#define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
	12	ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
	13	ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
	14
	15	/* Load DTLB fault information into VADDR and CTX, using BASE. */
	16	#define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
	17	ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
	18	ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
d257d5da	19
8b234274	20	/* DEST = (VADDR >> 22)
36a68e77	21	*
bcc28ee0	22	* Branch to ZERO_CTX_LABEL if context is zero.
d257d5da	23	*/
8b234274 DM	24	#define COMPUTE_TAG_TARGET(DEST, VADDR, CTX, ZERO_CTX_LABEL) \
8b234274 DM	25	srlx VADDR, 22, DEST; \
36a68e77	26	brz,pn CTX, ZERO_CTX_LABEL; \
8b234274	27	nop;
d257d5da DM	28
	29	/* Create TSB pointer. This is something like:
	30	*
	31	* index_mask = (512 << (tsb_reg & 0x7UL)) - 1UL;
	32	* tsb_base = tsb_reg & ~0x7UL;
dcc1e8dd	33	* tsb_index = ((vaddr >> HASH_SHIFT) & tsb_mask);
d257d5da DM	34	* tsb_ptr = tsb_base + (tsb_index * 16);
d257d5da DM	35	*/
dcc1e8dd	36	#define COMPUTE_TSB_PTR(TSB_PTR, VADDR, HASH_SHIFT, TMP1, TMP2) \
36a68e77 DM	37	and TSB_PTR, 0x7, TMP1; \
	38	mov 512, TMP2; \
	39	andn TSB_PTR, 0x7, TSB_PTR; \
	40	sllx TMP2, TMP1, TMP2; \
dcc1e8dd	41	srlx VADDR, HASH_SHIFT, TMP1; \
36a68e77 DM	42	sub TMP2, 1, TMP2; \
	43	and TMP1, TMP2, TMP1; \
	44	sllx TMP1, 4, TMP1; \
	45	add TSB_PTR, TMP1, TSB_PTR;
	46
	47	sun4v_itlb_miss:
	48	/* Load MMU Miss base into %g2. */
	49	ldxa [%g0] ASI_SCRATCHPAD, %g2
	50
	51	/* Load UTSB reg into %g1. */
	52	mov SCRATCHPAD_UTSBREG1, %g1
	53	ldxa [%g1] ASI_SCRATCHPAD, %g1
	54
	55	LOAD_ITLB_INFO(%g2, %g4, %g5)
8b234274	56	COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_itlb_4v)
dcc1e8dd	57	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
d257d5da DM	58
d257d5da DM	59	/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
c7f81d42	60	ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2
d257d5da	61	cmp %g2, %g6
d257d5da DM	62	bne,a,pn %xcc, tsb_miss_page_table_walk
d257d5da DM	63	mov FAULT_CODE_ITLB, %g3
45f791eb	64	andcc %g3, _PAGE_EXEC_4V, %g0
d257d5da DM	65	be,a,pn %xcc, tsb_do_fault
	66	mov FAULT_CODE_ITLB, %g3
	67
	68	/* We have a valid entry, make hypervisor call to load
	69	* I-TLB and return from trap.
	70	*
	71	* %g3: PTE
	72	* %g4: vaddr
d257d5da DM	73	*/
d257d5da DM	74	sun4v_itlb_load:
8b234274	75	ldxa [%g0] ASI_SCRATCHPAD, %g6
d257d5da DM	76	mov %o0, %g1 ! save %o0
	77	mov %o1, %g2 ! save %o1
	78	mov %o2, %g5 ! save %o2
	79	mov %o3, %g7 ! save %o3
	80	mov %g4, %o0 ! vaddr
8b234274	81	ldx [%g6 + HV_FAULT_I_CTX_OFFSET], %o1 ! ctx
d257d5da DM	82	mov %g3, %o2 ! PTE
	83	mov HV_MMU_IMMU, %o3 ! flags
	84	ta HV_MMU_MAP_ADDR_TRAP
6c8927c9 DM	85	brnz,pn %o0, sun4v_itlb_error
6c8927c9 DM	86	mov %g2, %o1 ! restore %o1
d257d5da	87	mov %g1, %o0 ! restore %o0
d257d5da DM	88	mov %g5, %o2 ! restore %o2
	89	mov %g7, %o3 ! restore %o3
	90
	91	retry
	92
	93	sun4v_dtlb_miss:
12eaa328 DM	94	/* Load MMU Miss base into %g2. */
12eaa328 DM	95	ldxa [%g0] ASI_SCRATCHPAD, %g2
d257d5da DM	96
d257d5da DM	97	/* Load UTSB reg into %g1. */
12eaa328	98	mov SCRATCHPAD_UTSBREG1, %g1
459b6e62	99	ldxa [%g1] ASI_SCRATCHPAD, %g1
d257d5da	100
36a68e77	101	LOAD_DTLB_INFO(%g2, %g4, %g5)
8b234274	102	COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_dtlb_4v)
dcc1e8dd	103	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g3, %g7)
d257d5da DM	104
d257d5da DM	105	/* Load TSB tag/pte into %g2/%g3 and compare the tag. */
c7f81d42	106	ldda [%g1] ASI_QUAD_LDD_PHYS_4V, %g2
d257d5da DM	107	cmp %g2, %g6
d257d5da DM	108	bne,a,pn %xcc, tsb_miss_page_table_walk
92daa77e	109	mov FAULT_CODE_DTLB, %g3
d257d5da DM	110
	111	/* We have a valid entry, make hypervisor call to load
	112	* D-TLB and return from trap.
	113	*
	114	* %g3: PTE
	115	* %g4: vaddr
d257d5da DM	116	*/
d257d5da DM	117	sun4v_dtlb_load:
8b234274	118	ldxa [%g0] ASI_SCRATCHPAD, %g6
d257d5da DM	119	mov %o0, %g1 ! save %o0
	120	mov %o1, %g2 ! save %o1
	121	mov %o2, %g5 ! save %o2
	122	mov %o3, %g7 ! save %o3
	123	mov %g4, %o0 ! vaddr
8b234274	124	ldx [%g6 + HV_FAULT_D_CTX_OFFSET], %o1 ! ctx
d257d5da DM	125	mov %g3, %o2 ! PTE
	126	mov HV_MMU_DMMU, %o3 ! flags
	127	ta HV_MMU_MAP_ADDR_TRAP
6c8927c9 DM	128	brnz,pn %o0, sun4v_dtlb_error
6c8927c9 DM	129	mov %g2, %o1 ! restore %o1
d257d5da	130	mov %g1, %o0 ! restore %o0
d257d5da DM	131	mov %g5, %o2 ! restore %o2
	132	mov %g7, %o3 ! restore %o3
	133
	134	retry
	135
	136	sun4v_dtlb_prot:
8b234274 DM	137	SET_GL(1)
8b234274 DM	138
24c523ec	139	/* Load MMU Miss base into %g5. */
8b234274	140	ldxa [%g0] ASI_SCRATCHPAD, %g5
d257d5da	141
8b234274	142	ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
d257d5da DM	143	rdpr %tl, %g1
d257d5da DM	144	cmp %g1, 1
8b234274	145	bgu,pn %xcc, winfix_trampoline
8b234274	146	mov FAULT_CODE_DTLB \| FAULT_CODE_WRITE, %g4
86d43258 DM	147	ba,pt %xcc, sparc64_realfault_common
86d43258 DM	148	nop
d257d5da	149
24c523ec DM	150	/* Called from trap table:
	151	* %g4: vaddr
	152	* %g5: context
	153	* %g6: TAG TARGET
aa9143b9 DM	154	*/
aa9143b9 DM	155	sun4v_itsb_miss:
459b6e62 DM	156	mov SCRATCHPAD_UTSBREG1, %g1
	157	ldxa [%g1] ASI_SCRATCHPAD, %g1
	158	brz,pn %g5, kvmap_itlb_4v
aa9143b9	159	mov FAULT_CODE_ITLB, %g3
6c8927c9	160	ba,a,pt %xcc, sun4v_tsb_miss_common
aa9143b9	161
24c523ec DM	162	/* Called from trap table:
	163	* %g4: vaddr
	164	* %g5: context
	165	* %g6: TAG TARGET
aa9143b9 DM	166	*/
aa9143b9 DM	167	sun4v_dtsb_miss:
459b6e62 DM	168	mov SCRATCHPAD_UTSBREG1, %g1
	169	ldxa [%g1] ASI_SCRATCHPAD, %g1
	170	brz,pn %g5, kvmap_dtlb_4v
	171	mov FAULT_CODE_DTLB, %g3
aa9143b9	172
24c523ec DM	173	/* fallthrough */
24c523ec DM	174
aa9143b9	175	sun4v_tsb_miss_common:
dcc1e8dd	176	COMPUTE_TSB_PTR(%g1, %g4, PAGE_SHIFT, %g5, %g7)
36a68e77	177
36a68e77	178	sub %g2, TRAP_PER_CPU_FAULT_INFO, %g2
dcc1e8dd	179
9e695d2e	180	#if defined(CONFIG_HUGETLB_PAGE) \|\| defined(CONFIG_TRANSPARENT_HUGEPAGE)
dcc1e8dd DM	181	mov SCRATCHPAD_UTSBREG2, %g5
	182	ldxa [%g5] ASI_SCRATCHPAD, %g5
	183	cmp %g5, -1
	184	be,pt %xcc, 80f
	185	nop
37b3a8ff	186	COMPUTE_TSB_PTR(%g5, %g4, REAL_HPAGE_SHIFT, %g2, %g7)
dcc1e8dd DM	187
	188	/* That clobbered %g2, reload it. */
	189	ldxa [%g0] ASI_SCRATCHPAD, %g2
	190	sub %g2, TRAP_PER_CPU_FAULT_INFO, %g2
	191
	192	80: stx %g5, [%g2 + TRAP_PER_CPU_TSB_HUGE_TEMP]
	193	#endif
	194
36a68e77 DM	195	ba,pt %xcc, tsb_miss_page_table_walk_sun4v_fastpath
36a68e77 DM	196	ldx [%g2 + TRAP_PER_CPU_PGD_PADDR], %g7
aa9143b9	197
6c8927c9	198	sun4v_itlb_error:
4ccb9272	199	rdpr %tl, %g1
	200	cmp %g1, 1
	201	ble,pt %icc, sun4v_bad_ra
	202	or %g0, FAULT_CODE_BAD_RA \| FAULT_CODE_ITLB, %g1
	203
6c8927c9 DM	204	sethi %hi(sun4v_err_itlb_vaddr), %g1
	205	stx %g4, [%g1 + %lo(sun4v_err_itlb_vaddr)]
	206	sethi %hi(sun4v_err_itlb_ctx), %g1
8b234274 DM	207	ldxa [%g0] ASI_SCRATCHPAD, %g6
8b234274 DM	208	ldx [%g6 + HV_FAULT_I_CTX_OFFSET], %o1
6c8927c9 DM	209	stx %o1, [%g1 + %lo(sun4v_err_itlb_ctx)]
	210	sethi %hi(sun4v_err_itlb_pte), %g1
	211	stx %g3, [%g1 + %lo(sun4v_err_itlb_pte)]
	212	sethi %hi(sun4v_err_itlb_error), %g1
	213	stx %o0, [%g1 + %lo(sun4v_err_itlb_error)]
	214
4ccb9272	215	sethi %hi(1f), %g7
6c8927c9	216	rdpr %tl, %g4
6c8927c9	217	ba,pt %xcc, etraptl1
4ccb9272	218	1: or %g7, %lo(1f), %g7
6320bceb	219	mov %l4, %o1
6c8927c9 DM	220	call sun4v_itlb_error_report
	221	add %sp, PTREGS_OFF, %o0
	222
	223	/* NOTREACHED */
	224
	225	sun4v_dtlb_error:
4ccb9272	226	rdpr %tl, %g1
	227	cmp %g1, 1
	228	ble,pt %icc, sun4v_bad_ra
	229	or %g0, FAULT_CODE_BAD_RA \| FAULT_CODE_DTLB, %g1
	230
6c8927c9 DM	231	sethi %hi(sun4v_err_dtlb_vaddr), %g1
	232	stx %g4, [%g1 + %lo(sun4v_err_dtlb_vaddr)]
	233	sethi %hi(sun4v_err_dtlb_ctx), %g1
8b234274 DM	234	ldxa [%g0] ASI_SCRATCHPAD, %g6
8b234274 DM	235	ldx [%g6 + HV_FAULT_D_CTX_OFFSET], %o1
6c8927c9 DM	236	stx %o1, [%g1 + %lo(sun4v_err_dtlb_ctx)]
	237	sethi %hi(sun4v_err_dtlb_pte), %g1
	238	stx %g3, [%g1 + %lo(sun4v_err_dtlb_pte)]
	239	sethi %hi(sun4v_err_dtlb_error), %g1
	240	stx %o0, [%g1 + %lo(sun4v_err_dtlb_error)]
	241
4ccb9272	242	sethi %hi(1f), %g7
6c8927c9	243	rdpr %tl, %g4
6c8927c9	244	ba,pt %xcc, etraptl1
4ccb9272	245	1: or %g7, %lo(1f), %g7
6320bceb	246	mov %l4, %o1
6c8927c9 DM	247	call sun4v_dtlb_error_report
	248	add %sp, PTREGS_OFF, %o0
	249
	250	/* NOTREACHED */
	251
4ccb9272	252	sun4v_bad_ra:
	253	or %g0, %g4, %g5
	254	ba,pt %xcc, sparc64_realfault_common
	255	or %g1, %g0, %g4
	256
	257	/* NOTREACHED */
	258
ed6b0b45 DM	259	/* Instruction Access Exception, tl0. */
ed6b0b45 DM	260	sun4v_iacc:
12eaa328 DM	261	ldxa [%g0] ASI_SCRATCHPAD, %g2
	262	ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
	263	ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
	264	ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
ed6b0b45 DM	265	sllx %g3, 16, %g3
	266	or %g5, %g3, %g5
	267	ba,pt %xcc, etrap
	268	rd %pc, %g7
	269	mov %l4, %o1
	270	mov %l5, %o2
	271	call sun4v_insn_access_exception
	272	add %sp, PTREGS_OFF, %o0
7697daaa	273	ba,a,pt %xcc, rtrap
ed6b0b45 DM	274
	275	/* Instruction Access Exception, tl1. */
	276	sun4v_iacc_tl1:
12eaa328 DM	277	ldxa [%g0] ASI_SCRATCHPAD, %g2
	278	ldx [%g2 + HV_FAULT_I_TYPE_OFFSET], %g3
	279	ldx [%g2 + HV_FAULT_I_ADDR_OFFSET], %g4
	280	ldx [%g2 + HV_FAULT_I_CTX_OFFSET], %g5
ed6b0b45 DM	281	sllx %g3, 16, %g3
	282	or %g5, %g3, %g5
	283	ba,pt %xcc, etraptl1
	284	rd %pc, %g7
	285	mov %l4, %o1
	286	mov %l5, %o2
	287	call sun4v_insn_access_exception_tl1
	288	add %sp, PTREGS_OFF, %o0
7697daaa	289	ba,a,pt %xcc, rtrap
ed6b0b45 DM	290
	291	/* Data Access Exception, tl0. */
	292	sun4v_dacc:
12eaa328 DM	293	ldxa [%g0] ASI_SCRATCHPAD, %g2
	294	ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	295	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	296	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	297	sllx %g3, 16, %g3
	298	or %g5, %g3, %g5
	299	ba,pt %xcc, etrap
	300	rd %pc, %g7
	301	mov %l4, %o1
	302	mov %l5, %o2
	303	call sun4v_data_access_exception
	304	add %sp, PTREGS_OFF, %o0
7697daaa	305	ba,a,pt %xcc, rtrap
ed6b0b45 DM	306
	307	/* Data Access Exception, tl1. */
	308	sun4v_dacc_tl1:
12eaa328 DM	309	ldxa [%g0] ASI_SCRATCHPAD, %g2
	310	ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	311	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	312	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	313	sllx %g3, 16, %g3
	314	or %g5, %g3, %g5
	315	ba,pt %xcc, etraptl1
	316	rd %pc, %g7
	317	mov %l4, %o1
	318	mov %l5, %o2
	319	call sun4v_data_access_exception_tl1
	320	add %sp, PTREGS_OFF, %o0
7697daaa	321	ba,a,pt %xcc, rtrap
ed6b0b45 DM	322
	323	/* Memory Address Unaligned. */
	324	sun4v_mna:
24c523ec DM	325	/* Window fixup? */
	326	rdpr %tl, %g2
	327	cmp %g2, 1
	328	ble,pt %icc, 1f
	329	nop
	330
	331	SET_GL(1)
bcc28ee0 DM	332	ldxa [%g0] ASI_SCRATCHPAD, %g2
bcc28ee0 DM	333	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g5
24c523ec	334	mov HV_FAULT_TYPE_UNALIGNED, %g3
bcc28ee0	335	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g4
24c523ec DM	336	sllx %g3, 16, %g3
	337	or %g4, %g3, %g4
	338	ba,pt %xcc, winfix_mna
	339	rdpr %tpc, %g3
	340	/* not reached */
	341
	342	1: ldxa [%g0] ASI_SCRATCHPAD, %g2
ed6b0b45	343	mov HV_FAULT_TYPE_UNALIGNED, %g3
12eaa328 DM	344	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
12eaa328 DM	345	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	346	sllx %g3, 16, %g3
	347	or %g5, %g3, %g5
	348
ed6b0b45 DM	349	ba,pt %xcc, etrap
	350	rd %pc, %g7
	351	mov %l4, %o1
	352	mov %l5, %o2
9f8a5b84	353	call sun4v_do_mna
ed6b0b45	354	add %sp, PTREGS_OFF, %o0
7697daaa	355	ba,a,pt %xcc, rtrap
0ae2d26f	356	nop
ed6b0b45 DM	357
	358	/* Privileged Action. */
	359	sun4v_privact:
	360	ba,pt %xcc, etrap
	361	rd %pc, %g7
	362	call do_privact
	363	add %sp, PTREGS_OFF, %o0
7697daaa	364	ba,a,pt %xcc, rtrap
ed6b0b45 DM	365
	366	/* Unaligned ldd float, tl0. */
	367	sun4v_lddfmna:
12eaa328 DM	368	ldxa [%g0] ASI_SCRATCHPAD, %g2
	369	ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	370	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	371	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	372	sllx %g3, 16, %g3
	373	or %g5, %g3, %g5
	374	ba,pt %xcc, etrap
	375	rd %pc, %g7
	376	mov %l4, %o1
	377	mov %l5, %o2
	378	call handle_lddfmna
	379	add %sp, PTREGS_OFF, %o0
7697daaa	380	ba,a,pt %xcc, rtrap
ed6b0b45 DM	381
	382	/* Unaligned std float, tl0. */
	383	sun4v_stdfmna:
12eaa328 DM	384	ldxa [%g0] ASI_SCRATCHPAD, %g2
	385	ldx [%g2 + HV_FAULT_D_TYPE_OFFSET], %g3
	386	ldx [%g2 + HV_FAULT_D_ADDR_OFFSET], %g4
	387	ldx [%g2 + HV_FAULT_D_CTX_OFFSET], %g5
ed6b0b45 DM	388	sllx %g3, 16, %g3
	389	or %g5, %g3, %g5
	390	ba,pt %xcc, etrap
	391	rd %pc, %g7
	392	mov %l4, %o1
	393	mov %l5, %o2
	394	call handle_stdfmna
	395	add %sp, PTREGS_OFF, %o0
7697daaa	396	ba,a,pt %xcc, rtrap
aa9143b9	397
d257d5da DM	398	#define BRANCH_ALWAYS 0x10680000
	399	#define NOP 0x01000000
	400	#define SUN4V_DO_PATCH(OLD, NEW) \
	401	sethi %hi(NEW), %g1; \
	402	or %g1, %lo(NEW), %g1; \
	403	sethi %hi(OLD), %g2; \
	404	or %g2, %lo(OLD), %g2; \
	405	sub %g1, %g2, %g1; \
	406	sethi %hi(BRANCH_ALWAYS), %g3; \
459b6e62 DM	407	sll %g1, 11, %g1; \
459b6e62 DM	408	srl %g1, 11 + 2, %g1; \
d257d5da DM	409	or %g3, %lo(BRANCH_ALWAYS), %g3; \
	410	or %g3, %g1, %g3; \
	411	stw %g3, [%g2]; \
	412	sethi %hi(NOP), %g3; \
	413	or %g3, %lo(NOP), %g3; \
	414	stw %g3, [%g2 + 0x4]; \
	415	flush %g2;
	416
	417	.globl sun4v_patch_tlb_handlers
	418	.type sun4v_patch_tlb_handlers,#function
	419	sun4v_patch_tlb_handlers:
	420	SUN4V_DO_PATCH(tl0_iamiss, sun4v_itlb_miss)
	421	SUN4V_DO_PATCH(tl1_iamiss, sun4v_itlb_miss)
	422	SUN4V_DO_PATCH(tl0_damiss, sun4v_dtlb_miss)
	423	SUN4V_DO_PATCH(tl1_damiss, sun4v_dtlb_miss)
	424	SUN4V_DO_PATCH(tl0_daprot, sun4v_dtlb_prot)
	425	SUN4V_DO_PATCH(tl1_daprot, sun4v_dtlb_prot)
ed6b0b45 DM	426	SUN4V_DO_PATCH(tl0_iax, sun4v_iacc)
	427	SUN4V_DO_PATCH(tl1_iax, sun4v_iacc_tl1)
	428	SUN4V_DO_PATCH(tl0_dax, sun4v_dacc)
	429	SUN4V_DO_PATCH(tl1_dax, sun4v_dacc_tl1)
	430	SUN4V_DO_PATCH(tl0_mna, sun4v_mna)
	431	SUN4V_DO_PATCH(tl1_mna, sun4v_mna)
	432	SUN4V_DO_PATCH(tl0_lddfmna, sun4v_lddfmna)
	433	SUN4V_DO_PATCH(tl0_stdfmna, sun4v_stdfmna)
	434	SUN4V_DO_PATCH(tl0_privact, sun4v_privact)
d257d5da DM	435	retl
	436	nop
	437	.size sun4v_patch_tlb_handlers,.-sun4v_patch_tlb_handlers