[mirror_ubuntu-bionic-kernel.git] / arch / sparc / kernel / time_32.c

/* linux/arch/sparc/kernel/time.c
 *
 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
 *
 * Chris Davis (cdavis@cois.on.ca) 03/27/1998
 * Added support for the intersil on the sun4/4200
 *
 * Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
 * Support for MicroSPARC-IIep, PCI CPU.
 *
 * This file handles the Sparc specific time handling details.
 *
 * 1997-09-10	Updated NTP code according to technical memorandum Jan '96
 *		"A Kernel Model for Precision Timekeeping" by Dave Mills
 */
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/param.h>
#include <linux/string.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/rtc.h>
#include <linux/rtc/m48t59.h>
#include <linux/timex.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/profile.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>

#include <asm/oplib.h>
#include <asm/timex.h>
#include <asm/timer.h>
#include <asm/irq.h>
#include <asm/io.h>
#include <asm/idprom.h>
#include <asm/page.h>
#include <asm/pcic.h>
#include <asm/irq_regs.h>
#include <asm/setup.h>

#include "irq.h"

static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
static __volatile__ u64 timer_cs_internal_counter = 0;
static char timer_cs_enabled = 0;

static struct clock_event_device timer_ce;
static char timer_ce_enabled = 0;

#ifdef CONFIG_SMP
DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
#endif

DEFINE_SPINLOCK(rtc_lock);
EXPORT_SYMBOL(rtc_lock);

static int set_rtc_mmss(unsigned long);

unsigned long profile_pc(struct pt_regs *regs)
{
	extern char __copy_user_begin[], __copy_user_end[];
	extern char __bzero_begin[], __bzero_end[];

	unsigned long pc = regs->pc;

	if (in_lock_functions(pc) ||
	    (pc >= (unsigned long) __copy_user_begin &&
	     pc < (unsigned long) __copy_user_end) ||
	    (pc >= (unsigned long) __bzero_begin &&
	     pc < (unsigned long) __bzero_end))
		pc = regs->u_regs[UREG_RETPC];
	return pc;
}

EXPORT_SYMBOL(profile_pc);

__volatile__ unsigned int *master_l10_counter;

int update_persistent_clock(struct timespec now)
{
	return set_rtc_mmss(now.tv_sec);
}

irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
{
	if (timer_cs_enabled) {
		write_seqlock(&timer_cs_lock);
		timer_cs_internal_counter++;
		clear_clock_irq();
		write_sequnlock(&timer_cs_lock);
	} else {
		clear_clock_irq();
	}

	if (timer_ce_enabled)
		timer_ce.event_handler(&timer_ce);

	return IRQ_HANDLED;
}

static void timer_ce_set_mode(enum clock_event_mode mode,
			      struct clock_event_device *evt)
{
	switch (mode) {
		case CLOCK_EVT_MODE_PERIODIC:
		case CLOCK_EVT_MODE_RESUME:
			timer_ce_enabled = 1;
			break;
		case CLOCK_EVT_MODE_SHUTDOWN:
			timer_ce_enabled = 0;
			break;
		default:
			break;
	}
	smp_mb();
}

static __init void setup_timer_ce(void)
{
	struct clock_event_device *ce = &timer_ce;

	BUG_ON(smp_processor_id() != boot_cpu_id);

	ce->name     = "timer_ce";
	ce->rating   = 100;
	ce->features = CLOCK_EVT_FEAT_PERIODIC;
	ce->set_mode = timer_ce_set_mode;
	ce->cpumask  = cpu_possible_mask;
	ce->shift    = 32;
	ce->mult     = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	                      ce->shift);
	clockevents_register_device(ce);
}

static unsigned int sbus_cycles_offset(void)
{
	unsigned int val, offset;

	val = *master_l10_counter;
	offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;

	/* Limit hit? */
	if (val & TIMER_LIMIT_BIT)
		offset += sparc_config.cs_period;

	return offset;
}

static cycle_t timer_cs_read(struct clocksource *cs)
{
	unsigned int seq, offset;
	u64 cycles;

	do {
		seq = read_seqbegin(&timer_cs_lock);

		cycles = timer_cs_internal_counter;
		offset = sparc_config.get_cycles_offset();
	} while (read_seqretry(&timer_cs_lock, seq));

	/* Count absolute cycles */
	cycles *= sparc_config.cs_period;
	cycles += offset;

	return cycles;
}

static struct clocksource timer_cs = {
	.name	= "timer_cs",
	.rating	= 100,
	.read	= timer_cs_read,
	.mask	= CLOCKSOURCE_MASK(64),
	.shift	= 2,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static __init int setup_timer_cs(void)
{
	timer_cs_enabled = 1;
	timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate,
	                                    timer_cs.shift);

	return clocksource_register(&timer_cs);
}

#ifdef CONFIG_SMP
static void percpu_ce_setup(enum clock_event_mode mode,
			struct clock_event_device *evt)
{
	int cpu = __first_cpu(evt->cpumask);

	switch (mode) {
		case CLOCK_EVT_MODE_PERIODIC:
			load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
			break;
		case CLOCK_EVT_MODE_ONESHOT:
		case CLOCK_EVT_MODE_SHUTDOWN:
		case CLOCK_EVT_MODE_UNUSED:
			load_profile_irq(cpu, 0);
			break;
		default:
			break;
	}
}

static int percpu_ce_set_next_event(unsigned long delta,
				    struct clock_event_device *evt)
{
	int cpu = __first_cpu(evt->cpumask);
	unsigned int next = (unsigned int)delta;

	load_profile_irq(cpu, next);
	return 0;
}

void register_percpu_ce(int cpu)
{
	struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
	unsigned int features = CLOCK_EVT_FEAT_PERIODIC;

	if (sparc_config.features & FEAT_L14_ONESHOT)
		features |= CLOCK_EVT_FEAT_ONESHOT;

	ce->name           = "percpu_ce";
	ce->rating         = 200;
	ce->features       = features;
	ce->set_mode       = percpu_ce_setup;
	ce->set_next_event = percpu_ce_set_next_event;
	ce->cpumask        = cpumask_of(cpu);
	ce->shift          = 32;
	ce->mult           = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	                            ce->shift);
	ce->max_delta_ns   = clockevent_delta2ns(sparc_config.clock_rate, ce);
	ce->min_delta_ns   = clockevent_delta2ns(100, ce);

	clockevents_register_device(ce);
}
#endif

static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct m48t59_plat_data *pdata = pdev->dev.platform_data;

	return readb(pdata->ioaddr + ofs);
}

static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct m48t59_plat_data *pdata = pdev->dev.platform_data;

	writeb(val, pdata->ioaddr + ofs);
}

static struct m48t59_plat_data m48t59_data = {
	.read_byte = mostek_read_byte,
	.write_byte = mostek_write_byte,
};

/* resource is set at runtime */
static struct platform_device m48t59_rtc = {
	.name		= "rtc-m48t59",
	.id		= 0,
	.num_resources	= 1,
	.dev	= {
		.platform_data = &m48t59_data,
	},
};

static int __devinit clock_probe(struct platform_device *op)
{
	struct device_node *dp = op->dev.of_node;
	const char *model = of_get_property(dp, "model", NULL);

	if (!model)
		return -ENODEV;

	/* Only the primary RTC has an address property */
	if (!of_find_property(dp, "address", NULL))
		return -ENODEV;

	m48t59_rtc.resource = &op->resource[0];
	if (!strcmp(model, "mk48t02")) {
		/* Map the clock register io area read-only */
		m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
						2048, "rtc-m48t59");
		m48t59_data.type = M48T59RTC_TYPE_M48T02;
	} else if (!strcmp(model, "mk48t08")) {
		m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
						8192, "rtc-m48t59");
		m48t59_data.type = M48T59RTC_TYPE_M48T08;
	} else
		return -ENODEV;

	if (platform_device_register(&m48t59_rtc) < 0)
		printk(KERN_ERR "Registering RTC device failed\n");

	return 0;
}

static struct of_device_id clock_match[] = {
	{
		.name = "eeprom",
	},
	{},
};

static struct platform_driver clock_driver = {
	.probe		= clock_probe,
	.driver = {
		.name = "rtc",
		.owner = THIS_MODULE,
		.of_match_table = clock_match,
	},
};


/* Probe for the mostek real time clock chip. */
static int __init clock_init(void)
{
	return platform_driver_register(&clock_driver);
}
/* Must be after subsys_initcall() so that busses are probed.  Must
 * be before device_initcall() because things like the RTC driver
 * need to see the clock registers.
 */
fs_initcall(clock_init);

static void __init sparc32_late_time_init(void)
{
	if (sparc_config.features & FEAT_L10_CLOCKEVENT)
		setup_timer_ce();
	if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
		setup_timer_cs();
#ifdef CONFIG_SMP
	register_percpu_ce(smp_processor_id());
#endif
}

static void __init sbus_time_init(void)
{
	sparc_config.get_cycles_offset = sbus_cycles_offset;
	sparc_config.init_timers();
}

void __init time_init(void)
{
	btfixup();

	sparc_config.features = 0;
	late_time_init = sparc32_late_time_init;

	if (pcic_present())
		pci_time_init();
	else
		sbus_time_init();
}


static int set_rtc_mmss(unsigned long secs)
{
	struct rtc_device *rtc = rtc_class_open("rtc0");
	int err = -1;

	if (rtc) {
		err = rtc_set_mmss(rtc, secs);
		rtc_class_close(rtc);
	}

	return err;
}
Commit	Line	Data
64d329ee	1	/* linux/arch/sparc/kernel/time.c
1da177e4	2	*
64d329ee	3	* Copyright (C) 1995 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	* Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
	5	*
	6	* Chris Davis (cdavis@cois.on.ca) 03/27/1998
	7	* Added support for the intersil on the sun4/4200
	8	*
	9	* Gleb Raiko (rajko@mech.math.msu.su) 08/18/1998
	10	* Support for MicroSPARC-IIep, PCI CPU.
	11	*
	12	* This file handles the Sparc specific time handling details.
	13	*
	14	* 1997-09-10 Updated NTP code according to technical memorandum Jan '96
	15	* "A Kernel Model for Precision Timekeeping" by Dave Mills
	16	*/
1da177e4 LT	17	#include <linux/errno.h>
	18	#include <linux/module.h>
	19	#include <linux/sched.h>
	20	#include <linux/kernel.h>
	21	#include <linux/param.h>
	22	#include <linux/string.h>
	23	#include <linux/mm.h>
	24	#include <linux/interrupt.h>
	25	#include <linux/time.h>
c4cbe6f9 DM	26	#include <linux/rtc.h>
c4cbe6f9 DM	27	#include <linux/rtc/m48t59.h>
1da177e4	28	#include <linux/timex.h>
62f08283 TK	29	#include <linux/clocksource.h>
62f08283 TK	30	#include <linux/clockchips.h>
1da177e4 LT	31	#include <linux/init.h>
	32	#include <linux/pci.h>
	33	#include <linux/ioport.h>
	34	#include <linux/profile.h>
454eeb2d	35	#include <linux/of.h>
764f2579	36	#include <linux/of_device.h>
c4cbe6f9	37	#include <linux/platform_device.h>
1da177e4 LT	38
1da177e4 LT	39	#include <asm/oplib.h>
0299b137	40	#include <asm/timex.h>
1da177e4	41	#include <asm/timer.h>
1da177e4 LT	42	#include <asm/irq.h>
	43	#include <asm/io.h>
	44	#include <asm/idprom.h>
1da177e4 LT	45	#include <asm/page.h>
1da177e4 LT	46	#include <asm/pcic.h>
0d84438d	47	#include <asm/irq_regs.h>
62f08283	48	#include <asm/setup.h>
1da177e4	49
32231a66 AV	50	#include "irq.h"
32231a66 AV	51
62f08283 TK	52	static __cacheline_aligned_in_smp DEFINE_SEQLOCK(timer_cs_lock);
	53	static __volatile__ u64 timer_cs_internal_counter = 0;
	54	static char timer_cs_enabled = 0;
	55
	56	static struct clock_event_device timer_ce;
	57	static char timer_ce_enabled = 0;
	58
	59	#ifdef CONFIG_SMP
	60	DEFINE_PER_CPU(struct clock_event_device, sparc32_clockevent);
	61	#endif
	62
1da177e4	63	DEFINE_SPINLOCK(rtc_lock);
6943f3da SR	64	EXPORT_SYMBOL(rtc_lock);
6943f3da SR	65
1da177e4	66	static int set_rtc_mmss(unsigned long);
1da177e4	67
1da177e4 LT	68	unsigned long profile_pc(struct pt_regs *regs)
	69	{
	70	extern char __copy_user_begin[], __copy_user_end[];
1da177e4	71	extern char __bzero_begin[], __bzero_end[];
1da177e4 LT	72
	73	unsigned long pc = regs->pc;
	74
	75	if (in_lock_functions(pc) \|\|
	76	(pc >= (unsigned long) __copy_user_begin &&
	77	pc < (unsigned long) __copy_user_end) \|\|
1da177e4	78	(pc >= (unsigned long) __bzero_begin &&
8a8b836b	79	pc < (unsigned long) __bzero_end))
1da177e4 LT	80	pc = regs->u_regs[UREG_RETPC];
	81	return pc;
	82	}
	83
9550e59c MH	84	EXPORT_SYMBOL(profile_pc);
9550e59c MH	85
1da177e4	86	__volatile__ unsigned int *master_l10_counter;
1da177e4	87
f5c9c9be JS	88	int update_persistent_clock(struct timespec now)
	89	{
	90	return set_rtc_mmss(now.tv_sec);
	91	}
	92
62f08283 TK	93	irqreturn_t notrace timer_interrupt(int dummy, void *dev_id)
	94	{
	95	if (timer_cs_enabled) {
	96	write_seqlock(&timer_cs_lock);
	97	timer_cs_internal_counter++;
	98	clear_clock_irq();
	99	write_sequnlock(&timer_cs_lock);
	100	} else {
	101	clear_clock_irq();
	102	}
1da177e4	103
62f08283 TK	104	if (timer_ce_enabled)
62f08283 TK	105	timer_ce.event_handler(&timer_ce);
1da177e4	106
62f08283 TK	107	return IRQ_HANDLED;
	108	}
	109
	110	static void timer_ce_set_mode(enum clock_event_mode mode,
	111	struct clock_event_device *evt)
1da177e4	112	{
62f08283 TK	113	switch (mode) {
	114	case CLOCK_EVT_MODE_PERIODIC:
	115	case CLOCK_EVT_MODE_RESUME:
	116	timer_ce_enabled = 1;
	117	break;
	118	case CLOCK_EVT_MODE_SHUTDOWN:
	119	timer_ce_enabled = 0;
	120	break;
	121	default:
	122	break;
	123	}
	124	smp_mb();
	125	}
	126
	127	static __init void setup_timer_ce(void)
	128	{
	129	struct clock_event_device *ce = &timer_ce;
	130
	131	BUG_ON(smp_processor_id() != boot_cpu_id);
	132
	133	ce->name = "timer_ce";
	134	ce->rating = 100;
	135	ce->features = CLOCK_EVT_FEAT_PERIODIC;
	136	ce->set_mode = timer_ce_set_mode;
	137	ce->cpumask = cpu_possible_mask;
	138	ce->shift = 32;
	139	ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
	140	ce->shift);
	141	clockevents_register_device(ce);
	142	}
1da177e4	143
62f08283 TK	144	static unsigned int sbus_cycles_offset(void)
	145	{
	146	unsigned int val, offset;
1da177e4	147
62f08283 TK	148	val = *master_l10_counter;
62f08283 TK	149	offset = (val >> TIMER_VALUE_SHIFT) & TIMER_VALUE_MASK;
1da177e4	150
62f08283 TK	151	/* Limit hit? */
	152	if (val & TIMER_LIMIT_BIT)
	153	offset += sparc_config.cs_period;
	154
	155	return offset;
1da177e4 LT	156	}
1da177e4 LT	157
62f08283 TK	158	static cycle_t timer_cs_read(struct clocksource *cs)
	159	{
	160	unsigned int seq, offset;
	161	u64 cycles;
	162
	163	do {
	164	seq = read_seqbegin(&timer_cs_lock);
	165
	166	cycles = timer_cs_internal_counter;
	167	offset = sparc_config.get_cycles_offset();
	168	} while (read_seqretry(&timer_cs_lock, seq));
	169
	170	/* Count absolute cycles */
	171	cycles *= sparc_config.cs_period;
	172	cycles += offset;
	173
	174	return cycles;
	175	}
	176
	177	static struct clocksource timer_cs = {
	178	.name = "timer_cs",
	179	.rating = 100,
	180	.read = timer_cs_read,
	181	.mask = CLOCKSOURCE_MASK(64),
	182	.shift = 2,
	183	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	184	};
	185
	186	static __init int setup_timer_cs(void)
	187	{
	188	timer_cs_enabled = 1;
	189	timer_cs.mult = clocksource_hz2mult(sparc_config.clock_rate,
	190	timer_cs.shift);
	191
	192	return clocksource_register(&timer_cs);
	193	}
	194
	195	#ifdef CONFIG_SMP
	196	static void percpu_ce_setup(enum clock_event_mode mode,
	197	struct clock_event_device *evt)
	198	{
	199	int cpu = __first_cpu(evt->cpumask);
	200
	201	switch (mode) {
	202	case CLOCK_EVT_MODE_PERIODIC:
	203	load_profile_irq(cpu, SBUS_CLOCK_RATE / HZ);
	204	break;
	205	case CLOCK_EVT_MODE_ONESHOT:
	206	case CLOCK_EVT_MODE_SHUTDOWN:
	207	case CLOCK_EVT_MODE_UNUSED:
	208	load_profile_irq(cpu, 0);
	209	break;
	210	default:
	211	break;
	212	}
	213	}
	214
	215	static int percpu_ce_set_next_event(unsigned long delta,
	216	struct clock_event_device *evt)
	217	{
	218	int cpu = __first_cpu(evt->cpumask);
	219	unsigned int next = (unsigned int)delta;
	220
	221	load_profile_irq(cpu, next);
222	return 0;
223	}
224
225	void register_percpu_ce(int cpu)
226	{
227	struct clock_event_device *ce = &per_cpu(sparc32_clockevent, cpu);
228	unsigned int features = CLOCK_EVT_FEAT_PERIODIC;
229
230	if (sparc_config.features & FEAT_L14_ONESHOT)
231	features \|= CLOCK_EVT_FEAT_ONESHOT;
232
233	ce->name = "percpu_ce";
234	ce->rating = 200;
235	ce->features = features;
236	ce->set_mode = percpu_ce_setup;
237	ce->set_next_event = percpu_ce_set_next_event;
238	ce->cpumask = cpumask_of(cpu);
239	ce->shift = 32;
240	ce->mult = div_sc(sparc_config.clock_rate, NSEC_PER_SEC,
241	ce->shift);
242	ce->max_delta_ns = clockevent_delta2ns(sparc_config.clock_rate, ce);
243	ce->min_delta_ns = clockevent_delta2ns(100, ce);
244
245	clockevents_register_device(ce);
246	}
247	#endif
248
c4cbe6f9	249	static unsigned char mostek_read_byte(struct device *dev, u32 ofs)
1da177e4	250	{
c4cbe6f9 DM	251	struct platform_device *pdev = to_platform_device(dev);
c4cbe6f9 DM	252	struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c KH	253
12a9ee3c KH	254	return readb(pdata->ioaddr + ofs);
1da177e4 LT	255	}
1da177e4 LT	256
c4cbe6f9	257	static void mostek_write_byte(struct device *dev, u32 ofs, u8 val)
1da177e4	258	{
c4cbe6f9 DM	259	struct platform_device *pdev = to_platform_device(dev);
c4cbe6f9 DM	260	struct m48t59_plat_data *pdata = pdev->dev.platform_data;
12a9ee3c KH	261
12a9ee3c KH	262	writeb(val, pdata->ioaddr + ofs);
1da177e4 LT	263	}
1da177e4 LT	264
c4cbe6f9 DM	265	static struct m48t59_plat_data m48t59_data = {
	266	.read_byte = mostek_read_byte,
	267	.write_byte = mostek_write_byte,
	268	};
	269
	270	/* resource is set at runtime */
	271	static struct platform_device m48t59_rtc = {
	272	.name = "rtc-m48t59",
	273	.id = 0,
	274	.num_resources = 1,
	275	.dev = {
	276	.platform_data = &m48t59_data,
	277	},
	278	};
96ba989d	279
4ebb24f7	280	static int __devinit clock_probe(struct platform_device *op)
1da177e4	281	{
61c7a080	282	struct device_node *dp = op->dev.of_node;
8271f042	283	const char *model = of_get_property(dp, "model", NULL);
1da177e4	284
ee5caf0e DM	285	if (!model)
ee5caf0e DM	286	return -ENODEV;
1da177e4	287
1c833bc3 KO	288	/* Only the primary RTC has an address property */
	289	if (!of_find_property(dp, "address", NULL))
	290	return -ENODEV;
	291
c4cbe6f9	292	m48t59_rtc.resource = &op->resource[0];
ee5caf0e	293	if (!strcmp(model, "mk48t02")) {
1da177e4	294	/* Map the clock register io area read-only */
c4cbe6f9 DM	295	m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
	296	2048, "rtc-m48t59");
	297	m48t59_data.type = M48T59RTC_TYPE_M48T02;
ee5caf0e	298	} else if (!strcmp(model, "mk48t08")) {
c4cbe6f9 DM	299	m48t59_data.ioaddr = of_ioremap(&op->resource[0], 0,
	300	8192, "rtc-m48t59");
	301	m48t59_data.type = M48T59RTC_TYPE_M48T08;
ee5caf0e DM	302	} else
ee5caf0e DM	303	return -ENODEV;
1da177e4	304
c4cbe6f9 DM	305	if (platform_device_register(&m48t59_rtc) < 0)
c4cbe6f9 DM	306	printk(KERN_ERR "Registering RTC device failed\n");
96ba989d	307
ee5caf0e DM	308	return 0;
	309	}
	310
505d9147	311	static struct of_device_id clock_match[] = {
ee5caf0e DM	312	{
	313	.name = "eeprom",
	314	},
	315	{},
	316	};
	317
4ebb24f7	318	static struct platform_driver clock_driver = {
ee5caf0e	319	.probe = clock_probe,
4018294b GL	320	.driver = {
	321	.name = "rtc",
	322	.owner = THIS_MODULE,
	323	.of_match_table = clock_match,
a2cd1558	324	},
ee5caf0e DM	325	};
	326
	327
	328	/* Probe for the mostek real time clock chip. */
96ba989d	329	static int __init clock_init(void)
ee5caf0e	330	{
4ebb24f7	331	return platform_driver_register(&clock_driver);
1da177e4	332	}
96ba989d BB	333	/* Must be after subsys_initcall() so that busses are probed. Must
	334	* be before device_initcall() because things like the RTC driver
	335	* need to see the clock registers.
	336	*/
	337	fs_initcall(clock_init);
96ba989d	338
62f08283	339	static void __init sparc32_late_time_init(void)
1da177e4	340	{
62f08283 TK	341	if (sparc_config.features & FEAT_L10_CLOCKEVENT)
	342	setup_timer_ce();
	343	if (sparc_config.features & FEAT_L10_CLOCKSOURCE)
	344	setup_timer_cs();
	345	#ifdef CONFIG_SMP
	346	register_percpu_ce(smp_processor_id());
	347	#endif
1da177e4 LT	348	}
1da177e4 LT	349
62f08283	350	static void __init sbus_time_init(void)
1da177e4	351	{
62f08283 TK	352	sparc_config.get_cycles_offset = sbus_cycles_offset;
62f08283 TK	353	sparc_config.init_timers();
1da177e4 LT	354	}
1da177e4 LT	355
62f08283	356	void __init time_init(void)
1da177e4	357	{
0299b137	358	btfixup();
1da177e4	359
62f08283 TK	360	sparc_config.features = 0;
62f08283 TK	361	late_time_init = sparc32_late_time_init;
1da177e4	362
06010fb5	363	if (pcic_present())
0299b137	364	pci_time_init();
06010fb5 SR	365	else
06010fb5 SR	366	sbus_time_init();
1da177e4 LT	367	}
1da177e4 LT	368
0299b137	369
c4cbe6f9	370	static int set_rtc_mmss(unsigned long secs)
1da177e4	371	{
c4cbe6f9	372	struct rtc_device *rtc = rtc_class_open("rtc0");
ab138c03	373	int err = -1;
1da177e4	374
ab138c03 DM	375	if (rtc) {
	376	err = rtc_set_mmss(rtc, secs);
	377	rtc_class_close(rtc);
	378	}
1da177e4	379
ab138c03	380	return err;
1da177e4	381	}