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Commit | Line | Data |
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1b1fbbca | 1 | /* ld script for sparc32/sparc64 kernel */ |
1da177e4 LT |
2 | |
3 | #include <asm-generic/vmlinux.lds.h> | |
b74e34db | 4 | |
bcbe40eb | 5 | #include <asm/page.h> |
b74e34db | 6 | #include <asm/thread_info.h> |
1da177e4 | 7 | |
1b1fbbca SR |
8 | #ifdef CONFIG_SPARC32 |
9 | #define INITIAL_ADDRESS 0x10000 + SIZEOF_HEADERS | |
10 | #define TEXTSTART 0xf0004000 | |
11 | ||
12 | #define SMP_CACHE_BYTES_SHIFT 5 | |
13 | ||
14 | #else | |
15 | #define SMP_CACHE_BYTES_SHIFT 6 | |
16 | #define INITIAL_ADDRESS 0x4000 | |
17 | #define TEXTSTART 0x0000000000404000 | |
18 | ||
19 | #endif | |
20 | ||
21 | #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) | |
22 | ||
23 | #ifdef CONFIG_SPARC32 | |
1da177e4 LT |
24 | OUTPUT_FORMAT("elf32-sparc", "elf32-sparc", "elf32-sparc") |
25 | OUTPUT_ARCH(sparc) | |
26 | ENTRY(_start) | |
27 | jiffies = jiffies_64 + 4; | |
1b1fbbca SR |
28 | #else |
29 | /* sparc64 */ | |
30 | OUTPUT_FORMAT("elf64-sparc", "elf64-sparc", "elf64-sparc") | |
31 | OUTPUT_ARCH(sparc:v9a) | |
32 | ENTRY(_start) | |
33 | jiffies = jiffies_64; | |
34 | #endif | |
35 | ||
1da177e4 LT |
36 | SECTIONS |
37 | { | |
1b1fbbca SR |
38 | /* swapper_low_pmd_dir is sparc64 only */ |
39 | swapper_low_pmd_dir = 0x0000000000402000; | |
40 | . = INITIAL_ADDRESS; | |
41 | .text TEXTSTART : | |
bcbe40eb SR |
42 | { |
43 | _text = .; | |
ce8a7424 | 44 | HEAD_TEXT |
bcbe40eb SR |
45 | TEXT_TEXT |
46 | SCHED_TEXT | |
47 | LOCK_TEXT | |
1b1fbbca | 48 | KPROBES_TEXT |
9960e9e8 | 49 | IRQENTRY_TEXT |
bcbe40eb SR |
50 | *(.gnu.warning) |
51 | } = 0 | |
52 | _etext = .; | |
1b1fbbca SR |
53 | |
54 | RO_DATA(PAGE_SIZE) | |
bcbe40eb SR |
55 | .data1 : { |
56 | *(.data1) | |
57 | } | |
3240a77b GT |
58 | RW_DATA_SECTION(SMP_CACHE_BYTES, 0, THREAD_SIZE) |
59 | ||
b74e34db | 60 | /* End of data section */ |
bcbe40eb | 61 | _edata = .; |
b74e34db | 62 | |
bcbe40eb SR |
63 | .fixup : { |
64 | __start___fixup = .; | |
65 | *(.fixup) | |
66 | __stop___fixup = .; | |
67 | } | |
3240a77b | 68 | EXCEPTION_TABLE(16) |
bcbe40eb SR |
69 | NOTES |
70 | ||
71 | . = ALIGN(PAGE_SIZE); | |
3240a77b GT |
72 | __init_begin = ALIGN(PAGE_SIZE); |
73 | INIT_TEXT_SECTION(PAGE_SIZE) | |
bcbe40eb | 74 | __init_text_end = .; |
3240a77b | 75 | INIT_DATA_SECTION(16) |
67d38229 | 76 | |
1b1fbbca SR |
77 | . = ALIGN(4); |
78 | .tsb_ldquad_phys_patch : { | |
79 | __tsb_ldquad_phys_patch = .; | |
80 | *(.tsb_ldquad_phys_patch) | |
81 | __tsb_ldquad_phys_patch_end = .; | |
82 | } | |
83 | ||
84 | .tsb_phys_patch : { | |
85 | __tsb_phys_patch = .; | |
86 | *(.tsb_phys_patch) | |
87 | __tsb_phys_patch_end = .; | |
88 | } | |
89 | ||
90 | .cpuid_patch : { | |
91 | __cpuid_patch = .; | |
92 | *(.cpuid_patch) | |
93 | __cpuid_patch_end = .; | |
94 | } | |
95 | ||
96 | .sun4v_1insn_patch : { | |
97 | __sun4v_1insn_patch = .; | |
98 | *(.sun4v_1insn_patch) | |
99 | __sun4v_1insn_patch_end = .; | |
100 | } | |
101 | .sun4v_2insn_patch : { | |
102 | __sun4v_2insn_patch = .; | |
103 | *(.sun4v_2insn_patch) | |
104 | __sun4v_2insn_patch_end = .; | |
105 | } | |
106 | ||
bcbe40eb | 107 | PERCPU(PAGE_SIZE) |
1b1fbbca | 108 | |
bcbe40eb SR |
109 | . = ALIGN(PAGE_SIZE); |
110 | __init_end = .; | |
3240a77b | 111 | BSS_SECTION(0, 0, 0) |
bcbe40eb | 112 | _end = . ; |
1b1fbbca | 113 | |
bcbe40eb SR |
114 | STABS_DEBUG |
115 | DWARF_DEBUG | |
023bf6f1 TH |
116 | |
117 | DISCARDS | |
1da177e4 | 118 | } |