[mirror_ubuntu-bionic-kernel.git] / arch / sparc / kernel / winfixup.S

/* winfixup.S: Handle cases where user stack pointer is found to be bogus.
 *
 * Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net)
 */

#include <asm/asi.h>
#include <asm/head.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include <asm/processor.h>
#include <asm/spitfire.h>
#include <asm/thread_info.h>

	.text

	/* It used to be the case that these register window fault
	 * handlers could run via the save and restore instructions
	 * done by the trap entry and exit code.  They now do the
	 * window spill/fill by hand, so that case no longer can occur.
	 */

	.align	32
fill_fixup:
	TRAP_LOAD_THREAD_REG(%g6, %g1)
	rdpr	%tstate, %g1
	and	%g1, TSTATE_CWP, %g1
	or	%g4, FAULT_CODE_WINFIXUP, %g4
	stb	%g4, [%g6 + TI_FAULT_CODE]
	stx	%g5, [%g6 + TI_FAULT_ADDR]
	wrpr	%g1, %cwp
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	call	do_sparc64_fault
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap

	/* Be very careful about usage of the trap globals here.
	 * You cannot touch %g5 as that has the fault information.
	 */
spill_fixup:
spill_fixup_mna:
spill_fixup_dax:
	TRAP_LOAD_THREAD_REG(%g6, %g1)
	ldx	[%g6 + TI_FLAGS], %g1
	andcc	%sp, 0x1, %g0
	movne	%icc, 0, %g1
	andcc	%g1, _TIF_32BIT, %g0
	ldub	[%g6 + TI_WSAVED], %g1
	sll	%g1, 3, %g3
	add	%g6, %g3, %g3
	stx	%sp, [%g3 + TI_RWIN_SPTRS]
	sll	%g1, 7, %g3
	bne,pt	%xcc, 1f
	 add	%g6, %g3, %g3
	stx	%l0, [%g3 + TI_REG_WINDOW + 0x00]
	stx	%l1, [%g3 + TI_REG_WINDOW + 0x08]
	stx	%l2, [%g3 + TI_REG_WINDOW + 0x10]
	stx	%l3, [%g3 + TI_REG_WINDOW + 0x18]
	stx	%l4, [%g3 + TI_REG_WINDOW + 0x20]
	stx	%l5, [%g3 + TI_REG_WINDOW + 0x28]
	stx	%l6, [%g3 + TI_REG_WINDOW + 0x30]
	stx	%l7, [%g3 + TI_REG_WINDOW + 0x38]
	stx	%i0, [%g3 + TI_REG_WINDOW + 0x40]
	stx	%i1, [%g3 + TI_REG_WINDOW + 0x48]
	stx	%i2, [%g3 + TI_REG_WINDOW + 0x50]
	stx	%i3, [%g3 + TI_REG_WINDOW + 0x58]
	stx	%i4, [%g3 + TI_REG_WINDOW + 0x60]
	stx	%i5, [%g3 + TI_REG_WINDOW + 0x68]
	stx	%i6, [%g3 + TI_REG_WINDOW + 0x70]
	ba,pt	%xcc, 2f
	 stx	%i7, [%g3 + TI_REG_WINDOW + 0x78]
1:	stw	%l0, [%g3 + TI_REG_WINDOW + 0x00]
	stw	%l1, [%g3 + TI_REG_WINDOW + 0x04]
	stw	%l2, [%g3 + TI_REG_WINDOW + 0x08]
	stw	%l3, [%g3 + TI_REG_WINDOW + 0x0c]
	stw	%l4, [%g3 + TI_REG_WINDOW + 0x10]
	stw	%l5, [%g3 + TI_REG_WINDOW + 0x14]
	stw	%l6, [%g3 + TI_REG_WINDOW + 0x18]
	stw	%l7, [%g3 + TI_REG_WINDOW + 0x1c]
	stw	%i0, [%g3 + TI_REG_WINDOW + 0x20]
	stw	%i1, [%g3 + TI_REG_WINDOW + 0x24]
	stw	%i2, [%g3 + TI_REG_WINDOW + 0x28]
	stw	%i3, [%g3 + TI_REG_WINDOW + 0x2c]
	stw	%i4, [%g3 + TI_REG_WINDOW + 0x30]
	stw	%i5, [%g3 + TI_REG_WINDOW + 0x34]
	stw	%i6, [%g3 + TI_REG_WINDOW + 0x38]
	stw	%i7, [%g3 + TI_REG_WINDOW + 0x3c]
2:	add	%g1, 1, %g1
	stb	%g1, [%g6 + TI_WSAVED]
	rdpr	%tstate, %g1
	andcc	%g1, TSTATE_PRIV, %g0
	saved
	be,pn	%xcc, 1f
	 and	%g1, TSTATE_CWP, %g1
	retry
1:	mov	FAULT_CODE_WRITE | FAULT_CODE_DTLB | FAULT_CODE_WINFIXUP, %g4
	stb	%g4, [%g6 + TI_FAULT_CODE]
	stx	%g5, [%g6 + TI_FAULT_ADDR]
	wrpr	%g1, %cwp
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	call	do_sparc64_fault
	 add	%sp, PTREGS_OFF, %o0
	ba,a,pt	%xcc, rtrap

winfix_mna:
	andn	%g3, 0x7f, %g3
	add	%g3, 0x78, %g3
	wrpr	%g3, %tnpc
	done

fill_fixup_mna:
	rdpr	%tstate, %g1
	and	%g1, TSTATE_CWP, %g1
	wrpr	%g1, %cwp
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	sethi	%hi(tlb_type), %g1
	lduw	[%g1 + %lo(tlb_type)], %g1
	cmp	%g1, 3
	bne,pt	%icc, 1f
	 add	%sp, PTREGS_OFF, %o0
	mov	%l4, %o2
	call	sun4v_do_mna
	 mov	%l5, %o1
	ba,a,pt	%xcc, rtrap
1:	mov	%l4, %o1
	mov	%l5, %o2
	call	mem_address_unaligned
	 nop
	ba,a,pt	%xcc, rtrap

winfix_dax:
	andn	%g3, 0x7f, %g3
	add	%g3, 0x74, %g3
	wrpr	%g3, %tnpc
	done

fill_fixup_dax:
	rdpr	%tstate, %g1
	and	%g1, TSTATE_CWP, %g1
	wrpr	%g1, %cwp
	ba,pt	%xcc, etrap
	 rd	%pc, %g7
	sethi	%hi(tlb_type), %g1
	mov	%l4, %o1
	lduw	[%g1 + %lo(tlb_type)], %g1
	mov	%l5, %o2
	cmp	%g1, 3
	bne,pt	%icc, 1f
	 add	%sp, PTREGS_OFF, %o0
	call	sun4v_data_access_exception
	 nop
	ba,a,pt	%xcc, rtrap
	 nop
1:	call	spitfire_data_access_exception
	 nop
	ba,a,pt	%xcc, rtrap
	 nop
Commit	Line	Data
314ef685	1	/* winfixup.S: Handle cases where user stack pointer is found to be bogus.
1da177e4	2	*
314ef685	3	* Copyright (C) 1997, 2006 David S. Miller (davem@davemloft.net)
1da177e4 LT	4	*/
	5
	6	#include <asm/asi.h>
	7	#include <asm/head.h>
	8	#include <asm/page.h>
	9	#include <asm/ptrace.h>
	10	#include <asm/processor.h>
	11	#include <asm/spitfire.h>
	12	#include <asm/thread_info.h>
	13
	14	.text
	15
314ef685 DM	16	/* It used to be the case that these register window fault
	17	* handlers could run via the save and restore instructions
	18	* done by the trap entry and exit code. They now do the
	19	* window spill/fill by hand, so that case no longer can occur.
	20	*/
1da177e4	21
1da177e4	22	.align 32
1da177e4	23	fill_fixup:
ffe483d5	24	TRAP_LOAD_THREAD_REG(%g6, %g1)
314ef685 DM	25	rdpr %tstate, %g1
	26	and %g1, TSTATE_CWP, %g1
	27	or %g4, FAULT_CODE_WINFIXUP, %g4
	28	stb %g4, [%g6 + TI_FAULT_CODE]
	29	stx %g5, [%g6 + TI_FAULT_ADDR]
	30	wrpr %g1, %cwp
	31	ba,pt %xcc, etrap
	32	rd %pc, %g7
	33	call do_sparc64_fault
	34	add %sp, PTREGS_OFF, %o0
49fa5230	35	ba,a,pt %xcc, rtrap
1da177e4	36
314ef685 DM	37	/* Be very careful about usage of the trap globals here.
314ef685 DM	38	* You cannot touch %g5 as that has the fault information.
1da177e4 LT	39	*/
1da177e4 LT	40	spill_fixup:
314ef685 DM	41	spill_fixup_mna:
314ef685 DM	42	spill_fixup_dax:
ffe483d5	43	TRAP_LOAD_THREAD_REG(%g6, %g1)
314ef685	44	ldx [%g6 + TI_FLAGS], %g1
517ffce4 DM	45	andcc %sp, 0x1, %g0
517ffce4 DM	46	movne %icc, 0, %g1
314ef685 DM	47	andcc %g1, _TIF_32BIT, %g0
	48	ldub [%g6 + TI_WSAVED], %g1
	49	sll %g1, 3, %g3
	50	add %g6, %g3, %g3
	51	stx %sp, [%g3 + TI_RWIN_SPTRS]
	52	sll %g1, 7, %g3
	53	bne,pt %xcc, 1f
	54	add %g6, %g3, %g3
	55	stx %l0, [%g3 + TI_REG_WINDOW + 0x00]
	56	stx %l1, [%g3 + TI_REG_WINDOW + 0x08]
	57	stx %l2, [%g3 + TI_REG_WINDOW + 0x10]
	58	stx %l3, [%g3 + TI_REG_WINDOW + 0x18]
	59	stx %l4, [%g3 + TI_REG_WINDOW + 0x20]
	60	stx %l5, [%g3 + TI_REG_WINDOW + 0x28]
	61	stx %l6, [%g3 + TI_REG_WINDOW + 0x30]
	62	stx %l7, [%g3 + TI_REG_WINDOW + 0x38]
	63	stx %i0, [%g3 + TI_REG_WINDOW + 0x40]
	64	stx %i1, [%g3 + TI_REG_WINDOW + 0x48]
	65	stx %i2, [%g3 + TI_REG_WINDOW + 0x50]
	66	stx %i3, [%g3 + TI_REG_WINDOW + 0x58]
	67	stx %i4, [%g3 + TI_REG_WINDOW + 0x60]
	68	stx %i5, [%g3 + TI_REG_WINDOW + 0x68]
	69	stx %i6, [%g3 + TI_REG_WINDOW + 0x70]
	70	ba,pt %xcc, 2f
	71	stx %i7, [%g3 + TI_REG_WINDOW + 0x78]
	72	1: stw %l0, [%g3 + TI_REG_WINDOW + 0x00]
	73	stw %l1, [%g3 + TI_REG_WINDOW + 0x04]
	74	stw %l2, [%g3 + TI_REG_WINDOW + 0x08]
	75	stw %l3, [%g3 + TI_REG_WINDOW + 0x0c]
	76	stw %l4, [%g3 + TI_REG_WINDOW + 0x10]
	77	stw %l5, [%g3 + TI_REG_WINDOW + 0x14]
	78	stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
	79	stw %l7, [%g3 + TI_REG_WINDOW + 0x1c]
	80	stw %i0, [%g3 + TI_REG_WINDOW + 0x20]
	81	stw %i1, [%g3 + TI_REG_WINDOW + 0x24]
	82	stw %i2, [%g3 + TI_REG_WINDOW + 0x28]
	83	stw %i3, [%g3 + TI_REG_WINDOW + 0x2c]
	84	stw %i4, [%g3 + TI_REG_WINDOW + 0x30]
	85	stw %i5, [%g3 + TI_REG_WINDOW + 0x34]
	86	stw %i6, [%g3 + TI_REG_WINDOW + 0x38]
	87	stw %i7, [%g3 + TI_REG_WINDOW + 0x3c]
	88	2: add %g1, 1, %g1
	89	stb %g1, [%g6 + TI_WSAVED]
	90	rdpr %tstate, %g1
	91	andcc %g1, TSTATE_PRIV, %g0
1da177e4	92	saved
314ef685 DM	93	be,pn %xcc, 1f
314ef685 DM	94	and %g1, TSTATE_CWP, %g1
1da177e4	95	retry
314ef685 DM	96	1: mov FAULT_CODE_WRITE \| FAULT_CODE_DTLB \| FAULT_CODE_WINFIXUP, %g4
	97	stb %g4, [%g6 + TI_FAULT_CODE]
	98	stx %g5, [%g6 + TI_FAULT_ADDR]
	99	wrpr %g1, %cwp
	100	ba,pt %xcc, etrap
	101	rd %pc, %g7
	102	call do_sparc64_fault
	103	add %sp, PTREGS_OFF, %o0
7697daaa	104	ba,a,pt %xcc, rtrap
1da177e4	105
1da177e4	106	winfix_mna:
314ef685 DM	107	andn %g3, 0x7f, %g3
	108	add %g3, 0x78, %g3
	109	wrpr %g3, %tnpc
1da177e4	110	done
1da177e4	111
314ef685	112	fill_fixup_mna:
314ef685 DM	113	rdpr %tstate, %g1
	114	and %g1, TSTATE_CWP, %g1
	115	wrpr %g1, %cwp
	116	ba,pt %xcc, etrap
	117	rd %pc, %g7
ed6b0b45	118	sethi %hi(tlb_type), %g1
ed6b0b45	119	lduw [%g1 + %lo(tlb_type)], %g1
ed6b0b45 DM	120	cmp %g1, 3
ed6b0b45 DM	121	bne,pt %icc, 1f
314ef685	122	add %sp, PTREGS_OFF, %o0
24c523ec	123	mov %l4, %o2
9b6b4647	124	call sun4v_do_mna
24c523ec	125	mov %l5, %o1
7697daaa	126	ba,a,pt %xcc, rtrap
24c523ec DM	127	1: mov %l4, %o1
	128	mov %l5, %o2
	129	call mem_address_unaligned
ed6b0b45	130	nop
7697daaa	131	ba,a,pt %xcc, rtrap
1da177e4	132
1da177e4	133	winfix_dax:
314ef685 DM	134	andn %g3, 0x7f, %g3
	135	add %g3, 0x74, %g3
	136	wrpr %g3, %tnpc
1da177e4	137	done
1da177e4	138
314ef685	139	fill_fixup_dax:
314ef685 DM	140	rdpr %tstate, %g1
	141	and %g1, TSTATE_CWP, %g1
	142	wrpr %g1, %cwp
	143	ba,pt %xcc, etrap
	144	rd %pc, %g7
ed6b0b45	145	sethi %hi(tlb_type), %g1
314ef685	146	mov %l4, %o1
ed6b0b45	147	lduw [%g1 + %lo(tlb_type)], %g1
314ef685	148	mov %l5, %o2
ed6b0b45 DM	149	cmp %g1, 3
ed6b0b45 DM	150	bne,pt %icc, 1f
314ef685	151	add %sp, PTREGS_OFF, %o0
ed6b0b45 DM	152	call sun4v_data_access_exception
ed6b0b45 DM	153	nop
7697daaa	154	ba,a,pt %xcc, rtrap
0ae2d26f	155	nop
ed6b0b45 DM	156	1: call spitfire_data_access_exception
ed6b0b45 DM	157	nop
7697daaa	158	ba,a,pt %xcc, rtrap
0ae2d26f	159	nop