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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
b00dc837 | 2 | /* |
1da177e4 LT |
3 | * arch/sparc64/mm/init.c |
4 | * | |
5 | * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu) | |
6 | * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
7 | */ | |
8 | ||
cdd4f4c7 | 9 | #include <linux/extable.h> |
1da177e4 LT |
10 | #include <linux/kernel.h> |
11 | #include <linux/sched.h> | |
12 | #include <linux/string.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/bootmem.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/hugetlb.h> | |
1da177e4 LT |
17 | #include <linux/initrd.h> |
18 | #include <linux/swap.h> | |
19 | #include <linux/pagemap.h> | |
c9cf5528 | 20 | #include <linux/poison.h> |
1da177e4 LT |
21 | #include <linux/fs.h> |
22 | #include <linux/seq_file.h> | |
05e14cb3 | 23 | #include <linux/kprobes.h> |
1ac4f5eb | 24 | #include <linux/cache.h> |
13edad7a | 25 | #include <linux/sort.h> |
f6d4fb5c | 26 | #include <linux/ioport.h> |
5cbc3073 | 27 | #include <linux/percpu.h> |
95f72d1e | 28 | #include <linux/memblock.h> |
919ee677 | 29 | #include <linux/mmzone.h> |
5a0e3ad6 | 30 | #include <linux/gfp.h> |
1da177e4 LT |
31 | |
32 | #include <asm/head.h> | |
1da177e4 LT |
33 | #include <asm/page.h> |
34 | #include <asm/pgalloc.h> | |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/oplib.h> | |
37 | #include <asm/iommu.h> | |
38 | #include <asm/io.h> | |
7c0f6ba6 | 39 | #include <linux/uaccess.h> |
1da177e4 LT |
40 | #include <asm/mmu_context.h> |
41 | #include <asm/tlbflush.h> | |
42 | #include <asm/dma.h> | |
43 | #include <asm/starfire.h> | |
44 | #include <asm/tlb.h> | |
45 | #include <asm/spitfire.h> | |
46 | #include <asm/sections.h> | |
517af332 | 47 | #include <asm/tsb.h> |
481295f9 | 48 | #include <asm/hypervisor.h> |
372b07bb | 49 | #include <asm/prom.h> |
5cbc3073 | 50 | #include <asm/mdesc.h> |
3d5ae6b6 | 51 | #include <asm/cpudata.h> |
59dec13b | 52 | #include <asm/setup.h> |
4f70f7a9 | 53 | #include <asm/irq.h> |
1da177e4 | 54 | |
27137e52 | 55 | #include "init_64.h" |
9cc3a1ac | 56 | |
4f93d21d | 57 | unsigned long kern_linear_pte_xor[4] __read_mostly; |
494e5b6f | 58 | static unsigned long page_cache4v_flag; |
9cc3a1ac | 59 | |
4f93d21d DM |
60 | /* A bitmap, two bits for every 256MB of physical memory. These two |
61 | * bits determine what page size we use for kernel linear | |
62 | * translations. They form an index into kern_linear_pte_xor[]. The | |
63 | * value in the indexed slot is XOR'd with the TLB miss virtual | |
64 | * address to form the resulting TTE. The mapping is: | |
65 | * | |
66 | * 0 ==> 4MB | |
67 | * 1 ==> 256MB | |
68 | * 2 ==> 2GB | |
69 | * 3 ==> 16GB | |
70 | * | |
71 | * All sun4v chips support 256MB pages. Only SPARC-T4 and later | |
72 | * support 2GB pages, and hopefully future cpus will support the 16GB | |
73 | * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there | |
74 | * if these larger page sizes are not supported by the cpu. | |
75 | * | |
76 | * It would be nice to determine this from the machine description | |
77 | * 'cpu' properties, but we need to have this table setup before the | |
78 | * MDESC is initialized. | |
9cc3a1ac | 79 | */ |
9cc3a1ac | 80 | |
d1acb421 | 81 | #ifndef CONFIG_DEBUG_PAGEALLOC |
4f93d21d DM |
82 | /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings. |
83 | * Space is allocated for this right after the trap table in | |
84 | * arch/sparc64/kernel/head.S | |
2d9e2763 DM |
85 | */ |
86 | extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES]; | |
d1acb421 | 87 | #endif |
0dd5b7b0 | 88 | extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES]; |
d7744a09 | 89 | |
ce33fdc5 DM |
90 | static unsigned long cpu_pgsz_mask; |
91 | ||
d195b71b | 92 | #define MAX_BANKS 1024 |
13edad7a | 93 | |
7c9503b8 GKH |
94 | static struct linux_prom64_registers pavail[MAX_BANKS]; |
95 | static int pavail_ents; | |
13edad7a | 96 | |
52708d69 NG |
97 | u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES]; |
98 | ||
13edad7a DM |
99 | static int cmp_p64(const void *a, const void *b) |
100 | { | |
101 | const struct linux_prom64_registers *x = a, *y = b; | |
102 | ||
103 | if (x->phys_addr > y->phys_addr) | |
104 | return 1; | |
105 | if (x->phys_addr < y->phys_addr) | |
106 | return -1; | |
107 | return 0; | |
108 | } | |
109 | ||
110 | static void __init read_obp_memory(const char *property, | |
111 | struct linux_prom64_registers *regs, | |
112 | int *num_ents) | |
113 | { | |
8d125562 | 114 | phandle node = prom_finddevice("/memory"); |
13edad7a DM |
115 | int prop_size = prom_getproplen(node, property); |
116 | int ents, ret, i; | |
117 | ||
118 | ents = prop_size / sizeof(struct linux_prom64_registers); | |
119 | if (ents > MAX_BANKS) { | |
120 | prom_printf("The machine has more %s property entries than " | |
121 | "this kernel can support (%d).\n", | |
122 | property, MAX_BANKS); | |
123 | prom_halt(); | |
124 | } | |
125 | ||
126 | ret = prom_getproperty(node, property, (char *) regs, prop_size); | |
127 | if (ret == -1) { | |
5da444aa AM |
128 | prom_printf("Couldn't get %s property from /memory.\n", |
129 | property); | |
13edad7a DM |
130 | prom_halt(); |
131 | } | |
132 | ||
13edad7a DM |
133 | /* Sanitize what we got from the firmware, by page aligning |
134 | * everything. | |
135 | */ | |
136 | for (i = 0; i < ents; i++) { | |
137 | unsigned long base, size; | |
138 | ||
139 | base = regs[i].phys_addr; | |
140 | size = regs[i].reg_size; | |
10147570 | 141 | |
13edad7a DM |
142 | size &= PAGE_MASK; |
143 | if (base & ~PAGE_MASK) { | |
144 | unsigned long new_base = PAGE_ALIGN(base); | |
145 | ||
146 | size -= new_base - base; | |
147 | if ((long) size < 0L) | |
148 | size = 0UL; | |
149 | base = new_base; | |
150 | } | |
0015d3d6 DM |
151 | if (size == 0UL) { |
152 | /* If it is empty, simply get rid of it. | |
153 | * This simplifies the logic of the other | |
154 | * functions that process these arrays. | |
155 | */ | |
156 | memmove(®s[i], ®s[i + 1], | |
157 | (ents - i - 1) * sizeof(regs[0])); | |
486ad10a | 158 | i--; |
0015d3d6 DM |
159 | ents--; |
160 | continue; | |
486ad10a | 161 | } |
0015d3d6 DM |
162 | regs[i].phys_addr = base; |
163 | regs[i].reg_size = size; | |
486ad10a DM |
164 | } |
165 | ||
166 | *num_ents = ents; | |
167 | ||
c9c10830 | 168 | sort(regs, ents, sizeof(struct linux_prom64_registers), |
13edad7a DM |
169 | cmp_p64, NULL); |
170 | } | |
1da177e4 | 171 | |
d1112018 | 172 | /* Kernel physical address base and size in bytes. */ |
1ac4f5eb DM |
173 | unsigned long kern_base __read_mostly; |
174 | unsigned long kern_size __read_mostly; | |
1da177e4 | 175 | |
1da177e4 LT |
176 | /* Initial ramdisk setup */ |
177 | extern unsigned long sparc_ramdisk_image64; | |
178 | extern unsigned int sparc_ramdisk_image; | |
179 | extern unsigned int sparc_ramdisk_size; | |
180 | ||
1ac4f5eb | 181 | struct page *mem_map_zero __read_mostly; |
35802c0b | 182 | EXPORT_SYMBOL(mem_map_zero); |
1da177e4 | 183 | |
0835ae0f DM |
184 | unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly; |
185 | ||
186 | unsigned long sparc64_kern_pri_context __read_mostly; | |
187 | unsigned long sparc64_kern_pri_nuc_bits __read_mostly; | |
188 | unsigned long sparc64_kern_sec_context __read_mostly; | |
189 | ||
64658743 | 190 | int num_kernel_image_mappings; |
1da177e4 | 191 | |
1da177e4 LT |
192 | #ifdef CONFIG_DEBUG_DCFLUSH |
193 | atomic_t dcpage_flushes = ATOMIC_INIT(0); | |
194 | #ifdef CONFIG_SMP | |
195 | atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0); | |
196 | #endif | |
197 | #endif | |
198 | ||
7a591cfe | 199 | inline void flush_dcache_page_impl(struct page *page) |
1da177e4 | 200 | { |
7a591cfe | 201 | BUG_ON(tlb_type == hypervisor); |
1da177e4 LT |
202 | #ifdef CONFIG_DEBUG_DCFLUSH |
203 | atomic_inc(&dcpage_flushes); | |
204 | #endif | |
205 | ||
206 | #ifdef DCACHE_ALIASING_POSSIBLE | |
207 | __flush_dcache_page(page_address(page), | |
208 | ((tlb_type == spitfire) && | |
209 | page_mapping(page) != NULL)); | |
210 | #else | |
211 | if (page_mapping(page) != NULL && | |
212 | tlb_type == spitfire) | |
213 | __flush_icache_page(__pa(page_address(page))); | |
214 | #endif | |
215 | } | |
216 | ||
217 | #define PG_dcache_dirty PG_arch_1 | |
22adb358 DM |
218 | #define PG_dcache_cpu_shift 32UL |
219 | #define PG_dcache_cpu_mask \ | |
220 | ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL) | |
1da177e4 LT |
221 | |
222 | #define dcache_dirty_cpu(page) \ | |
48b0e548 | 223 | (((page)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask) |
1da177e4 | 224 | |
d979f179 | 225 | static inline void set_dcache_dirty(struct page *page, int this_cpu) |
1da177e4 LT |
226 | { |
227 | unsigned long mask = this_cpu; | |
48b0e548 DM |
228 | unsigned long non_cpu_bits; |
229 | ||
230 | non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift); | |
231 | mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty); | |
232 | ||
1da177e4 LT |
233 | __asm__ __volatile__("1:\n\t" |
234 | "ldx [%2], %%g7\n\t" | |
235 | "and %%g7, %1, %%g1\n\t" | |
236 | "or %%g1, %0, %%g1\n\t" | |
237 | "casx [%2], %%g7, %%g1\n\t" | |
238 | "cmp %%g7, %%g1\n\t" | |
239 | "bne,pn %%xcc, 1b\n\t" | |
b445e26c | 240 | " nop" |
1da177e4 LT |
241 | : /* no outputs */ |
242 | : "r" (mask), "r" (non_cpu_bits), "r" (&page->flags) | |
243 | : "g1", "g7"); | |
244 | } | |
245 | ||
d979f179 | 246 | static inline void clear_dcache_dirty_cpu(struct page *page, unsigned long cpu) |
1da177e4 LT |
247 | { |
248 | unsigned long mask = (1UL << PG_dcache_dirty); | |
249 | ||
250 | __asm__ __volatile__("! test_and_clear_dcache_dirty\n" | |
251 | "1:\n\t" | |
252 | "ldx [%2], %%g7\n\t" | |
48b0e548 | 253 | "srlx %%g7, %4, %%g1\n\t" |
1da177e4 LT |
254 | "and %%g1, %3, %%g1\n\t" |
255 | "cmp %%g1, %0\n\t" | |
256 | "bne,pn %%icc, 2f\n\t" | |
257 | " andn %%g7, %1, %%g1\n\t" | |
258 | "casx [%2], %%g7, %%g1\n\t" | |
259 | "cmp %%g7, %%g1\n\t" | |
260 | "bne,pn %%xcc, 1b\n\t" | |
b445e26c | 261 | " nop\n" |
1da177e4 LT |
262 | "2:" |
263 | : /* no outputs */ | |
264 | : "r" (cpu), "r" (mask), "r" (&page->flags), | |
48b0e548 DM |
265 | "i" (PG_dcache_cpu_mask), |
266 | "i" (PG_dcache_cpu_shift) | |
1da177e4 LT |
267 | : "g1", "g7"); |
268 | } | |
269 | ||
517af332 DM |
270 | static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte) |
271 | { | |
272 | unsigned long tsb_addr = (unsigned long) ent; | |
273 | ||
3b3ab2eb | 274 | if (tlb_type == cheetah_plus || tlb_type == hypervisor) |
517af332 DM |
275 | tsb_addr = __pa(tsb_addr); |
276 | ||
277 | __tsb_insert(tsb_addr, tag, pte); | |
278 | } | |
279 | ||
c4bce90e | 280 | unsigned long _PAGE_ALL_SZ_BITS __read_mostly; |
c4bce90e | 281 | |
ff9aefbf | 282 | static void flush_dcache(unsigned long pfn) |
1da177e4 | 283 | { |
ff9aefbf | 284 | struct page *page; |
7a591cfe | 285 | |
ff9aefbf | 286 | page = pfn_to_page(pfn); |
1a78cedb | 287 | if (page) { |
7a591cfe | 288 | unsigned long pg_flags; |
7a591cfe | 289 | |
ff9aefbf SR |
290 | pg_flags = page->flags; |
291 | if (pg_flags & (1UL << PG_dcache_dirty)) { | |
7a591cfe DM |
292 | int cpu = ((pg_flags >> PG_dcache_cpu_shift) & |
293 | PG_dcache_cpu_mask); | |
294 | int this_cpu = get_cpu(); | |
295 | ||
296 | /* This is just to optimize away some function calls | |
297 | * in the SMP case. | |
298 | */ | |
299 | if (cpu == this_cpu) | |
300 | flush_dcache_page_impl(page); | |
301 | else | |
302 | smp_flush_dcache_page_impl(page, cpu); | |
303 | ||
304 | clear_dcache_dirty_cpu(page, cpu); | |
305 | ||
306 | put_cpu(); | |
307 | } | |
1da177e4 | 308 | } |
ff9aefbf SR |
309 | } |
310 | ||
9e695d2e DM |
311 | /* mm->context.lock must be held */ |
312 | static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index, | |
313 | unsigned long tsb_hash_shift, unsigned long address, | |
314 | unsigned long tte) | |
315 | { | |
316 | struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb; | |
317 | unsigned long tag; | |
318 | ||
bcd896ba DM |
319 | if (unlikely(!tsb)) |
320 | return; | |
321 | ||
9e695d2e DM |
322 | tsb += ((address >> tsb_hash_shift) & |
323 | (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL)); | |
324 | tag = (address >> 22UL); | |
325 | tsb_insert(tsb, tag, tte); | |
326 | } | |
327 | ||
c7d9f77d | 328 | #ifdef CONFIG_HUGETLB_PAGE |
8399e4b8 NG |
329 | static void __init add_huge_page_size(unsigned long size) |
330 | { | |
331 | unsigned int order; | |
332 | ||
333 | if (size_to_hstate(size)) | |
334 | return; | |
335 | ||
336 | order = ilog2(size) - PAGE_SHIFT; | |
337 | hugetlb_add_hstate(order); | |
338 | } | |
339 | ||
340 | static int __init hugetlbpage_init(void) | |
341 | { | |
342 | add_huge_page_size(1UL << HPAGE_64K_SHIFT); | |
343 | add_huge_page_size(1UL << HPAGE_SHIFT); | |
344 | add_huge_page_size(1UL << HPAGE_256MB_SHIFT); | |
345 | add_huge_page_size(1UL << HPAGE_2GB_SHIFT); | |
346 | ||
347 | return 0; | |
348 | } | |
349 | ||
350 | arch_initcall(hugetlbpage_init); | |
351 | ||
df7b2155 NG |
352 | static void __init pud_huge_patch(void) |
353 | { | |
354 | struct pud_huge_patch_entry *p; | |
355 | unsigned long addr; | |
356 | ||
357 | p = &__pud_huge_patch; | |
358 | addr = p->addr; | |
359 | *(unsigned int *)addr = p->insn; | |
360 | ||
361 | __asm__ __volatile__("flush %0" : : "r" (addr)); | |
362 | } | |
363 | ||
c7d9f77d NG |
364 | static int __init setup_hugepagesz(char *string) |
365 | { | |
366 | unsigned long long hugepage_size; | |
367 | unsigned int hugepage_shift; | |
368 | unsigned short hv_pgsz_idx; | |
369 | unsigned int hv_pgsz_mask; | |
370 | int rc = 0; | |
371 | ||
372 | hugepage_size = memparse(string, &string); | |
373 | hugepage_shift = ilog2(hugepage_size); | |
374 | ||
375 | switch (hugepage_shift) { | |
df7b2155 NG |
376 | case HPAGE_16GB_SHIFT: |
377 | hv_pgsz_mask = HV_PGSZ_MASK_16GB; | |
378 | hv_pgsz_idx = HV_PGSZ_IDX_16GB; | |
379 | pud_huge_patch(); | |
380 | break; | |
85b1da7c NG |
381 | case HPAGE_2GB_SHIFT: |
382 | hv_pgsz_mask = HV_PGSZ_MASK_2GB; | |
383 | hv_pgsz_idx = HV_PGSZ_IDX_2GB; | |
384 | break; | |
c7d9f77d NG |
385 | case HPAGE_256MB_SHIFT: |
386 | hv_pgsz_mask = HV_PGSZ_MASK_256MB; | |
387 | hv_pgsz_idx = HV_PGSZ_IDX_256MB; | |
388 | break; | |
389 | case HPAGE_SHIFT: | |
390 | hv_pgsz_mask = HV_PGSZ_MASK_4MB; | |
391 | hv_pgsz_idx = HV_PGSZ_IDX_4MB; | |
392 | break; | |
dcd1912d NG |
393 | case HPAGE_64K_SHIFT: |
394 | hv_pgsz_mask = HV_PGSZ_MASK_64K; | |
395 | hv_pgsz_idx = HV_PGSZ_IDX_64K; | |
396 | break; | |
c7d9f77d NG |
397 | default: |
398 | hv_pgsz_mask = 0; | |
399 | } | |
400 | ||
401 | if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U) { | |
f322980b LH |
402 | hugetlb_bad_size(); |
403 | pr_err("hugepagesz=%llu not supported by MMU.\n", | |
c7d9f77d NG |
404 | hugepage_size); |
405 | goto out; | |
406 | } | |
407 | ||
8399e4b8 | 408 | add_huge_page_size(hugepage_size); |
c7d9f77d NG |
409 | rc = 1; |
410 | ||
411 | out: | |
412 | return rc; | |
413 | } | |
414 | __setup("hugepagesz=", setup_hugepagesz); | |
415 | #endif /* CONFIG_HUGETLB_PAGE */ | |
416 | ||
4b3073e1 | 417 | void update_mmu_cache(struct vm_area_struct *vma, unsigned long address, pte_t *ptep) |
ff9aefbf SR |
418 | { |
419 | struct mm_struct *mm; | |
bcd896ba | 420 | unsigned long flags; |
df7b2155 | 421 | bool is_huge_tsb; |
4b3073e1 | 422 | pte_t pte = *ptep; |
ff9aefbf SR |
423 | |
424 | if (tlb_type != hypervisor) { | |
425 | unsigned long pfn = pte_pfn(pte); | |
426 | ||
427 | if (pfn_valid(pfn)) | |
428 | flush_dcache(pfn); | |
429 | } | |
bd40791e DM |
430 | |
431 | mm = vma->vm_mm; | |
7a1ac526 | 432 | |
18f38132 DM |
433 | /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */ |
434 | if (!pte_accessible(mm, pte)) | |
435 | return; | |
436 | ||
7a1ac526 DM |
437 | spin_lock_irqsave(&mm->context.lock, flags); |
438 | ||
df7b2155 | 439 | is_huge_tsb = false; |
9e695d2e | 440 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) |
df7b2155 NG |
441 | if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) { |
442 | unsigned long hugepage_size = PAGE_SIZE; | |
443 | ||
444 | if (is_vm_hugetlb_page(vma)) | |
445 | hugepage_size = huge_page_size(hstate_vma(vma)); | |
446 | ||
447 | if (hugepage_size >= PUD_SIZE) { | |
448 | unsigned long mask = 0x1ffc00000UL; | |
449 | ||
450 | /* Transfer bits [32:22] from address to resolve | |
451 | * at 4M granularity. | |
452 | */ | |
453 | pte_val(pte) &= ~mask; | |
454 | pte_val(pte) |= (address & mask); | |
455 | } else if (hugepage_size >= PMD_SIZE) { | |
456 | /* We are fabricating 8MB pages using 4MB | |
457 | * real hw pages. | |
458 | */ | |
459 | pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT)); | |
460 | } | |
461 | ||
462 | if (hugepage_size >= PMD_SIZE) { | |
463 | __update_mmu_tsb_insert(mm, MM_TSB_HUGE, | |
464 | REAL_HPAGE_SHIFT, address, pte_val(pte)); | |
465 | is_huge_tsb = true; | |
466 | } | |
467 | } | |
dcc1e8dd | 468 | #endif |
df7b2155 | 469 | if (!is_huge_tsb) |
bcd896ba DM |
470 | __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT, |
471 | address, pte_val(pte)); | |
7a1ac526 DM |
472 | |
473 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
1da177e4 LT |
474 | } |
475 | ||
476 | void flush_dcache_page(struct page *page) | |
477 | { | |
a9546f59 DM |
478 | struct address_space *mapping; |
479 | int this_cpu; | |
1da177e4 | 480 | |
7a591cfe DM |
481 | if (tlb_type == hypervisor) |
482 | return; | |
483 | ||
a9546f59 DM |
484 | /* Do not bother with the expensive D-cache flush if it |
485 | * is merely the zero page. The 'bigcore' testcase in GDB | |
486 | * causes this case to run millions of times. | |
487 | */ | |
488 | if (page == ZERO_PAGE(0)) | |
489 | return; | |
490 | ||
491 | this_cpu = get_cpu(); | |
492 | ||
493 | mapping = page_mapping(page); | |
1da177e4 | 494 | if (mapping && !mapping_mapped(mapping)) { |
a9546f59 | 495 | int dirty = test_bit(PG_dcache_dirty, &page->flags); |
1da177e4 | 496 | if (dirty) { |
a9546f59 DM |
497 | int dirty_cpu = dcache_dirty_cpu(page); |
498 | ||
1da177e4 LT |
499 | if (dirty_cpu == this_cpu) |
500 | goto out; | |
501 | smp_flush_dcache_page_impl(page, dirty_cpu); | |
502 | } | |
503 | set_dcache_dirty(page, this_cpu); | |
504 | } else { | |
505 | /* We could delay the flush for the !page_mapping | |
506 | * case too. But that case is for exec env/arg | |
507 | * pages and those are %99 certainly going to get | |
508 | * faulted into the tlb (and thus flushed) anyways. | |
509 | */ | |
510 | flush_dcache_page_impl(page); | |
511 | } | |
512 | ||
513 | out: | |
514 | put_cpu(); | |
515 | } | |
917c3660 | 516 | EXPORT_SYMBOL(flush_dcache_page); |
1da177e4 | 517 | |
05e14cb3 | 518 | void __kprobes flush_icache_range(unsigned long start, unsigned long end) |
1da177e4 | 519 | { |
a43fe0e7 | 520 | /* Cheetah and Hypervisor platform cpus have coherent I-cache. */ |
1da177e4 LT |
521 | if (tlb_type == spitfire) { |
522 | unsigned long kaddr; | |
523 | ||
a94aa253 DM |
524 | /* This code only runs on Spitfire cpus so this is |
525 | * why we can assume _PAGE_PADDR_4U. | |
526 | */ | |
527 | for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) { | |
528 | unsigned long paddr, mask = _PAGE_PADDR_4U; | |
529 | ||
530 | if (kaddr >= PAGE_OFFSET) | |
531 | paddr = kaddr & mask; | |
532 | else { | |
533 | pgd_t *pgdp = pgd_offset_k(kaddr); | |
534 | pud_t *pudp = pud_offset(pgdp, kaddr); | |
535 | pmd_t *pmdp = pmd_offset(pudp, kaddr); | |
536 | pte_t *ptep = pte_offset_kernel(pmdp, kaddr); | |
537 | ||
538 | paddr = pte_val(*ptep) & mask; | |
539 | } | |
540 | __flush_icache_page(paddr); | |
541 | } | |
1da177e4 LT |
542 | } |
543 | } | |
917c3660 | 544 | EXPORT_SYMBOL(flush_icache_range); |
1da177e4 | 545 | |
1da177e4 LT |
546 | void mmu_info(struct seq_file *m) |
547 | { | |
ce33fdc5 DM |
548 | static const char *pgsz_strings[] = { |
549 | "8K", "64K", "512K", "4MB", "32MB", | |
550 | "256MB", "2GB", "16GB", | |
551 | }; | |
552 | int i, printed; | |
553 | ||
1da177e4 LT |
554 | if (tlb_type == cheetah) |
555 | seq_printf(m, "MMU Type\t: Cheetah\n"); | |
556 | else if (tlb_type == cheetah_plus) | |
557 | seq_printf(m, "MMU Type\t: Cheetah+\n"); | |
558 | else if (tlb_type == spitfire) | |
559 | seq_printf(m, "MMU Type\t: Spitfire\n"); | |
a43fe0e7 DM |
560 | else if (tlb_type == hypervisor) |
561 | seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n"); | |
1da177e4 LT |
562 | else |
563 | seq_printf(m, "MMU Type\t: ???\n"); | |
564 | ||
ce33fdc5 DM |
565 | seq_printf(m, "MMU PGSZs\t: "); |
566 | printed = 0; | |
567 | for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) { | |
568 | if (cpu_pgsz_mask & (1UL << i)) { | |
569 | seq_printf(m, "%s%s", | |
570 | printed ? "," : "", pgsz_strings[i]); | |
571 | printed++; | |
572 | } | |
573 | } | |
574 | seq_putc(m, '\n'); | |
575 | ||
1da177e4 LT |
576 | #ifdef CONFIG_DEBUG_DCFLUSH |
577 | seq_printf(m, "DCPageFlushes\t: %d\n", | |
578 | atomic_read(&dcpage_flushes)); | |
579 | #ifdef CONFIG_SMP | |
580 | seq_printf(m, "DCPageFlushesXC\t: %d\n", | |
581 | atomic_read(&dcpage_flushes_xcall)); | |
582 | #endif /* CONFIG_SMP */ | |
583 | #endif /* CONFIG_DEBUG_DCFLUSH */ | |
584 | } | |
585 | ||
a94aa253 DM |
586 | struct linux_prom_translation prom_trans[512] __read_mostly; |
587 | unsigned int prom_trans_ents __read_mostly; | |
588 | ||
1da177e4 LT |
589 | unsigned long kern_locked_tte_data; |
590 | ||
c9c10830 DM |
591 | /* The obp translations are saved based on 8k pagesize, since obp can |
592 | * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS -> | |
74bf4312 | 593 | * HI_OBP_ADDRESS range are handled in ktlb.S. |
c9c10830 | 594 | */ |
5085b4a5 DM |
595 | static inline int in_obp_range(unsigned long vaddr) |
596 | { | |
597 | return (vaddr >= LOW_OBP_ADDRESS && | |
598 | vaddr < HI_OBP_ADDRESS); | |
599 | } | |
600 | ||
c9c10830 | 601 | static int cmp_ptrans(const void *a, const void *b) |
405599bd | 602 | { |
c9c10830 | 603 | const struct linux_prom_translation *x = a, *y = b; |
405599bd | 604 | |
c9c10830 DM |
605 | if (x->virt > y->virt) |
606 | return 1; | |
607 | if (x->virt < y->virt) | |
608 | return -1; | |
609 | return 0; | |
405599bd DM |
610 | } |
611 | ||
c9c10830 | 612 | /* Read OBP translations property into 'prom_trans[]'. */ |
9ad98c5b | 613 | static void __init read_obp_translations(void) |
405599bd | 614 | { |
c9c10830 | 615 | int n, node, ents, first, last, i; |
1da177e4 LT |
616 | |
617 | node = prom_finddevice("/virtual-memory"); | |
618 | n = prom_getproplen(node, "translations"); | |
405599bd | 619 | if (unlikely(n == 0 || n == -1)) { |
b206fc4c | 620 | prom_printf("prom_mappings: Couldn't get size.\n"); |
1da177e4 LT |
621 | prom_halt(); |
622 | } | |
405599bd | 623 | if (unlikely(n > sizeof(prom_trans))) { |
5da444aa | 624 | prom_printf("prom_mappings: Size %d is too big.\n", n); |
1da177e4 LT |
625 | prom_halt(); |
626 | } | |
405599bd | 627 | |
b206fc4c | 628 | if ((n = prom_getproperty(node, "translations", |
405599bd DM |
629 | (char *)&prom_trans[0], |
630 | sizeof(prom_trans))) == -1) { | |
b206fc4c | 631 | prom_printf("prom_mappings: Couldn't get property.\n"); |
1da177e4 LT |
632 | prom_halt(); |
633 | } | |
9ad98c5b | 634 | |
b206fc4c | 635 | n = n / sizeof(struct linux_prom_translation); |
9ad98c5b | 636 | |
c9c10830 DM |
637 | ents = n; |
638 | ||
639 | sort(prom_trans, ents, sizeof(struct linux_prom_translation), | |
640 | cmp_ptrans, NULL); | |
641 | ||
642 | /* Now kick out all the non-OBP entries. */ | |
643 | for (i = 0; i < ents; i++) { | |
644 | if (in_obp_range(prom_trans[i].virt)) | |
645 | break; | |
646 | } | |
647 | first = i; | |
648 | for (; i < ents; i++) { | |
649 | if (!in_obp_range(prom_trans[i].virt)) | |
650 | break; | |
651 | } | |
652 | last = i; | |
653 | ||
654 | for (i = 0; i < (last - first); i++) { | |
655 | struct linux_prom_translation *src = &prom_trans[i + first]; | |
656 | struct linux_prom_translation *dest = &prom_trans[i]; | |
657 | ||
658 | *dest = *src; | |
659 | } | |
660 | for (; i < ents; i++) { | |
661 | struct linux_prom_translation *dest = &prom_trans[i]; | |
662 | dest->virt = dest->size = dest->data = 0x0UL; | |
663 | } | |
664 | ||
665 | prom_trans_ents = last - first; | |
666 | ||
667 | if (tlb_type == spitfire) { | |
668 | /* Clear diag TTE bits. */ | |
669 | for (i = 0; i < prom_trans_ents; i++) | |
670 | prom_trans[i].data &= ~0x0003fe0000000000UL; | |
671 | } | |
f4142cba DM |
672 | |
673 | /* Force execute bit on. */ | |
674 | for (i = 0; i < prom_trans_ents; i++) | |
675 | prom_trans[i].data |= (tlb_type == hypervisor ? | |
676 | _PAGE_EXEC_4V : _PAGE_EXEC_4U); | |
405599bd | 677 | } |
1da177e4 | 678 | |
d82ace7d DM |
679 | static void __init hypervisor_tlb_lock(unsigned long vaddr, |
680 | unsigned long pte, | |
681 | unsigned long mmu) | |
682 | { | |
7db35f31 DM |
683 | unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu); |
684 | ||
685 | if (ret != 0) { | |
5da444aa | 686 | prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: " |
7db35f31 | 687 | "errors with %lx\n", vaddr, 0, pte, mmu, ret); |
12e126ad DM |
688 | prom_halt(); |
689 | } | |
d82ace7d DM |
690 | } |
691 | ||
c4bce90e DM |
692 | static unsigned long kern_large_tte(unsigned long paddr); |
693 | ||
898cf0ec | 694 | static void __init remap_kernel(void) |
405599bd DM |
695 | { |
696 | unsigned long phys_page, tte_vaddr, tte_data; | |
64658743 | 697 | int i, tlb_ent = sparc64_highest_locked_tlbent(); |
405599bd | 698 | |
1da177e4 | 699 | tte_vaddr = (unsigned long) KERNBASE; |
0eef331a | 700 | phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; |
c4bce90e | 701 | tte_data = kern_large_tte(phys_page); |
1da177e4 LT |
702 | |
703 | kern_locked_tte_data = tte_data; | |
704 | ||
d82ace7d DM |
705 | /* Now lock us into the TLBs via Hypervisor or OBP. */ |
706 | if (tlb_type == hypervisor) { | |
64658743 | 707 | for (i = 0; i < num_kernel_image_mappings; i++) { |
d82ace7d DM |
708 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU); |
709 | hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU); | |
64658743 DM |
710 | tte_vaddr += 0x400000; |
711 | tte_data += 0x400000; | |
d82ace7d DM |
712 | } |
713 | } else { | |
64658743 DM |
714 | for (i = 0; i < num_kernel_image_mappings; i++) { |
715 | prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
716 | prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr); | |
717 | tte_vaddr += 0x400000; | |
718 | tte_data += 0x400000; | |
d82ace7d | 719 | } |
64658743 | 720 | sparc64_highest_unlocked_tlb_ent = tlb_ent - i; |
1da177e4 | 721 | } |
0835ae0f DM |
722 | if (tlb_type == cheetah_plus) { |
723 | sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 | | |
724 | CTX_CHEETAH_PLUS_NUC); | |
725 | sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC; | |
726 | sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0; | |
727 | } | |
405599bd | 728 | } |
1da177e4 | 729 | |
405599bd | 730 | |
c9c10830 | 731 | static void __init inherit_prom_mappings(void) |
9ad98c5b | 732 | { |
405599bd | 733 | /* Now fixup OBP's idea about where we really are mapped. */ |
3c62a2d3 | 734 | printk("Remapping the kernel... "); |
405599bd | 735 | remap_kernel(); |
3c62a2d3 | 736 | printk("done.\n"); |
1da177e4 LT |
737 | } |
738 | ||
1da177e4 LT |
739 | void prom_world(int enter) |
740 | { | |
1da177e4 | 741 | if (!enter) |
dff933da | 742 | set_fs(get_fs()); |
1da177e4 | 743 | |
3487d1d4 | 744 | __asm__ __volatile__("flushw"); |
1da177e4 LT |
745 | } |
746 | ||
1da177e4 LT |
747 | void __flush_dcache_range(unsigned long start, unsigned long end) |
748 | { | |
749 | unsigned long va; | |
750 | ||
751 | if (tlb_type == spitfire) { | |
752 | int n = 0; | |
753 | ||
754 | for (va = start; va < end; va += 32) { | |
755 | spitfire_put_dcache_tag(va & 0x3fe0, 0x0); | |
756 | if (++n >= 512) | |
757 | break; | |
758 | } | |
a43fe0e7 | 759 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
760 | start = __pa(start); |
761 | end = __pa(end); | |
762 | for (va = start; va < end; va += 32) | |
763 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
764 | "membar #Sync" | |
765 | : /* no outputs */ | |
766 | : "r" (va), | |
767 | "i" (ASI_DCACHE_INVALIDATE)); | |
768 | } | |
769 | } | |
917c3660 | 770 | EXPORT_SYMBOL(__flush_dcache_range); |
1da177e4 | 771 | |
85f1e1f6 DM |
772 | /* get_new_mmu_context() uses "cache + 1". */ |
773 | DEFINE_SPINLOCK(ctx_alloc_lock); | |
c4415235 | 774 | unsigned long tlb_context_cache = CTX_FIRST_VERSION; |
85f1e1f6 DM |
775 | #define MAX_CTX_NR (1UL << CTX_NR_BITS) |
776 | #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR) | |
777 | DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR); | |
7a5b4bbf | 778 | DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0}; |
85f1e1f6 | 779 | |
a0582f26 PT |
780 | static void mmu_context_wrap(void) |
781 | { | |
782 | unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK; | |
783 | unsigned long new_ver, new_ctx, old_ctx; | |
784 | struct mm_struct *mm; | |
785 | int cpu; | |
786 | ||
787 | bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS); | |
788 | ||
789 | /* Reserve kernel context */ | |
790 | set_bit(0, mmu_context_bmap); | |
791 | ||
792 | new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION; | |
793 | if (unlikely(new_ver == 0)) | |
794 | new_ver = CTX_FIRST_VERSION; | |
795 | tlb_context_cache = new_ver; | |
796 | ||
797 | /* | |
798 | * Make sure that any new mm that are added into per_cpu_secondary_mm, | |
799 | * are going to go through get_new_mmu_context() path. | |
800 | */ | |
801 | mb(); | |
802 | ||
803 | /* | |
804 | * Updated versions to current on those CPUs that had valid secondary | |
805 | * contexts | |
806 | */ | |
807 | for_each_online_cpu(cpu) { | |
808 | /* | |
809 | * If a new mm is stored after we took this mm from the array, | |
810 | * it will go into get_new_mmu_context() path, because we | |
811 | * already bumped the version in tlb_context_cache. | |
812 | */ | |
813 | mm = per_cpu(per_cpu_secondary_mm, cpu); | |
814 | ||
815 | if (unlikely(!mm || mm == &init_mm)) | |
816 | continue; | |
817 | ||
818 | old_ctx = mm->context.sparc64_ctx_val; | |
819 | if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) { | |
820 | new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver; | |
821 | set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap); | |
822 | mm->context.sparc64_ctx_val = new_ctx; | |
823 | } | |
824 | } | |
825 | } | |
826 | ||
1da177e4 LT |
827 | /* Caller does TLB context flushing on local CPU if necessary. |
828 | * The caller also ensures that CTX_VALID(mm->context) is false. | |
829 | * | |
830 | * We must be careful about boundary cases so that we never | |
831 | * let the user have CTX 0 (nucleus) or we ever use a CTX | |
832 | * version of zero (and thus NO_CONTEXT would not be caught | |
833 | * by version mis-match tests in mmu_context.h). | |
a0663a79 DM |
834 | * |
835 | * Always invoked with interrupts disabled. | |
1da177e4 LT |
836 | */ |
837 | void get_new_mmu_context(struct mm_struct *mm) | |
838 | { | |
839 | unsigned long ctx, new_ctx; | |
840 | unsigned long orig_pgsz_bits; | |
1da177e4 | 841 | |
07df8418 | 842 | spin_lock(&ctx_alloc_lock); |
a0582f26 PT |
843 | retry: |
844 | /* wrap might have happened, test again if our context became valid */ | |
845 | if (unlikely(CTX_VALID(mm->context))) | |
846 | goto out; | |
1da177e4 LT |
847 | orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK); |
848 | ctx = (tlb_context_cache + 1) & CTX_NR_MASK; | |
849 | new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx); | |
850 | if (new_ctx >= (1 << CTX_NR_BITS)) { | |
851 | new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1); | |
852 | if (new_ctx >= ctx) { | |
a0582f26 PT |
853 | mmu_context_wrap(); |
854 | goto retry; | |
1da177e4 LT |
855 | } |
856 | } | |
58897485 PT |
857 | if (mm->context.sparc64_ctx_val) |
858 | cpumask_clear(mm_cpumask(mm)); | |
1da177e4 LT |
859 | mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63)); |
860 | new_ctx |= (tlb_context_cache & CTX_VERSION_MASK); | |
1da177e4 LT |
861 | tlb_context_cache = new_ctx; |
862 | mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits; | |
a0582f26 | 863 | out: |
07df8418 | 864 | spin_unlock(&ctx_alloc_lock); |
1da177e4 LT |
865 | } |
866 | ||
919ee677 DM |
867 | static int numa_enabled = 1; |
868 | static int numa_debug; | |
869 | ||
870 | static int __init early_numa(char *p) | |
1da177e4 | 871 | { |
919ee677 DM |
872 | if (!p) |
873 | return 0; | |
874 | ||
875 | if (strstr(p, "off")) | |
876 | numa_enabled = 0; | |
d1112018 | 877 | |
919ee677 DM |
878 | if (strstr(p, "debug")) |
879 | numa_debug = 1; | |
d1112018 | 880 | |
919ee677 | 881 | return 0; |
d1112018 | 882 | } |
919ee677 DM |
883 | early_param("numa", early_numa); |
884 | ||
885 | #define numadbg(f, a...) \ | |
886 | do { if (numa_debug) \ | |
887 | printk(KERN_INFO f, ## a); \ | |
888 | } while (0) | |
d1112018 | 889 | |
4e82c9a6 DM |
890 | static void __init find_ramdisk(unsigned long phys_base) |
891 | { | |
892 | #ifdef CONFIG_BLK_DEV_INITRD | |
893 | if (sparc_ramdisk_image || sparc_ramdisk_image64) { | |
894 | unsigned long ramdisk_image; | |
895 | ||
896 | /* Older versions of the bootloader only supported a | |
897 | * 32-bit physical address for the ramdisk image | |
898 | * location, stored at sparc_ramdisk_image. Newer | |
899 | * SILO versions set sparc_ramdisk_image to zero and | |
900 | * provide a full 64-bit physical address at | |
901 | * sparc_ramdisk_image64. | |
902 | */ | |
903 | ramdisk_image = sparc_ramdisk_image; | |
904 | if (!ramdisk_image) | |
905 | ramdisk_image = sparc_ramdisk_image64; | |
906 | ||
907 | /* Another bootloader quirk. The bootloader normalizes | |
908 | * the physical address to KERNBASE, so we have to | |
909 | * factor that back out and add in the lowest valid | |
910 | * physical page address to get the true physical address. | |
911 | */ | |
912 | ramdisk_image -= KERNBASE; | |
913 | ramdisk_image += phys_base; | |
914 | ||
919ee677 DM |
915 | numadbg("Found ramdisk at physical address 0x%lx, size %u\n", |
916 | ramdisk_image, sparc_ramdisk_size); | |
917 | ||
4e82c9a6 DM |
918 | initrd_start = ramdisk_image; |
919 | initrd_end = ramdisk_image + sparc_ramdisk_size; | |
3b2a7e23 | 920 | |
95f72d1e | 921 | memblock_reserve(initrd_start, sparc_ramdisk_size); |
d45100f7 DM |
922 | |
923 | initrd_start += PAGE_OFFSET; | |
924 | initrd_end += PAGE_OFFSET; | |
4e82c9a6 DM |
925 | } |
926 | #endif | |
927 | } | |
928 | ||
919ee677 DM |
929 | struct node_mem_mask { |
930 | unsigned long mask; | |
1537b26d | 931 | unsigned long match; |
919ee677 DM |
932 | }; |
933 | static struct node_mem_mask node_masks[MAX_NUMNODES]; | |
934 | static int num_node_masks; | |
935 | ||
48d37216 SR |
936 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
937 | ||
1537b26d PT |
938 | struct mdesc_mlgroup { |
939 | u64 node; | |
940 | u64 latency; | |
941 | u64 match; | |
942 | u64 mask; | |
943 | }; | |
944 | ||
945 | static struct mdesc_mlgroup *mlgroups; | |
946 | static int num_mlgroups; | |
947 | ||
919ee677 DM |
948 | int numa_cpu_lookup_table[NR_CPUS]; |
949 | cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES]; | |
950 | ||
919ee677 DM |
951 | struct mdesc_mblock { |
952 | u64 base; | |
953 | u64 size; | |
954 | u64 offset; /* RA-to-PA */ | |
955 | }; | |
956 | static struct mdesc_mblock *mblocks; | |
957 | static int num_mblocks; | |
958 | ||
1537b26d | 959 | static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr) |
919ee677 | 960 | { |
1537b26d | 961 | struct mdesc_mblock *m = NULL; |
919ee677 DM |
962 | int i; |
963 | ||
964 | for (i = 0; i < num_mblocks; i++) { | |
1537b26d | 965 | m = &mblocks[i]; |
919ee677 DM |
966 | |
967 | if (addr >= m->base && | |
968 | addr < (m->base + m->size)) { | |
919ee677 DM |
969 | break; |
970 | } | |
971 | } | |
1537b26d PT |
972 | |
973 | return m; | |
919ee677 DM |
974 | } |
975 | ||
1537b26d | 976 | static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid) |
919ee677 | 977 | { |
1537b26d | 978 | int prev_nid, new_nid; |
919ee677 | 979 | |
1537b26d PT |
980 | prev_nid = -1; |
981 | for ( ; start < end; start += PAGE_SIZE) { | |
982 | for (new_nid = 0; new_nid < num_node_masks; new_nid++) { | |
983 | struct node_mem_mask *p = &node_masks[new_nid]; | |
919ee677 | 984 | |
1537b26d PT |
985 | if ((start & p->mask) == p->match) { |
986 | if (prev_nid == -1) | |
987 | prev_nid = new_nid; | |
988 | break; | |
989 | } | |
74a5ed5c | 990 | } |
1537b26d PT |
991 | |
992 | if (new_nid == num_node_masks) { | |
993 | prev_nid = 0; | |
994 | WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.", | |
995 | start); | |
996 | break; | |
997 | } | |
998 | ||
999 | if (prev_nid != new_nid) | |
1000 | break; | |
74a5ed5c | 1001 | } |
1537b26d | 1002 | *nid = prev_nid; |
74a5ed5c | 1003 | |
1537b26d | 1004 | return start > end ? end : start; |
919ee677 DM |
1005 | } |
1006 | ||
87a349f9 | 1007 | static u64 __init memblock_nid_range(u64 start, u64 end, int *nid) |
919ee677 | 1008 | { |
1537b26d PT |
1009 | u64 ret_end, pa_start, m_mask, m_match, m_end; |
1010 | struct mdesc_mblock *mblock; | |
1011 | int _nid, i; | |
1012 | ||
1013 | if (tlb_type != hypervisor) | |
1014 | return memblock_nid_range_sun4u(start, end, nid); | |
1015 | ||
1016 | mblock = addr_to_mblock(start); | |
1017 | if (!mblock) { | |
1018 | WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]", | |
1019 | start); | |
1020 | ||
1021 | _nid = 0; | |
1022 | ret_end = end; | |
1023 | goto done; | |
1024 | } | |
1025 | ||
1026 | pa_start = start + mblock->offset; | |
1027 | m_match = 0; | |
1028 | m_mask = 0; | |
919ee677 | 1029 | |
1537b26d PT |
1030 | for (_nid = 0; _nid < num_node_masks; _nid++) { |
1031 | struct node_mem_mask *const m = &node_masks[_nid]; | |
1032 | ||
1033 | if ((pa_start & m->mask) == m->match) { | |
1034 | m_match = m->match; | |
1035 | m_mask = m->mask; | |
919ee677 | 1036 | break; |
1537b26d | 1037 | } |
919ee677 DM |
1038 | } |
1039 | ||
1537b26d PT |
1040 | if (num_node_masks == _nid) { |
1041 | /* We could not find NUMA group, so default to 0, but lets | |
1042 | * search for latency group, so we could calculate the correct | |
1043 | * end address that we return | |
1044 | */ | |
1045 | _nid = 0; | |
1046 | ||
1047 | for (i = 0; i < num_mlgroups; i++) { | |
1048 | struct mdesc_mlgroup *const m = &mlgroups[i]; | |
c918dcce | 1049 | |
1537b26d PT |
1050 | if ((pa_start & m->mask) == m->match) { |
1051 | m_match = m->match; | |
1052 | m_mask = m->mask; | |
1053 | break; | |
1054 | } | |
1055 | } | |
1056 | ||
1057 | if (i == num_mlgroups) { | |
1058 | WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]", | |
1059 | start); | |
1060 | ||
1061 | ret_end = end; | |
1062 | goto done; | |
1063 | } | |
1064 | } | |
1065 | ||
1066 | /* | |
1067 | * Each latency group has match and mask, and each memory block has an | |
1068 | * offset. An address belongs to a latency group if its address matches | |
1069 | * the following formula: ((addr + offset) & mask) == match | |
1070 | * It is, however, slow to check every single page if it matches a | |
1071 | * particular latency group. As optimization we calculate end value by | |
1072 | * using bit arithmetics. | |
1073 | */ | |
1074 | m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset; | |
1075 | m_end += pa_start & ~((1ul << fls64(m_mask)) - 1); | |
1076 | ret_end = m_end > end ? end : m_end; | |
1077 | ||
1078 | done: | |
1079 | *nid = _nid; | |
1080 | return ret_end; | |
919ee677 | 1081 | } |
919ee677 DM |
1082 | #endif |
1083 | ||
1084 | /* This must be invoked after performing all of the necessary | |
2a4814df | 1085 | * memblock_set_node() calls for 'nid'. We need to be able to get |
919ee677 | 1086 | * correct data from get_pfn_range_for_nid(). |
f1cfdb55 | 1087 | */ |
919ee677 DM |
1088 | static void __init allocate_node_data(int nid) |
1089 | { | |
919ee677 | 1090 | struct pglist_data *p; |
aa6f0790 | 1091 | unsigned long start_pfn, end_pfn; |
919ee677 | 1092 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
aa6f0790 PG |
1093 | unsigned long paddr; |
1094 | ||
9d1e2492 | 1095 | paddr = memblock_alloc_try_nid(sizeof(struct pglist_data), SMP_CACHE_BYTES, nid); |
919ee677 DM |
1096 | if (!paddr) { |
1097 | prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid); | |
1098 | prom_halt(); | |
1099 | } | |
1100 | NODE_DATA(nid) = __va(paddr); | |
1101 | memset(NODE_DATA(nid), 0, sizeof(struct pglist_data)); | |
1102 | ||
625d693e | 1103 | NODE_DATA(nid)->node_id = nid; |
919ee677 DM |
1104 | #endif |
1105 | ||
1106 | p = NODE_DATA(nid); | |
1107 | ||
1108 | get_pfn_range_for_nid(nid, &start_pfn, &end_pfn); | |
1109 | p->node_start_pfn = start_pfn; | |
1110 | p->node_spanned_pages = end_pfn - start_pfn; | |
919ee677 DM |
1111 | } |
1112 | ||
1113 | static void init_node_masks_nonnuma(void) | |
d1112018 | 1114 | { |
48d37216 | 1115 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
1da177e4 | 1116 | int i; |
48d37216 | 1117 | #endif |
1da177e4 | 1118 | |
919ee677 | 1119 | numadbg("Initializing tables for non-numa.\n"); |
6fc5bae7 | 1120 | |
1537b26d PT |
1121 | node_masks[0].mask = 0; |
1122 | node_masks[0].match = 0; | |
919ee677 | 1123 | num_node_masks = 1; |
d1112018 | 1124 | |
48d37216 | 1125 | #ifdef CONFIG_NEED_MULTIPLE_NODES |
919ee677 DM |
1126 | for (i = 0; i < NR_CPUS; i++) |
1127 | numa_cpu_lookup_table[i] = 0; | |
1da177e4 | 1128 | |
fb1fece5 | 1129 | cpumask_setall(&numa_cpumask_lookup_table[0]); |
48d37216 | 1130 | #endif |
919ee677 DM |
1131 | } |
1132 | ||
1133 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
1134 | struct pglist_data *node_data[MAX_NUMNODES]; | |
1135 | ||
1136 | EXPORT_SYMBOL(numa_cpu_lookup_table); | |
1137 | EXPORT_SYMBOL(numa_cpumask_lookup_table); | |
1138 | EXPORT_SYMBOL(node_data); | |
1139 | ||
919ee677 DM |
1140 | static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio, |
1141 | u32 cfg_handle) | |
1142 | { | |
1143 | u64 arc; | |
1144 | ||
1145 | mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) { | |
1146 | u64 target = mdesc_arc_target(md, arc); | |
1147 | const u64 *val; | |
1148 | ||
1149 | val = mdesc_get_property(md, target, | |
1150 | "cfg-handle", NULL); | |
1151 | if (val && *val == cfg_handle) | |
1152 | return 0; | |
1153 | } | |
1154 | return -ENODEV; | |
1155 | } | |
1156 | ||
1157 | static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp, | |
1158 | u32 cfg_handle) | |
1159 | { | |
1160 | u64 arc, candidate, best_latency = ~(u64)0; | |
1161 | ||
1162 | candidate = MDESC_NODE_NULL; | |
1163 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
1164 | u64 target = mdesc_arc_target(md, arc); | |
1165 | const char *name = mdesc_node_name(md, target); | |
1166 | const u64 *val; | |
1167 | ||
1168 | if (strcmp(name, "pio-latency-group")) | |
1169 | continue; | |
1170 | ||
1171 | val = mdesc_get_property(md, target, "latency", NULL); | |
1172 | if (!val) | |
1173 | continue; | |
1174 | ||
1175 | if (*val < best_latency) { | |
1176 | candidate = target; | |
1177 | best_latency = *val; | |
1178 | } | |
1179 | } | |
1180 | ||
1181 | if (candidate == MDESC_NODE_NULL) | |
1182 | return -ENODEV; | |
1183 | ||
1184 | return scan_pio_for_cfg_handle(md, candidate, cfg_handle); | |
1185 | } | |
1186 | ||
1187 | int of_node_to_nid(struct device_node *dp) | |
1188 | { | |
1189 | const struct linux_prom64_registers *regs; | |
1190 | struct mdesc_handle *md; | |
1191 | u32 cfg_handle; | |
1192 | int count, nid; | |
1193 | u64 grp; | |
1194 | ||
072bd413 DM |
1195 | /* This is the right thing to do on currently supported |
1196 | * SUN4U NUMA platforms as well, as the PCI controller does | |
1197 | * not sit behind any particular memory controller. | |
1198 | */ | |
919ee677 DM |
1199 | if (!mlgroups) |
1200 | return -1; | |
1201 | ||
1202 | regs = of_get_property(dp, "reg", NULL); | |
1203 | if (!regs) | |
1204 | return -1; | |
1205 | ||
1206 | cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff; | |
1207 | ||
1208 | md = mdesc_grab(); | |
1209 | ||
1210 | count = 0; | |
1211 | nid = -1; | |
1212 | mdesc_for_each_node_by_name(md, grp, "group") { | |
1213 | if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) { | |
1214 | nid = count; | |
1215 | break; | |
1216 | } | |
1217 | count++; | |
1218 | } | |
1219 | ||
1220 | mdesc_release(md); | |
1221 | ||
1222 | return nid; | |
1223 | } | |
1224 | ||
01c45381 | 1225 | static void __init add_node_ranges(void) |
919ee677 | 1226 | { |
08b84798 | 1227 | struct memblock_region *reg; |
cd429ce2 PT |
1228 | unsigned long prev_max; |
1229 | ||
1230 | memblock_resized: | |
1231 | prev_max = memblock.memory.max; | |
919ee677 | 1232 | |
08b84798 BH |
1233 | for_each_memblock(memory, reg) { |
1234 | unsigned long size = reg->size; | |
919ee677 DM |
1235 | unsigned long start, end; |
1236 | ||
08b84798 | 1237 | start = reg->base; |
919ee677 DM |
1238 | end = start + size; |
1239 | while (start < end) { | |
1240 | unsigned long this_end; | |
1241 | int nid; | |
1242 | ||
35a1f0bd | 1243 | this_end = memblock_nid_range(start, end, &nid); |
919ee677 | 1244 | |
2a4814df | 1245 | numadbg("Setting memblock NUMA node nid[%d] " |
919ee677 DM |
1246 | "start[%lx] end[%lx]\n", |
1247 | nid, start, this_end); | |
1248 | ||
e7e8de59 TC |
1249 | memblock_set_node(start, this_end - start, |
1250 | &memblock.memory, nid); | |
cd429ce2 PT |
1251 | if (memblock.memory.max != prev_max) |
1252 | goto memblock_resized; | |
919ee677 DM |
1253 | start = this_end; |
1254 | } | |
1255 | } | |
1256 | } | |
1257 | ||
1258 | static int __init grab_mlgroups(struct mdesc_handle *md) | |
1259 | { | |
1260 | unsigned long paddr; | |
1261 | int count = 0; | |
1262 | u64 node; | |
1263 | ||
1264 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") | |
1265 | count++; | |
1266 | if (!count) | |
1267 | return -ENOENT; | |
1268 | ||
95f72d1e | 1269 | paddr = memblock_alloc(count * sizeof(struct mdesc_mlgroup), |
919ee677 DM |
1270 | SMP_CACHE_BYTES); |
1271 | if (!paddr) | |
1272 | return -ENOMEM; | |
1273 | ||
1274 | mlgroups = __va(paddr); | |
1275 | num_mlgroups = count; | |
1276 | ||
1277 | count = 0; | |
1278 | mdesc_for_each_node_by_name(md, node, "memory-latency-group") { | |
1279 | struct mdesc_mlgroup *m = &mlgroups[count++]; | |
1280 | const u64 *val; | |
1281 | ||
1282 | m->node = node; | |
1283 | ||
1284 | val = mdesc_get_property(md, node, "latency", NULL); | |
1285 | m->latency = *val; | |
1286 | val = mdesc_get_property(md, node, "address-match", NULL); | |
1287 | m->match = *val; | |
1288 | val = mdesc_get_property(md, node, "address-mask", NULL); | |
1289 | m->mask = *val; | |
1290 | ||
90181136 SR |
1291 | numadbg("MLGROUP[%d]: node[%llx] latency[%llx] " |
1292 | "match[%llx] mask[%llx]\n", | |
919ee677 DM |
1293 | count - 1, m->node, m->latency, m->match, m->mask); |
1294 | } | |
1295 | ||
1296 | return 0; | |
1297 | } | |
1298 | ||
1299 | static int __init grab_mblocks(struct mdesc_handle *md) | |
1300 | { | |
1301 | unsigned long paddr; | |
1302 | int count = 0; | |
1303 | u64 node; | |
1304 | ||
1305 | mdesc_for_each_node_by_name(md, node, "mblock") | |
1306 | count++; | |
1307 | if (!count) | |
1308 | return -ENOENT; | |
1309 | ||
95f72d1e | 1310 | paddr = memblock_alloc(count * sizeof(struct mdesc_mblock), |
919ee677 DM |
1311 | SMP_CACHE_BYTES); |
1312 | if (!paddr) | |
1313 | return -ENOMEM; | |
1314 | ||
1315 | mblocks = __va(paddr); | |
1316 | num_mblocks = count; | |
1317 | ||
1318 | count = 0; | |
1319 | mdesc_for_each_node_by_name(md, node, "mblock") { | |
1320 | struct mdesc_mblock *m = &mblocks[count++]; | |
1321 | const u64 *val; | |
1322 | ||
1323 | val = mdesc_get_property(md, node, "base", NULL); | |
1324 | m->base = *val; | |
1325 | val = mdesc_get_property(md, node, "size", NULL); | |
1326 | m->size = *val; | |
1327 | val = mdesc_get_property(md, node, | |
1328 | "address-congruence-offset", NULL); | |
771a37ff | 1329 | |
1330 | /* The address-congruence-offset property is optional. | |
1331 | * Explicity zero it be identifty this. | |
1332 | */ | |
1333 | if (val) | |
1334 | m->offset = *val; | |
1335 | else | |
1336 | m->offset = 0UL; | |
919ee677 | 1337 | |
90181136 | 1338 | numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n", |
919ee677 DM |
1339 | count - 1, m->base, m->size, m->offset); |
1340 | } | |
1341 | ||
1342 | return 0; | |
1343 | } | |
1344 | ||
1345 | static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md, | |
1346 | u64 grp, cpumask_t *mask) | |
1347 | { | |
1348 | u64 arc; | |
1349 | ||
fb1fece5 | 1350 | cpumask_clear(mask); |
919ee677 DM |
1351 | |
1352 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) { | |
1353 | u64 target = mdesc_arc_target(md, arc); | |
1354 | const char *name = mdesc_node_name(md, target); | |
1355 | const u64 *id; | |
1356 | ||
1357 | if (strcmp(name, "cpu")) | |
1358 | continue; | |
1359 | id = mdesc_get_property(md, target, "id", NULL); | |
e305cb8f | 1360 | if (*id < nr_cpu_ids) |
fb1fece5 | 1361 | cpumask_set_cpu(*id, mask); |
919ee677 DM |
1362 | } |
1363 | } | |
1364 | ||
1365 | static struct mdesc_mlgroup * __init find_mlgroup(u64 node) | |
1366 | { | |
1367 | int i; | |
1368 | ||
1369 | for (i = 0; i < num_mlgroups; i++) { | |
1370 | struct mdesc_mlgroup *m = &mlgroups[i]; | |
1371 | if (m->node == node) | |
1372 | return m; | |
1373 | } | |
1374 | return NULL; | |
1375 | } | |
1376 | ||
52708d69 NG |
1377 | int __node_distance(int from, int to) |
1378 | { | |
1379 | if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) { | |
1380 | pr_warn("Returning default NUMA distance value for %d->%d\n", | |
1381 | from, to); | |
1382 | return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE; | |
1383 | } | |
1384 | return numa_latency[from][to]; | |
1385 | } | |
1386 | ||
bdf2f59e | 1387 | static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp) |
52708d69 NG |
1388 | { |
1389 | int i; | |
1390 | ||
1391 | for (i = 0; i < MAX_NUMNODES; i++) { | |
1392 | struct node_mem_mask *n = &node_masks[i]; | |
1393 | ||
1537b26d | 1394 | if ((grp->mask == n->mask) && (grp->match == n->match)) |
52708d69 NG |
1395 | break; |
1396 | } | |
1397 | return i; | |
1398 | } | |
1399 | ||
bdf2f59e PG |
1400 | static void __init find_numa_latencies_for_group(struct mdesc_handle *md, |
1401 | u64 grp, int index) | |
52708d69 NG |
1402 | { |
1403 | u64 arc; | |
1404 | ||
1405 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
1406 | int tnode; | |
1407 | u64 target = mdesc_arc_target(md, arc); | |
1408 | struct mdesc_mlgroup *m = find_mlgroup(target); | |
1409 | ||
1410 | if (!m) | |
1411 | continue; | |
1412 | tnode = find_best_numa_node_for_mlgroup(m); | |
1413 | if (tnode == MAX_NUMNODES) | |
1414 | continue; | |
1415 | numa_latency[index][tnode] = m->latency; | |
1416 | } | |
1417 | } | |
1418 | ||
919ee677 DM |
1419 | static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp, |
1420 | int index) | |
1421 | { | |
1422 | struct mdesc_mlgroup *candidate = NULL; | |
1423 | u64 arc, best_latency = ~(u64)0; | |
1424 | struct node_mem_mask *n; | |
1425 | ||
1426 | mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) { | |
1427 | u64 target = mdesc_arc_target(md, arc); | |
1428 | struct mdesc_mlgroup *m = find_mlgroup(target); | |
1429 | if (!m) | |
1430 | continue; | |
1431 | if (m->latency < best_latency) { | |
1432 | candidate = m; | |
1433 | best_latency = m->latency; | |
1434 | } | |
1435 | } | |
1436 | if (!candidate) | |
1437 | return -ENOENT; | |
1438 | ||
1439 | if (num_node_masks != index) { | |
1440 | printk(KERN_ERR "Inconsistent NUMA state, " | |
1441 | "index[%d] != num_node_masks[%d]\n", | |
1442 | index, num_node_masks); | |
1443 | return -EINVAL; | |
1444 | } | |
1445 | ||
1446 | n = &node_masks[num_node_masks++]; | |
1447 | ||
1448 | n->mask = candidate->mask; | |
1537b26d | 1449 | n->match = candidate->match; |
1da177e4 | 1450 | |
1537b26d PT |
1451 | numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n", |
1452 | index, n->mask, n->match, candidate->latency); | |
1da177e4 | 1453 | |
919ee677 DM |
1454 | return 0; |
1455 | } | |
1456 | ||
1457 | static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp, | |
1458 | int index) | |
1459 | { | |
1460 | cpumask_t mask; | |
1461 | int cpu; | |
1462 | ||
1463 | numa_parse_mdesc_group_cpus(md, grp, &mask); | |
1464 | ||
fb1fece5 | 1465 | for_each_cpu(cpu, &mask) |
919ee677 | 1466 | numa_cpu_lookup_table[cpu] = index; |
fb1fece5 | 1467 | cpumask_copy(&numa_cpumask_lookup_table[index], &mask); |
919ee677 DM |
1468 | |
1469 | if (numa_debug) { | |
1470 | printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index); | |
fb1fece5 | 1471 | for_each_cpu(cpu, &mask) |
919ee677 DM |
1472 | printk("%d ", cpu); |
1473 | printk("]\n"); | |
1474 | } | |
1475 | ||
1476 | return numa_attach_mlgroup(md, grp, index); | |
1477 | } | |
1478 | ||
1479 | static int __init numa_parse_mdesc(void) | |
1480 | { | |
1481 | struct mdesc_handle *md = mdesc_grab(); | |
52708d69 | 1482 | int i, j, err, count; |
919ee677 DM |
1483 | u64 node; |
1484 | ||
1485 | node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups"); | |
1486 | if (node == MDESC_NODE_NULL) { | |
1487 | mdesc_release(md); | |
1488 | return -ENOENT; | |
1489 | } | |
1490 | ||
1491 | err = grab_mblocks(md); | |
1492 | if (err < 0) | |
1493 | goto out; | |
1494 | ||
1495 | err = grab_mlgroups(md); | |
1496 | if (err < 0) | |
1497 | goto out; | |
1498 | ||
1499 | count = 0; | |
1500 | mdesc_for_each_node_by_name(md, node, "group") { | |
1501 | err = numa_parse_mdesc_group(md, node, count); | |
1502 | if (err < 0) | |
1503 | break; | |
1504 | count++; | |
1505 | } | |
1506 | ||
52708d69 NG |
1507 | count = 0; |
1508 | mdesc_for_each_node_by_name(md, node, "group") { | |
1509 | find_numa_latencies_for_group(md, node, count); | |
1510 | count++; | |
1511 | } | |
1512 | ||
1513 | /* Normalize numa latency matrix according to ACPI SLIT spec. */ | |
1514 | for (i = 0; i < MAX_NUMNODES; i++) { | |
1515 | u64 self_latency = numa_latency[i][i]; | |
1516 | ||
1517 | for (j = 0; j < MAX_NUMNODES; j++) { | |
1518 | numa_latency[i][j] = | |
1519 | (numa_latency[i][j] * LOCAL_DISTANCE) / | |
1520 | self_latency; | |
1521 | } | |
1522 | } | |
1523 | ||
919ee677 DM |
1524 | add_node_ranges(); |
1525 | ||
1526 | for (i = 0; i < num_node_masks; i++) { | |
1527 | allocate_node_data(i); | |
1528 | node_set_online(i); | |
1529 | } | |
1530 | ||
1531 | err = 0; | |
1532 | out: | |
1533 | mdesc_release(md); | |
1534 | return err; | |
1535 | } | |
1536 | ||
072bd413 DM |
1537 | static int __init numa_parse_jbus(void) |
1538 | { | |
1539 | unsigned long cpu, index; | |
1540 | ||
1541 | /* NUMA node id is encoded in bits 36 and higher, and there is | |
1542 | * a 1-to-1 mapping from CPU ID to NUMA node ID. | |
1543 | */ | |
1544 | index = 0; | |
1545 | for_each_present_cpu(cpu) { | |
1546 | numa_cpu_lookup_table[cpu] = index; | |
fb1fece5 | 1547 | cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu)); |
072bd413 | 1548 | node_masks[index].mask = ~((1UL << 36UL) - 1UL); |
1537b26d | 1549 | node_masks[index].match = cpu << 36UL; |
072bd413 DM |
1550 | |
1551 | index++; | |
1552 | } | |
1553 | num_node_masks = index; | |
1554 | ||
1555 | add_node_ranges(); | |
1556 | ||
1557 | for (index = 0; index < num_node_masks; index++) { | |
1558 | allocate_node_data(index); | |
1559 | node_set_online(index); | |
1560 | } | |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
919ee677 DM |
1565 | static int __init numa_parse_sun4u(void) |
1566 | { | |
072bd413 DM |
1567 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1568 | unsigned long ver; | |
1569 | ||
1570 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
1571 | if ((ver >> 32UL) == __JALAPENO_ID || | |
1572 | (ver >> 32UL) == __SERRANO_ID) | |
1573 | return numa_parse_jbus(); | |
1574 | } | |
919ee677 DM |
1575 | return -1; |
1576 | } | |
1577 | ||
1578 | static int __init bootmem_init_numa(void) | |
1579 | { | |
36beca65 | 1580 | int i, j; |
919ee677 DM |
1581 | int err = -1; |
1582 | ||
1583 | numadbg("bootmem_init_numa()\n"); | |
1584 | ||
36beca65 NG |
1585 | /* Some sane defaults for numa latency values */ |
1586 | for (i = 0; i < MAX_NUMNODES; i++) { | |
1587 | for (j = 0; j < MAX_NUMNODES; j++) | |
1588 | numa_latency[i][j] = (i == j) ? | |
1589 | LOCAL_DISTANCE : REMOTE_DISTANCE; | |
1590 | } | |
1591 | ||
919ee677 DM |
1592 | if (numa_enabled) { |
1593 | if (tlb_type == hypervisor) | |
1594 | err = numa_parse_mdesc(); | |
1595 | else | |
1596 | err = numa_parse_sun4u(); | |
1597 | } | |
1598 | return err; | |
1599 | } | |
1600 | ||
1601 | #else | |
1da177e4 | 1602 | |
919ee677 DM |
1603 | static int bootmem_init_numa(void) |
1604 | { | |
1605 | return -1; | |
1606 | } | |
1607 | ||
1608 | #endif | |
1609 | ||
1610 | static void __init bootmem_init_nonnuma(void) | |
1611 | { | |
95f72d1e YL |
1612 | unsigned long top_of_ram = memblock_end_of_DRAM(); |
1613 | unsigned long total_ram = memblock_phys_mem_size(); | |
919ee677 DM |
1614 | |
1615 | numadbg("bootmem_init_nonnuma()\n"); | |
1616 | ||
1617 | printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n", | |
1618 | top_of_ram, total_ram); | |
1619 | printk(KERN_INFO "Memory hole size: %ldMB\n", | |
1620 | (top_of_ram - total_ram) >> 20); | |
1621 | ||
1622 | init_node_masks_nonnuma(); | |
e7e8de59 | 1623 | memblock_set_node(0, (phys_addr_t)ULLONG_MAX, &memblock.memory, 0); |
919ee677 | 1624 | allocate_node_data(0); |
919ee677 DM |
1625 | node_set_online(0); |
1626 | } | |
1627 | ||
919ee677 DM |
1628 | static unsigned long __init bootmem_init(unsigned long phys_base) |
1629 | { | |
1630 | unsigned long end_pfn; | |
919ee677 | 1631 | |
95f72d1e | 1632 | end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT; |
919ee677 DM |
1633 | max_pfn = max_low_pfn = end_pfn; |
1634 | min_low_pfn = (phys_base >> PAGE_SHIFT); | |
1635 | ||
1636 | if (bootmem_init_numa() < 0) | |
1637 | bootmem_init_nonnuma(); | |
1638 | ||
625d693e DM |
1639 | /* Dump memblock with node info. */ |
1640 | memblock_dump_all(); | |
919ee677 | 1641 | |
625d693e | 1642 | /* XXX cpu notifier XXX */ |
d1112018 | 1643 | |
625d693e | 1644 | sparse_memory_present_with_active_regions(MAX_NUMNODES); |
d1112018 DM |
1645 | sparse_init(); |
1646 | ||
1da177e4 LT |
1647 | return end_pfn; |
1648 | } | |
1649 | ||
9cc3a1ac DM |
1650 | static struct linux_prom64_registers pall[MAX_BANKS] __initdata; |
1651 | static int pall_ents __initdata; | |
1652 | ||
0dd5b7b0 DM |
1653 | static unsigned long max_phys_bits = 40; |
1654 | ||
1655 | bool kern_addr_valid(unsigned long addr) | |
1656 | { | |
0dd5b7b0 DM |
1657 | pgd_t *pgd; |
1658 | pud_t *pud; | |
1659 | pmd_t *pmd; | |
1660 | pte_t *pte; | |
1661 | ||
bb4e6e85 | 1662 | if ((long)addr < 0L) { |
0dd5b7b0 DM |
1663 | unsigned long pa = __pa(addr); |
1664 | ||
adfae8a5 | 1665 | if ((pa >> max_phys_bits) != 0UL) |
bb4e6e85 DM |
1666 | return false; |
1667 | ||
0dd5b7b0 DM |
1668 | return pfn_valid(pa >> PAGE_SHIFT); |
1669 | } | |
1670 | ||
bb4e6e85 DM |
1671 | if (addr >= (unsigned long) KERNBASE && |
1672 | addr < (unsigned long)&_end) | |
1673 | return true; | |
1674 | ||
0dd5b7b0 DM |
1675 | pgd = pgd_offset_k(addr); |
1676 | if (pgd_none(*pgd)) | |
1677 | return 0; | |
1678 | ||
1679 | pud = pud_offset(pgd, addr); | |
1680 | if (pud_none(*pud)) | |
1681 | return 0; | |
1682 | ||
1683 | if (pud_large(*pud)) | |
1684 | return pfn_valid(pud_pfn(*pud)); | |
1685 | ||
1686 | pmd = pmd_offset(pud, addr); | |
1687 | if (pmd_none(*pmd)) | |
1688 | return 0; | |
1689 | ||
1690 | if (pmd_large(*pmd)) | |
1691 | return pfn_valid(pmd_pfn(*pmd)); | |
1692 | ||
1693 | pte = pte_offset_kernel(pmd, addr); | |
1694 | if (pte_none(*pte)) | |
1695 | return 0; | |
1696 | ||
1697 | return pfn_valid(pte_pfn(*pte)); | |
1698 | } | |
1699 | EXPORT_SYMBOL(kern_addr_valid); | |
1700 | ||
1701 | static unsigned long __ref kernel_map_hugepud(unsigned long vstart, | |
1702 | unsigned long vend, | |
1703 | pud_t *pud) | |
1704 | { | |
1705 | const unsigned long mask16gb = (1UL << 34) - 1UL; | |
1706 | u64 pte_val = vstart; | |
1707 | ||
1708 | /* Each PUD is 8GB */ | |
1709 | if ((vstart & mask16gb) || | |
1710 | (vend - vstart <= mask16gb)) { | |
1711 | pte_val ^= kern_linear_pte_xor[2]; | |
1712 | pud_val(*pud) = pte_val | _PAGE_PUD_HUGE; | |
1713 | ||
1714 | return vstart + PUD_SIZE; | |
1715 | } | |
1716 | ||
1717 | pte_val ^= kern_linear_pte_xor[3]; | |
1718 | pte_val |= _PAGE_PUD_HUGE; | |
1719 | ||
1720 | vend = vstart + mask16gb + 1UL; | |
1721 | while (vstart < vend) { | |
1722 | pud_val(*pud) = pte_val; | |
1723 | ||
1724 | pte_val += PUD_SIZE; | |
1725 | vstart += PUD_SIZE; | |
1726 | pud++; | |
1727 | } | |
1728 | return vstart; | |
1729 | } | |
1730 | ||
1731 | static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend, | |
1732 | bool guard) | |
1733 | { | |
1734 | if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE) | |
1735 | return true; | |
1736 | ||
1737 | return false; | |
1738 | } | |
1739 | ||
1740 | static unsigned long __ref kernel_map_hugepmd(unsigned long vstart, | |
1741 | unsigned long vend, | |
1742 | pmd_t *pmd) | |
1743 | { | |
1744 | const unsigned long mask256mb = (1UL << 28) - 1UL; | |
1745 | const unsigned long mask2gb = (1UL << 31) - 1UL; | |
1746 | u64 pte_val = vstart; | |
1747 | ||
1748 | /* Each PMD is 8MB */ | |
1749 | if ((vstart & mask256mb) || | |
1750 | (vend - vstart <= mask256mb)) { | |
1751 | pte_val ^= kern_linear_pte_xor[0]; | |
1752 | pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE; | |
1753 | ||
1754 | return vstart + PMD_SIZE; | |
1755 | } | |
1756 | ||
1757 | if ((vstart & mask2gb) || | |
1758 | (vend - vstart <= mask2gb)) { | |
1759 | pte_val ^= kern_linear_pte_xor[1]; | |
1760 | pte_val |= _PAGE_PMD_HUGE; | |
1761 | vend = vstart + mask256mb + 1UL; | |
1762 | } else { | |
1763 | pte_val ^= kern_linear_pte_xor[2]; | |
1764 | pte_val |= _PAGE_PMD_HUGE; | |
1765 | vend = vstart + mask2gb + 1UL; | |
1766 | } | |
1767 | ||
1768 | while (vstart < vend) { | |
1769 | pmd_val(*pmd) = pte_val; | |
1770 | ||
1771 | pte_val += PMD_SIZE; | |
1772 | vstart += PMD_SIZE; | |
1773 | pmd++; | |
1774 | } | |
1775 | ||
1776 | return vstart; | |
1777 | } | |
1778 | ||
1779 | static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend, | |
1780 | bool guard) | |
1781 | { | |
1782 | if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE) | |
1783 | return true; | |
1784 | ||
1785 | return false; | |
1786 | } | |
1787 | ||
896aef43 | 1788 | static unsigned long __ref kernel_map_range(unsigned long pstart, |
0dd5b7b0 DM |
1789 | unsigned long pend, pgprot_t prot, |
1790 | bool use_huge) | |
56425306 DM |
1791 | { |
1792 | unsigned long vstart = PAGE_OFFSET + pstart; | |
1793 | unsigned long vend = PAGE_OFFSET + pend; | |
1794 | unsigned long alloc_bytes = 0UL; | |
1795 | ||
1796 | if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) { | |
13edad7a | 1797 | prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n", |
56425306 DM |
1798 | vstart, vend); |
1799 | prom_halt(); | |
1800 | } | |
1801 | ||
1802 | while (vstart < vend) { | |
1803 | unsigned long this_end, paddr = __pa(vstart); | |
1804 | pgd_t *pgd = pgd_offset_k(vstart); | |
1805 | pud_t *pud; | |
1806 | pmd_t *pmd; | |
1807 | pte_t *pte; | |
1808 | ||
ac55c768 DM |
1809 | if (pgd_none(*pgd)) { |
1810 | pud_t *new; | |
1811 | ||
1812 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); | |
1813 | alloc_bytes += PAGE_SIZE; | |
1814 | pgd_populate(&init_mm, pgd, new); | |
1815 | } | |
56425306 DM |
1816 | pud = pud_offset(pgd, vstart); |
1817 | if (pud_none(*pud)) { | |
1818 | pmd_t *new; | |
1819 | ||
0dd5b7b0 DM |
1820 | if (kernel_can_map_hugepud(vstart, vend, use_huge)) { |
1821 | vstart = kernel_map_hugepud(vstart, vend, pud); | |
1822 | continue; | |
1823 | } | |
56425306 DM |
1824 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); |
1825 | alloc_bytes += PAGE_SIZE; | |
1826 | pud_populate(&init_mm, pud, new); | |
1827 | } | |
1828 | ||
1829 | pmd = pmd_offset(pud, vstart); | |
0dd5b7b0 | 1830 | if (pmd_none(*pmd)) { |
56425306 DM |
1831 | pte_t *new; |
1832 | ||
0dd5b7b0 DM |
1833 | if (kernel_can_map_hugepmd(vstart, vend, use_huge)) { |
1834 | vstart = kernel_map_hugepmd(vstart, vend, pmd); | |
1835 | continue; | |
1836 | } | |
56425306 DM |
1837 | new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE); |
1838 | alloc_bytes += PAGE_SIZE; | |
1839 | pmd_populate_kernel(&init_mm, pmd, new); | |
1840 | } | |
1841 | ||
1842 | pte = pte_offset_kernel(pmd, vstart); | |
1843 | this_end = (vstart + PMD_SIZE) & PMD_MASK; | |
1844 | if (this_end > vend) | |
1845 | this_end = vend; | |
1846 | ||
1847 | while (vstart < this_end) { | |
1848 | pte_val(*pte) = (paddr | pgprot_val(prot)); | |
1849 | ||
1850 | vstart += PAGE_SIZE; | |
1851 | paddr += PAGE_SIZE; | |
1852 | pte++; | |
1853 | } | |
1854 | } | |
1855 | ||
1856 | return alloc_bytes; | |
1857 | } | |
1858 | ||
0dd5b7b0 | 1859 | static void __init flush_all_kernel_tsbs(void) |
4f93d21d | 1860 | { |
0dd5b7b0 | 1861 | int i; |
4f93d21d | 1862 | |
0dd5b7b0 DM |
1863 | for (i = 0; i < KERNEL_TSB_NENTRIES; i++) { |
1864 | struct tsb *ent = &swapper_tsb[i]; | |
4f93d21d | 1865 | |
0dd5b7b0 | 1866 | ent->tag = (1UL << TSB_TAG_INVALID_BIT); |
4f93d21d | 1867 | } |
0dd5b7b0 DM |
1868 | #ifndef CONFIG_DEBUG_PAGEALLOC |
1869 | for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) { | |
1870 | struct tsb *ent = &swapper_4m_tsb[i]; | |
4f93d21d | 1871 | |
0dd5b7b0 | 1872 | ent->tag = (1UL << TSB_TAG_INVALID_BIT); |
9cc3a1ac | 1873 | } |
0dd5b7b0 | 1874 | #endif |
9cc3a1ac | 1875 | } |
56425306 | 1876 | |
0dd5b7b0 | 1877 | extern unsigned int kvmap_linear_patch[1]; |
9cc3a1ac | 1878 | |
8f361453 DM |
1879 | static void __init kernel_physical_mapping_init(void) |
1880 | { | |
8f361453 | 1881 | unsigned long i, mem_alloced = 0UL; |
0dd5b7b0 | 1882 | bool use_huge = true; |
8f361453 | 1883 | |
0dd5b7b0 DM |
1884 | #ifdef CONFIG_DEBUG_PAGEALLOC |
1885 | use_huge = false; | |
1886 | #endif | |
8f361453 DM |
1887 | for (i = 0; i < pall_ents; i++) { |
1888 | unsigned long phys_start, phys_end; | |
1889 | ||
1890 | phys_start = pall[i].phys_addr; | |
1891 | phys_end = phys_start + pall[i].reg_size; | |
1892 | ||
56425306 | 1893 | mem_alloced += kernel_map_range(phys_start, phys_end, |
0dd5b7b0 | 1894 | PAGE_KERNEL, use_huge); |
56425306 DM |
1895 | } |
1896 | ||
1897 | printk("Allocated %ld bytes for kernel page tables.\n", | |
1898 | mem_alloced); | |
1899 | ||
1900 | kvmap_linear_patch[0] = 0x01000000; /* nop */ | |
1901 | flushi(&kvmap_linear_patch[0]); | |
1902 | ||
0dd5b7b0 DM |
1903 | flush_all_kernel_tsbs(); |
1904 | ||
56425306 DM |
1905 | __flush_tlb_all(); |
1906 | } | |
1907 | ||
9cc3a1ac | 1908 | #ifdef CONFIG_DEBUG_PAGEALLOC |
031bc574 | 1909 | void __kernel_map_pages(struct page *page, int numpages, int enable) |
56425306 DM |
1910 | { |
1911 | unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT; | |
1912 | unsigned long phys_end = phys_start + (numpages * PAGE_SIZE); | |
1913 | ||
1914 | kernel_map_range(phys_start, phys_end, | |
0dd5b7b0 | 1915 | (enable ? PAGE_KERNEL : __pgprot(0)), false); |
56425306 | 1916 | |
74bf4312 DM |
1917 | flush_tsb_kernel_range(PAGE_OFFSET + phys_start, |
1918 | PAGE_OFFSET + phys_end); | |
1919 | ||
56425306 DM |
1920 | /* we should perform an IPI and flush all tlbs, |
1921 | * but that can deadlock->flush only current cpu. | |
1922 | */ | |
1923 | __flush_tlb_kernel_range(PAGE_OFFSET + phys_start, | |
1924 | PAGE_OFFSET + phys_end); | |
1925 | } | |
1926 | #endif | |
1927 | ||
10147570 DM |
1928 | unsigned long __init find_ecache_flush_span(unsigned long size) |
1929 | { | |
0836a0eb DM |
1930 | int i; |
1931 | ||
13edad7a DM |
1932 | for (i = 0; i < pavail_ents; i++) { |
1933 | if (pavail[i].reg_size >= size) | |
1934 | return pavail[i].phys_addr; | |
0836a0eb DM |
1935 | } |
1936 | ||
13edad7a | 1937 | return ~0UL; |
0836a0eb DM |
1938 | } |
1939 | ||
b2d43834 DM |
1940 | unsigned long PAGE_OFFSET; |
1941 | EXPORT_SYMBOL(PAGE_OFFSET); | |
1942 | ||
bb4e6e85 DM |
1943 | unsigned long VMALLOC_END = 0x0000010000000000UL; |
1944 | EXPORT_SYMBOL(VMALLOC_END); | |
1945 | ||
4397bed0 DM |
1946 | unsigned long sparc64_va_hole_top = 0xfffff80000000000UL; |
1947 | unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL; | |
1948 | ||
b2d43834 DM |
1949 | static void __init setup_page_offset(void) |
1950 | { | |
b2d43834 | 1951 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
4397bed0 DM |
1952 | /* Cheetah/Panther support a full 64-bit virtual |
1953 | * address, so we can use all that our page tables | |
1954 | * support. | |
1955 | */ | |
1956 | sparc64_va_hole_top = 0xfff0000000000000UL; | |
1957 | sparc64_va_hole_bottom = 0x0010000000000000UL; | |
1958 | ||
b2d43834 DM |
1959 | max_phys_bits = 42; |
1960 | } else if (tlb_type == hypervisor) { | |
1961 | switch (sun4v_chip_type) { | |
1962 | case SUN4V_CHIP_NIAGARA1: | |
1963 | case SUN4V_CHIP_NIAGARA2: | |
4397bed0 DM |
1964 | /* T1 and T2 support 48-bit virtual addresses. */ |
1965 | sparc64_va_hole_top = 0xffff800000000000UL; | |
1966 | sparc64_va_hole_bottom = 0x0000800000000000UL; | |
1967 | ||
b2d43834 DM |
1968 | max_phys_bits = 39; |
1969 | break; | |
1970 | case SUN4V_CHIP_NIAGARA3: | |
4397bed0 DM |
1971 | /* T3 supports 48-bit virtual addresses. */ |
1972 | sparc64_va_hole_top = 0xffff800000000000UL; | |
1973 | sparc64_va_hole_bottom = 0x0000800000000000UL; | |
1974 | ||
b2d43834 DM |
1975 | max_phys_bits = 43; |
1976 | break; | |
1977 | case SUN4V_CHIP_NIAGARA4: | |
1978 | case SUN4V_CHIP_NIAGARA5: | |
1979 | case SUN4V_CHIP_SPARC64X: | |
7c0fa0f2 | 1980 | case SUN4V_CHIP_SPARC_M6: |
4397bed0 DM |
1981 | /* T4 and later support 52-bit virtual addresses. */ |
1982 | sparc64_va_hole_top = 0xfff8000000000000UL; | |
1983 | sparc64_va_hole_bottom = 0x0008000000000000UL; | |
b2d43834 DM |
1984 | max_phys_bits = 47; |
1985 | break; | |
7c0fa0f2 | 1986 | case SUN4V_CHIP_SPARC_M7: |
c5b8b5be | 1987 | case SUN4V_CHIP_SPARC_SN: |
7c0fa0f2 DM |
1988 | /* M7 and later support 52-bit virtual addresses. */ |
1989 | sparc64_va_hole_top = 0xfff8000000000000UL; | |
1990 | sparc64_va_hole_bottom = 0x0008000000000000UL; | |
1991 | max_phys_bits = 49; | |
1992 | break; | |
fdaccf74 VK |
1993 | case SUN4V_CHIP_SPARC_M8: |
1994 | default: | |
1995 | /* M8 and later support 54-bit virtual addresses. | |
1996 | * However, restricting M8 and above VA bits to 53 | |
1997 | * as 4-level page table cannot support more than | |
1998 | * 53 VA bits. | |
1999 | */ | |
2000 | sparc64_va_hole_top = 0xfff0000000000000UL; | |
2001 | sparc64_va_hole_bottom = 0x0010000000000000UL; | |
2002 | max_phys_bits = 51; | |
2003 | break; | |
b2d43834 DM |
2004 | } |
2005 | } | |
2006 | ||
2007 | if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) { | |
2008 | prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n", | |
2009 | max_phys_bits); | |
2010 | prom_halt(); | |
2011 | } | |
2012 | ||
bb4e6e85 DM |
2013 | PAGE_OFFSET = sparc64_va_hole_top; |
2014 | VMALLOC_END = ((sparc64_va_hole_bottom >> 1) + | |
2015 | (sparc64_va_hole_bottom >> 2)); | |
b2d43834 | 2016 | |
bb4e6e85 | 2017 | pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n", |
b2d43834 | 2018 | PAGE_OFFSET, max_phys_bits); |
bb4e6e85 DM |
2019 | pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n", |
2020 | VMALLOC_START, VMALLOC_END); | |
2021 | pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n", | |
2022 | VMEMMAP_BASE, VMEMMAP_BASE << 1); | |
b2d43834 DM |
2023 | } |
2024 | ||
517af332 DM |
2025 | static void __init tsb_phys_patch(void) |
2026 | { | |
d257d5da | 2027 | struct tsb_ldquad_phys_patch_entry *pquad; |
517af332 DM |
2028 | struct tsb_phys_patch_entry *p; |
2029 | ||
d257d5da DM |
2030 | pquad = &__tsb_ldquad_phys_patch; |
2031 | while (pquad < &__tsb_ldquad_phys_patch_end) { | |
2032 | unsigned long addr = pquad->addr; | |
2033 | ||
2034 | if (tlb_type == hypervisor) | |
2035 | *(unsigned int *) addr = pquad->sun4v_insn; | |
2036 | else | |
2037 | *(unsigned int *) addr = pquad->sun4u_insn; | |
2038 | wmb(); | |
2039 | __asm__ __volatile__("flush %0" | |
2040 | : /* no outputs */ | |
2041 | : "r" (addr)); | |
2042 | ||
2043 | pquad++; | |
2044 | } | |
2045 | ||
517af332 DM |
2046 | p = &__tsb_phys_patch; |
2047 | while (p < &__tsb_phys_patch_end) { | |
2048 | unsigned long addr = p->addr; | |
2049 | ||
2050 | *(unsigned int *) addr = p->insn; | |
2051 | wmb(); | |
2052 | __asm__ __volatile__("flush %0" | |
2053 | : /* no outputs */ | |
2054 | : "r" (addr)); | |
2055 | ||
2056 | p++; | |
2057 | } | |
2058 | } | |
2059 | ||
490384e7 | 2060 | /* Don't mark as init, we give this to the Hypervisor. */ |
d1acb421 DM |
2061 | #ifndef CONFIG_DEBUG_PAGEALLOC |
2062 | #define NUM_KTSB_DESCR 2 | |
2063 | #else | |
2064 | #define NUM_KTSB_DESCR 1 | |
2065 | #endif | |
2066 | static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR]; | |
490384e7 | 2067 | |
8c82dc0e DM |
2068 | /* The swapper TSBs are loaded with a base sequence of: |
2069 | * | |
2070 | * sethi %uhi(SYMBOL), REG1 | |
2071 | * sethi %hi(SYMBOL), REG2 | |
2072 | * or REG1, %ulo(SYMBOL), REG1 | |
2073 | * or REG2, %lo(SYMBOL), REG2 | |
2074 | * sllx REG1, 32, REG1 | |
2075 | * or REG1, REG2, REG1 | |
2076 | * | |
2077 | * When we use physical addressing for the TSB accesses, we patch the | |
2078 | * first four instructions in the above sequence. | |
2079 | */ | |
2080 | ||
9076d0e7 DM |
2081 | static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa) |
2082 | { | |
8c82dc0e DM |
2083 | unsigned long high_bits, low_bits; |
2084 | ||
2085 | high_bits = (pa >> 32) & 0xffffffff; | |
2086 | low_bits = (pa >> 0) & 0xffffffff; | |
9076d0e7 DM |
2087 | |
2088 | while (start < end) { | |
2089 | unsigned int *ia = (unsigned int *)(unsigned long)*start; | |
2090 | ||
8c82dc0e | 2091 | ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10); |
9076d0e7 DM |
2092 | __asm__ __volatile__("flush %0" : : "r" (ia)); |
2093 | ||
8c82dc0e | 2094 | ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10); |
9076d0e7 DM |
2095 | __asm__ __volatile__("flush %0" : : "r" (ia + 1)); |
2096 | ||
8c82dc0e DM |
2097 | ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff); |
2098 | __asm__ __volatile__("flush %0" : : "r" (ia + 2)); | |
2099 | ||
2100 | ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff); | |
2101 | __asm__ __volatile__("flush %0" : : "r" (ia + 3)); | |
2102 | ||
9076d0e7 DM |
2103 | start++; |
2104 | } | |
2105 | } | |
2106 | ||
2107 | static void ktsb_phys_patch(void) | |
2108 | { | |
2109 | extern unsigned int __swapper_tsb_phys_patch; | |
2110 | extern unsigned int __swapper_tsb_phys_patch_end; | |
9076d0e7 DM |
2111 | unsigned long ktsb_pa; |
2112 | ||
2113 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); | |
2114 | patch_one_ktsb_phys(&__swapper_tsb_phys_patch, | |
2115 | &__swapper_tsb_phys_patch_end, ktsb_pa); | |
2116 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
0785a8e8 DM |
2117 | { |
2118 | extern unsigned int __swapper_4m_tsb_phys_patch; | |
2119 | extern unsigned int __swapper_4m_tsb_phys_patch_end; | |
9076d0e7 DM |
2120 | ktsb_pa = (kern_base + |
2121 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
2122 | patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch, | |
2123 | &__swapper_4m_tsb_phys_patch_end, ktsb_pa); | |
0785a8e8 | 2124 | } |
9076d0e7 DM |
2125 | #endif |
2126 | } | |
2127 | ||
490384e7 DM |
2128 | static void __init sun4v_ktsb_init(void) |
2129 | { | |
2130 | unsigned long ktsb_pa; | |
2131 | ||
d7744a09 | 2132 | /* First KTSB for PAGE_SIZE mappings. */ |
490384e7 DM |
2133 | ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE); |
2134 | ||
2135 | switch (PAGE_SIZE) { | |
2136 | case 8 * 1024: | |
2137 | default: | |
2138 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K; | |
2139 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K; | |
2140 | break; | |
2141 | ||
2142 | case 64 * 1024: | |
2143 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K; | |
2144 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K; | |
2145 | break; | |
2146 | ||
2147 | case 512 * 1024: | |
2148 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K; | |
2149 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K; | |
2150 | break; | |
2151 | ||
2152 | case 4 * 1024 * 1024: | |
2153 | ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB; | |
2154 | ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB; | |
2155 | break; | |
6cb79b3f | 2156 | } |
490384e7 | 2157 | |
3f19a84e | 2158 | ktsb_descr[0].assoc = 1; |
490384e7 DM |
2159 | ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES; |
2160 | ktsb_descr[0].ctx_idx = 0; | |
2161 | ktsb_descr[0].tsb_base = ktsb_pa; | |
2162 | ktsb_descr[0].resv = 0; | |
2163 | ||
d1acb421 | 2164 | #ifndef CONFIG_DEBUG_PAGEALLOC |
4f93d21d | 2165 | /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */ |
d7744a09 DM |
2166 | ktsb_pa = (kern_base + |
2167 | ((unsigned long)&swapper_4m_tsb[0] - KERNBASE)); | |
2168 | ||
2169 | ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB; | |
c69ad0a3 DM |
2170 | ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB | |
2171 | HV_PGSZ_MASK_256MB | | |
2172 | HV_PGSZ_MASK_2GB | | |
2173 | HV_PGSZ_MASK_16GB) & | |
2174 | cpu_pgsz_mask); | |
d7744a09 DM |
2175 | ktsb_descr[1].assoc = 1; |
2176 | ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES; | |
2177 | ktsb_descr[1].ctx_idx = 0; | |
2178 | ktsb_descr[1].tsb_base = ktsb_pa; | |
2179 | ktsb_descr[1].resv = 0; | |
d1acb421 | 2180 | #endif |
490384e7 DM |
2181 | } |
2182 | ||
2066aadd | 2183 | void sun4v_ktsb_register(void) |
490384e7 | 2184 | { |
7db35f31 | 2185 | unsigned long pa, ret; |
490384e7 DM |
2186 | |
2187 | pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE); | |
2188 | ||
7db35f31 DM |
2189 | ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa); |
2190 | if (ret != 0) { | |
2191 | prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: " | |
2192 | "errors with %lx\n", pa, ret); | |
2193 | prom_halt(); | |
2194 | } | |
490384e7 DM |
2195 | } |
2196 | ||
c69ad0a3 DM |
2197 | static void __init sun4u_linear_pte_xor_finalize(void) |
2198 | { | |
2199 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
2200 | /* This is where we would add Panther support for | |
2201 | * 32MB and 256MB pages. | |
2202 | */ | |
2203 | #endif | |
2204 | } | |
2205 | ||
2206 | static void __init sun4v_linear_pte_xor_finalize(void) | |
2207 | { | |
494e5b6f KA |
2208 | unsigned long pagecv_flag; |
2209 | ||
2210 | /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead | |
2211 | * enables MCD error. Do not set bit 9 on M7 processor. | |
2212 | */ | |
2213 | switch (sun4v_chip_type) { | |
2214 | case SUN4V_CHIP_SPARC_M7: | |
7d484acb | 2215 | case SUN4V_CHIP_SPARC_M8: |
c5b8b5be | 2216 | case SUN4V_CHIP_SPARC_SN: |
494e5b6f KA |
2217 | pagecv_flag = 0x00; |
2218 | break; | |
2219 | default: | |
2220 | pagecv_flag = _PAGE_CV_4V; | |
2221 | break; | |
2222 | } | |
c69ad0a3 DM |
2223 | #ifndef CONFIG_DEBUG_PAGEALLOC |
2224 | if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) { | |
2225 | kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^ | |
922631b9 | 2226 | PAGE_OFFSET; |
494e5b6f | 2227 | kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag | |
c69ad0a3 DM |
2228 | _PAGE_P_4V | _PAGE_W_4V); |
2229 | } else { | |
2230 | kern_linear_pte_xor[1] = kern_linear_pte_xor[0]; | |
2231 | } | |
2232 | ||
2233 | if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) { | |
2234 | kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^ | |
922631b9 | 2235 | PAGE_OFFSET; |
494e5b6f | 2236 | kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag | |
c69ad0a3 DM |
2237 | _PAGE_P_4V | _PAGE_W_4V); |
2238 | } else { | |
2239 | kern_linear_pte_xor[2] = kern_linear_pte_xor[1]; | |
2240 | } | |
2241 | ||
2242 | if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) { | |
2243 | kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^ | |
922631b9 | 2244 | PAGE_OFFSET; |
494e5b6f | 2245 | kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag | |
c69ad0a3 DM |
2246 | _PAGE_P_4V | _PAGE_W_4V); |
2247 | } else { | |
2248 | kern_linear_pte_xor[3] = kern_linear_pte_xor[2]; | |
2249 | } | |
2250 | #endif | |
2251 | } | |
2252 | ||
1da177e4 LT |
2253 | /* paging_init() sets up the page tables */ |
2254 | ||
1da177e4 | 2255 | static unsigned long last_valid_pfn; |
ac55c768 | 2256 | |
c4bce90e DM |
2257 | static void sun4u_pgprot_init(void); |
2258 | static void sun4v_pgprot_init(void); | |
2259 | ||
7c21d533 | 2260 | static phys_addr_t __init available_memory(void) |
2261 | { | |
2262 | phys_addr_t available = 0ULL; | |
2263 | phys_addr_t pa_start, pa_end; | |
2264 | u64 i; | |
2265 | ||
fc6daaf9 TL |
2266 | for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, |
2267 | &pa_end, NULL) | |
7c21d533 | 2268 | available = available + (pa_end - pa_start); |
2269 | ||
2270 | return available; | |
2271 | } | |
2272 | ||
494e5b6f KA |
2273 | #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U) |
2274 | #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V) | |
2275 | #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U) | |
2276 | #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V) | |
2277 | #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R) | |
2278 | #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R) | |
2279 | ||
7c21d533 | 2280 | /* We need to exclude reserved regions. This exclusion will include |
2281 | * vmlinux and initrd. To be more precise the initrd size could be used to | |
2282 | * compute a new lower limit because it is freed later during initialization. | |
2283 | */ | |
2284 | static void __init reduce_memory(phys_addr_t limit_ram) | |
2285 | { | |
2286 | phys_addr_t avail_ram = available_memory(); | |
2287 | phys_addr_t pa_start, pa_end; | |
2288 | u64 i; | |
2289 | ||
2290 | if (limit_ram >= avail_ram) | |
2291 | return; | |
2292 | ||
fc6daaf9 TL |
2293 | for_each_free_mem_range(i, NUMA_NO_NODE, MEMBLOCK_NONE, &pa_start, |
2294 | &pa_end, NULL) { | |
7c21d533 | 2295 | phys_addr_t region_size = pa_end - pa_start; |
2296 | phys_addr_t clip_start = pa_start; | |
2297 | ||
2298 | avail_ram = avail_ram - region_size; | |
2299 | /* Are we consuming too much? */ | |
2300 | if (avail_ram < limit_ram) { | |
2301 | phys_addr_t give_back = limit_ram - avail_ram; | |
2302 | ||
2303 | region_size = region_size - give_back; | |
2304 | clip_start = clip_start + give_back; | |
2305 | } | |
2306 | ||
2307 | memblock_remove(clip_start, region_size); | |
2308 | ||
2309 | if (avail_ram <= limit_ram) | |
2310 | break; | |
2311 | i = 0UL; | |
2312 | } | |
2313 | } | |
2314 | ||
1da177e4 LT |
2315 | void __init paging_init(void) |
2316 | { | |
919ee677 | 2317 | unsigned long end_pfn, shift, phys_base; |
0836a0eb DM |
2318 | unsigned long real_end, i; |
2319 | ||
b2d43834 DM |
2320 | setup_page_offset(); |
2321 | ||
22adb358 DM |
2322 | /* These build time checkes make sure that the dcache_dirty_cpu() |
2323 | * page->flags usage will work. | |
2324 | * | |
2325 | * When a page gets marked as dcache-dirty, we store the | |
2326 | * cpu number starting at bit 32 in the page->flags. Also, | |
2327 | * functions like clear_dcache_dirty_cpu use the cpu mask | |
2328 | * in 13-bit signed-immediate instruction fields. | |
2329 | */ | |
9223b419 CL |
2330 | |
2331 | /* | |
2332 | * Page flags must not reach into upper 32 bits that are used | |
2333 | * for the cpu number | |
2334 | */ | |
2335 | BUILD_BUG_ON(NR_PAGEFLAGS > 32); | |
2336 | ||
2337 | /* | |
2338 | * The bit fields placed in the high range must not reach below | |
2339 | * the 32 bit boundary. Otherwise we cannot place the cpu field | |
2340 | * at the 32 bit boundary. | |
2341 | */ | |
22adb358 | 2342 | BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH + |
9223b419 CL |
2343 | ilog2(roundup_pow_of_two(NR_CPUS)) > 32); |
2344 | ||
22adb358 DM |
2345 | BUILD_BUG_ON(NR_CPUS > 4096); |
2346 | ||
0eef331a | 2347 | kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB; |
481295f9 DM |
2348 | kern_size = (unsigned long)&_end - (unsigned long)KERNBASE; |
2349 | ||
d7744a09 | 2350 | /* Invalidate both kernel TSBs. */ |
8b234274 | 2351 | memset(swapper_tsb, 0x40, sizeof(swapper_tsb)); |
d1acb421 | 2352 | #ifndef CONFIG_DEBUG_PAGEALLOC |
d7744a09 | 2353 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); |
d1acb421 | 2354 | #endif |
8b234274 | 2355 | |
494e5b6f KA |
2356 | /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde |
2357 | * bit on M7 processor. This is a conflicting usage of the same | |
2358 | * bit. Enabling TTE.cv on M7 would turn on Memory Corruption | |
2359 | * Detection error on all pages and this will lead to problems | |
2360 | * later. Kernel does not run with MCD enabled and hence rest | |
2361 | * of the required steps to fully configure memory corruption | |
2362 | * detection are not taken. We need to ensure TTE.mcde is not | |
2363 | * set on M7 processor. Compute the value of cacheability | |
2364 | * flag for use later taking this into consideration. | |
2365 | */ | |
2366 | switch (sun4v_chip_type) { | |
2367 | case SUN4V_CHIP_SPARC_M7: | |
7d484acb | 2368 | case SUN4V_CHIP_SPARC_M8: |
c5b8b5be | 2369 | case SUN4V_CHIP_SPARC_SN: |
494e5b6f KA |
2370 | page_cache4v_flag = _PAGE_CP_4V; |
2371 | break; | |
2372 | default: | |
2373 | page_cache4v_flag = _PAGE_CACHE_4V; | |
2374 | break; | |
2375 | } | |
2376 | ||
c4bce90e DM |
2377 | if (tlb_type == hypervisor) |
2378 | sun4v_pgprot_init(); | |
2379 | else | |
2380 | sun4u_pgprot_init(); | |
2381 | ||
d257d5da | 2382 | if (tlb_type == cheetah_plus || |
9076d0e7 | 2383 | tlb_type == hypervisor) { |
517af332 | 2384 | tsb_phys_patch(); |
9076d0e7 DM |
2385 | ktsb_phys_patch(); |
2386 | } | |
517af332 | 2387 | |
c69ad0a3 | 2388 | if (tlb_type == hypervisor) |
d257d5da DM |
2389 | sun4v_patch_tlb_handlers(); |
2390 | ||
a94a172d DM |
2391 | /* Find available physical memory... |
2392 | * | |
2393 | * Read it twice in order to work around a bug in openfirmware. | |
2394 | * The call to grab this table itself can cause openfirmware to | |
2395 | * allocate memory, which in turn can take away some space from | |
2396 | * the list of available memory. Reading it twice makes sure | |
2397 | * we really do get the final value. | |
2398 | */ | |
2399 | read_obp_translations(); | |
2400 | read_obp_memory("reg", &pall[0], &pall_ents); | |
2401 | read_obp_memory("available", &pavail[0], &pavail_ents); | |
13edad7a | 2402 | read_obp_memory("available", &pavail[0], &pavail_ents); |
0836a0eb DM |
2403 | |
2404 | phys_base = 0xffffffffffffffffUL; | |
3b2a7e23 | 2405 | for (i = 0; i < pavail_ents; i++) { |
13edad7a | 2406 | phys_base = min(phys_base, pavail[i].phys_addr); |
95f72d1e | 2407 | memblock_add(pavail[i].phys_addr, pavail[i].reg_size); |
3b2a7e23 DM |
2408 | } |
2409 | ||
95f72d1e | 2410 | memblock_reserve(kern_base, kern_size); |
0836a0eb | 2411 | |
4e82c9a6 DM |
2412 | find_ramdisk(phys_base); |
2413 | ||
7c21d533 | 2414 | if (cmdline_memory_size) |
2415 | reduce_memory(cmdline_memory_size); | |
25b0c659 | 2416 | |
1aadc056 | 2417 | memblock_allow_resize(); |
95f72d1e | 2418 | memblock_dump_all(); |
3b2a7e23 | 2419 | |
1da177e4 LT |
2420 | set_bit(0, mmu_context_bmap); |
2421 | ||
2bdb3cb2 DM |
2422 | shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE); |
2423 | ||
1da177e4 | 2424 | real_end = (unsigned long)_end; |
0eef331a | 2425 | num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB); |
64658743 DM |
2426 | printk("Kernel: Using %d locked TLB entries for main kernel image.\n", |
2427 | num_kernel_image_mappings); | |
2bdb3cb2 DM |
2428 | |
2429 | /* Set kernel pgd to upper alias so physical page computations | |
1da177e4 LT |
2430 | * work. |
2431 | */ | |
2432 | init_mm.pgd += ((shift) / (sizeof(pgd_t))); | |
2433 | ||
d195b71b | 2434 | memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir)); |
0dd5b7b0 | 2435 | |
c9c10830 | 2436 | inherit_prom_mappings(); |
5085b4a5 | 2437 | |
a8b900d8 DM |
2438 | /* Ok, we can use our TLB miss and window trap handlers safely. */ |
2439 | setup_tba(); | |
1da177e4 | 2440 | |
c9c10830 | 2441 | __flush_tlb_all(); |
9ad98c5b | 2442 | |
ad072004 | 2443 | prom_build_devicetree(); |
b696fdc2 | 2444 | of_populate_present_mask(); |
b99c6ebe DM |
2445 | #ifndef CONFIG_SMP |
2446 | of_fill_in_cpu_data(); | |
2447 | #endif | |
ad072004 | 2448 | |
890db403 | 2449 | if (tlb_type == hypervisor) { |
4a283339 | 2450 | sun4v_mdesc_init(); |
6ac5c610 | 2451 | mdesc_populate_present_mask(cpu_all_mask); |
b99c6ebe DM |
2452 | #ifndef CONFIG_SMP |
2453 | mdesc_fill_in_cpu_data(cpu_all_mask); | |
2454 | #endif | |
ce33fdc5 | 2455 | mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask); |
c69ad0a3 DM |
2456 | |
2457 | sun4v_linear_pte_xor_finalize(); | |
2458 | ||
2459 | sun4v_ktsb_init(); | |
2460 | sun4v_ktsb_register(); | |
ce33fdc5 DM |
2461 | } else { |
2462 | unsigned long impl, ver; | |
2463 | ||
2464 | cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K | | |
2465 | HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB); | |
2466 | ||
2467 | __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver)); | |
2468 | impl = ((ver >> 32) & 0xffff); | |
2469 | if (impl == PANTHER_IMPL) | |
2470 | cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB | | |
2471 | HV_PGSZ_MASK_256MB); | |
c69ad0a3 DM |
2472 | |
2473 | sun4u_linear_pte_xor_finalize(); | |
890db403 | 2474 | } |
4a283339 | 2475 | |
c69ad0a3 DM |
2476 | /* Flush the TLBs and the 4M TSB so that the updated linear |
2477 | * pte XOR settings are realized for all mappings. | |
2478 | */ | |
2479 | __flush_tlb_all(); | |
2480 | #ifndef CONFIG_DEBUG_PAGEALLOC | |
2481 | memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb)); | |
2482 | #endif | |
2483 | __flush_tlb_all(); | |
2484 | ||
5ed56f1a DM |
2485 | /* Setup bootmem... */ |
2486 | last_valid_pfn = end_pfn = bootmem_init(phys_base); | |
2487 | ||
56425306 | 2488 | kernel_physical_mapping_init(); |
56425306 | 2489 | |
1da177e4 | 2490 | { |
919ee677 | 2491 | unsigned long max_zone_pfns[MAX_NR_ZONES]; |
1da177e4 | 2492 | |
919ee677 | 2493 | memset(max_zone_pfns, 0, sizeof(max_zone_pfns)); |
1da177e4 | 2494 | |
919ee677 | 2495 | max_zone_pfns[ZONE_NORMAL] = end_pfn; |
1da177e4 | 2496 | |
919ee677 | 2497 | free_area_init_nodes(max_zone_pfns); |
1da177e4 LT |
2498 | } |
2499 | ||
3c62a2d3 | 2500 | printk("Booting Linux...\n"); |
1da177e4 LT |
2501 | } |
2502 | ||
7c9503b8 | 2503 | int page_in_phys_avail(unsigned long paddr) |
919ee677 DM |
2504 | { |
2505 | int i; | |
2506 | ||
2507 | paddr &= PAGE_MASK; | |
2508 | ||
2509 | for (i = 0; i < pavail_ents; i++) { | |
2510 | unsigned long start, end; | |
2511 | ||
2512 | start = pavail[i].phys_addr; | |
2513 | end = start + pavail[i].reg_size; | |
2514 | ||
2515 | if (paddr >= start && paddr < end) | |
2516 | return 1; | |
2517 | } | |
2518 | if (paddr >= kern_base && paddr < (kern_base + kern_size)) | |
2519 | return 1; | |
2520 | #ifdef CONFIG_BLK_DEV_INITRD | |
2521 | if (paddr >= __pa(initrd_start) && | |
2522 | paddr < __pa(PAGE_ALIGN(initrd_end))) | |
2523 | return 1; | |
2524 | #endif | |
2525 | ||
2526 | return 0; | |
2527 | } | |
2528 | ||
961f8fa0 YL |
2529 | static void __init register_page_bootmem_info(void) |
2530 | { | |
2531 | #ifdef CONFIG_NEED_MULTIPLE_NODES | |
2532 | int i; | |
2533 | ||
2534 | for_each_online_node(i) | |
2535 | if (NODE_DATA(i)->node_spanned_pages) | |
2536 | register_page_bootmem_info_node(NODE_DATA(i)); | |
2537 | #endif | |
2538 | } | |
1da177e4 LT |
2539 | void __init mem_init(void) |
2540 | { | |
1da177e4 LT |
2541 | high_memory = __va(last_valid_pfn << PAGE_SHIFT); |
2542 | ||
961f8fa0 | 2543 | register_page_bootmem_info(); |
0c988534 | 2544 | free_all_bootmem(); |
919ee677 | 2545 | |
1da177e4 LT |
2546 | /* |
2547 | * Set up the zero page, mark it reserved, so that page count | |
2548 | * is not manipulated when freeing the page from user ptes. | |
2549 | */ | |
2550 | mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0); | |
2551 | if (mem_map_zero == NULL) { | |
2552 | prom_printf("paging_init: Cannot alloc zero page.\n"); | |
2553 | prom_halt(); | |
2554 | } | |
70affe45 | 2555 | mark_page_reserved(mem_map_zero); |
1da177e4 | 2556 | |
dceccbe9 | 2557 | mem_init_print_info(NULL); |
1da177e4 LT |
2558 | |
2559 | if (tlb_type == cheetah || tlb_type == cheetah_plus) | |
2560 | cheetah_ecache_flush_init(); | |
2561 | } | |
2562 | ||
898cf0ec | 2563 | void free_initmem(void) |
1da177e4 LT |
2564 | { |
2565 | unsigned long addr, initend; | |
f2b60794 DM |
2566 | int do_free = 1; |
2567 | ||
2568 | /* If the physical memory maps were trimmed by kernel command | |
2569 | * line options, don't even try freeing this initmem stuff up. | |
2570 | * The kernel image could have been in the trimmed out region | |
2571 | * and if so the freeing below will free invalid page structs. | |
2572 | */ | |
2573 | if (cmdline_memory_size) | |
2574 | do_free = 0; | |
1da177e4 LT |
2575 | |
2576 | /* | |
2577 | * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes. | |
2578 | */ | |
2579 | addr = PAGE_ALIGN((unsigned long)(__init_begin)); | |
2580 | initend = (unsigned long)(__init_end) & PAGE_MASK; | |
2581 | for (; addr < initend; addr += PAGE_SIZE) { | |
2582 | unsigned long page; | |
1da177e4 LT |
2583 | |
2584 | page = (addr + | |
2585 | ((unsigned long) __va(kern_base)) - | |
2586 | ((unsigned long) KERNBASE)); | |
c9cf5528 | 2587 | memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE); |
1da177e4 | 2588 | |
70affe45 JL |
2589 | if (do_free) |
2590 | free_reserved_page(virt_to_page(page)); | |
1da177e4 LT |
2591 | } |
2592 | } | |
2593 | ||
2594 | #ifdef CONFIG_BLK_DEV_INITRD | |
2595 | void free_initrd_mem(unsigned long start, unsigned long end) | |
2596 | { | |
dceccbe9 JL |
2597 | free_reserved_area((void *)start, (void *)end, POISON_FREE_INITMEM, |
2598 | "initrd"); | |
1da177e4 LT |
2599 | } |
2600 | #endif | |
c4bce90e | 2601 | |
c4bce90e DM |
2602 | pgprot_t PAGE_KERNEL __read_mostly; |
2603 | EXPORT_SYMBOL(PAGE_KERNEL); | |
2604 | ||
2605 | pgprot_t PAGE_KERNEL_LOCKED __read_mostly; | |
2606 | pgprot_t PAGE_COPY __read_mostly; | |
0f15952a DM |
2607 | |
2608 | pgprot_t PAGE_SHARED __read_mostly; | |
2609 | EXPORT_SYMBOL(PAGE_SHARED); | |
2610 | ||
c4bce90e DM |
2611 | unsigned long pg_iobits __read_mostly; |
2612 | ||
2613 | unsigned long _PAGE_IE __read_mostly; | |
987c74fc | 2614 | EXPORT_SYMBOL(_PAGE_IE); |
b2bef442 | 2615 | |
c4bce90e | 2616 | unsigned long _PAGE_E __read_mostly; |
b2bef442 DM |
2617 | EXPORT_SYMBOL(_PAGE_E); |
2618 | ||
c4bce90e | 2619 | unsigned long _PAGE_CACHE __read_mostly; |
b2bef442 | 2620 | EXPORT_SYMBOL(_PAGE_CACHE); |
c4bce90e | 2621 | |
46644c24 | 2622 | #ifdef CONFIG_SPARSEMEM_VMEMMAP |
0aad818b JW |
2623 | int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend, |
2624 | int node) | |
46644c24 | 2625 | { |
46644c24 DM |
2626 | unsigned long pte_base; |
2627 | ||
2628 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2629 | _PAGE_CP_4U | _PAGE_CV_4U | | |
2630 | _PAGE_P_4U | _PAGE_W_4U); | |
2631 | if (tlb_type == hypervisor) | |
2632 | pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
494e5b6f | 2633 | page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V); |
46644c24 | 2634 | |
c06240c7 | 2635 | pte_base |= _PAGE_PMD_HUGE; |
46644c24 | 2636 | |
c06240c7 DM |
2637 | vstart = vstart & PMD_MASK; |
2638 | vend = ALIGN(vend, PMD_SIZE); | |
2639 | for (; vstart < vend; vstart += PMD_SIZE) { | |
2640 | pgd_t *pgd = pgd_offset_k(vstart); | |
2641 | unsigned long pte; | |
2642 | pud_t *pud; | |
2643 | pmd_t *pmd; | |
2644 | ||
2645 | if (pgd_none(*pgd)) { | |
2646 | pud_t *new = vmemmap_alloc_block(PAGE_SIZE, node); | |
2647 | ||
2648 | if (!new) | |
46644c24 | 2649 | return -ENOMEM; |
c06240c7 DM |
2650 | pgd_populate(&init_mm, pgd, new); |
2651 | } | |
46644c24 | 2652 | |
c06240c7 DM |
2653 | pud = pud_offset(pgd, vstart); |
2654 | if (pud_none(*pud)) { | |
2655 | pmd_t *new = vmemmap_alloc_block(PAGE_SIZE, node); | |
46644c24 | 2656 | |
c06240c7 DM |
2657 | if (!new) |
2658 | return -ENOMEM; | |
2659 | pud_populate(&init_mm, pud, new); | |
46644c24 | 2660 | } |
2856cc2e | 2661 | |
c06240c7 DM |
2662 | pmd = pmd_offset(pud, vstart); |
2663 | ||
2664 | pte = pmd_val(*pmd); | |
2665 | if (!(pte & _PAGE_VALID)) { | |
2666 | void *block = vmemmap_alloc_block(PMD_SIZE, node); | |
2667 | ||
2668 | if (!block) | |
2669 | return -ENOMEM; | |
2670 | ||
2671 | pmd_val(*pmd) = pte_base | __pa(block); | |
2672 | } | |
2856cc2e | 2673 | } |
c06240c7 DM |
2674 | |
2675 | return 0; | |
2856cc2e | 2676 | } |
46723bfa | 2677 | |
0aad818b | 2678 | void vmemmap_free(unsigned long start, unsigned long end) |
0197518c TC |
2679 | { |
2680 | } | |
46644c24 DM |
2681 | #endif /* CONFIG_SPARSEMEM_VMEMMAP */ |
2682 | ||
c4bce90e DM |
2683 | static void prot_init_common(unsigned long page_none, |
2684 | unsigned long page_shared, | |
2685 | unsigned long page_copy, | |
2686 | unsigned long page_readonly, | |
2687 | unsigned long page_exec_bit) | |
2688 | { | |
2689 | PAGE_COPY = __pgprot(page_copy); | |
0f15952a | 2690 | PAGE_SHARED = __pgprot(page_shared); |
c4bce90e DM |
2691 | |
2692 | protection_map[0x0] = __pgprot(page_none); | |
2693 | protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit); | |
2694 | protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit); | |
2695 | protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit); | |
2696 | protection_map[0x4] = __pgprot(page_readonly); | |
2697 | protection_map[0x5] = __pgprot(page_readonly); | |
2698 | protection_map[0x6] = __pgprot(page_copy); | |
2699 | protection_map[0x7] = __pgprot(page_copy); | |
2700 | protection_map[0x8] = __pgprot(page_none); | |
2701 | protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit); | |
2702 | protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit); | |
2703 | protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit); | |
2704 | protection_map[0xc] = __pgprot(page_readonly); | |
2705 | protection_map[0xd] = __pgprot(page_readonly); | |
2706 | protection_map[0xe] = __pgprot(page_shared); | |
2707 | protection_map[0xf] = __pgprot(page_shared); | |
2708 | } | |
2709 | ||
2710 | static void __init sun4u_pgprot_init(void) | |
2711 | { | |
2712 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2713 | unsigned long page_exec_bit; | |
4f93d21d | 2714 | int i; |
c4bce90e DM |
2715 | |
2716 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2717 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2718 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2719 | _PAGE_EXEC_4U); | |
2720 | PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID | | |
2721 | _PAGE_CACHE_4U | _PAGE_P_4U | | |
2722 | __ACCESS_BITS_4U | __DIRTY_BITS_4U | | |
2723 | _PAGE_EXEC_4U | _PAGE_L_4U); | |
c4bce90e DM |
2724 | |
2725 | _PAGE_IE = _PAGE_IE_4U; | |
2726 | _PAGE_E = _PAGE_E_4U; | |
2727 | _PAGE_CACHE = _PAGE_CACHE_4U; | |
2728 | ||
2729 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U | | |
2730 | __ACCESS_BITS_4U | _PAGE_E_4U); | |
2731 | ||
d1acb421 | 2732 | #ifdef CONFIG_DEBUG_PAGEALLOC |
922631b9 | 2733 | kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; |
d1acb421 | 2734 | #else |
9cc3a1ac | 2735 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^ |
922631b9 | 2736 | PAGE_OFFSET; |
d1acb421 | 2737 | #endif |
9cc3a1ac DM |
2738 | kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U | |
2739 | _PAGE_P_4U | _PAGE_W_4U); | |
2740 | ||
4f93d21d DM |
2741 | for (i = 1; i < 4; i++) |
2742 | kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; | |
c4bce90e | 2743 | |
c4bce90e DM |
2744 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U | |
2745 | _PAGE_SZ64K_4U | _PAGE_SZ8K_4U | | |
2746 | _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U); | |
2747 | ||
2748 | ||
2749 | page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U; | |
2750 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2751 | __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U); | |
2752 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2753 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2754 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U | | |
2755 | __ACCESS_BITS_4U | _PAGE_EXEC_4U); | |
2756 | ||
2757 | page_exec_bit = _PAGE_EXEC_4U; | |
2758 | ||
2759 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2760 | page_exec_bit); | |
2761 | } | |
2762 | ||
2763 | static void __init sun4v_pgprot_init(void) | |
2764 | { | |
2765 | unsigned long page_none, page_shared, page_copy, page_readonly; | |
2766 | unsigned long page_exec_bit; | |
4f93d21d | 2767 | int i; |
c4bce90e DM |
2768 | |
2769 | PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID | | |
494e5b6f | 2770 | page_cache4v_flag | _PAGE_P_4V | |
c4bce90e DM |
2771 | __ACCESS_BITS_4V | __DIRTY_BITS_4V | |
2772 | _PAGE_EXEC_4V); | |
2773 | PAGE_KERNEL_LOCKED = PAGE_KERNEL; | |
c4bce90e DM |
2774 | |
2775 | _PAGE_IE = _PAGE_IE_4V; | |
2776 | _PAGE_E = _PAGE_E_4V; | |
494e5b6f | 2777 | _PAGE_CACHE = page_cache4v_flag; |
c4bce90e | 2778 | |
d1acb421 | 2779 | #ifdef CONFIG_DEBUG_PAGEALLOC |
922631b9 | 2780 | kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET; |
d1acb421 | 2781 | #else |
9cc3a1ac | 2782 | kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^ |
922631b9 | 2783 | PAGE_OFFSET; |
d1acb421 | 2784 | #endif |
494e5b6f KA |
2785 | kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V | |
2786 | _PAGE_W_4V); | |
9cc3a1ac | 2787 | |
c69ad0a3 DM |
2788 | for (i = 1; i < 4; i++) |
2789 | kern_linear_pte_xor[i] = kern_linear_pte_xor[0]; | |
4f93d21d | 2790 | |
c4bce90e DM |
2791 | pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V | |
2792 | __ACCESS_BITS_4V | _PAGE_E_4V); | |
2793 | ||
c4bce90e DM |
2794 | _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V | |
2795 | _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V | | |
2796 | _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V | | |
2797 | _PAGE_SZ64K_4V | _PAGE_SZ8K_4V); | |
2798 | ||
494e5b6f KA |
2799 | page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag; |
2800 | page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | | |
c4bce90e | 2801 | __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V); |
494e5b6f | 2802 | page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | |
c4bce90e | 2803 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); |
494e5b6f | 2804 | page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag | |
c4bce90e DM |
2805 | __ACCESS_BITS_4V | _PAGE_EXEC_4V); |
2806 | ||
2807 | page_exec_bit = _PAGE_EXEC_4V; | |
2808 | ||
2809 | prot_init_common(page_none, page_shared, page_copy, page_readonly, | |
2810 | page_exec_bit); | |
2811 | } | |
2812 | ||
2813 | unsigned long pte_sz_bits(unsigned long sz) | |
2814 | { | |
2815 | if (tlb_type == hypervisor) { | |
2816 | switch (sz) { | |
2817 | case 8 * 1024: | |
2818 | default: | |
2819 | return _PAGE_SZ8K_4V; | |
2820 | case 64 * 1024: | |
2821 | return _PAGE_SZ64K_4V; | |
2822 | case 512 * 1024: | |
2823 | return _PAGE_SZ512K_4V; | |
2824 | case 4 * 1024 * 1024: | |
2825 | return _PAGE_SZ4MB_4V; | |
6cb79b3f | 2826 | } |
c4bce90e DM |
2827 | } else { |
2828 | switch (sz) { | |
2829 | case 8 * 1024: | |
2830 | default: | |
2831 | return _PAGE_SZ8K_4U; | |
2832 | case 64 * 1024: | |
2833 | return _PAGE_SZ64K_4U; | |
2834 | case 512 * 1024: | |
2835 | return _PAGE_SZ512K_4U; | |
2836 | case 4 * 1024 * 1024: | |
2837 | return _PAGE_SZ4MB_4U; | |
6cb79b3f | 2838 | } |
c4bce90e DM |
2839 | } |
2840 | } | |
2841 | ||
2842 | pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size) | |
2843 | { | |
2844 | pte_t pte; | |
cf627156 DM |
2845 | |
2846 | pte_val(pte) = page | pgprot_val(pgprot_noncached(prot)); | |
c4bce90e DM |
2847 | pte_val(pte) |= (((unsigned long)space) << 32); |
2848 | pte_val(pte) |= pte_sz_bits(page_size); | |
c4bce90e | 2849 | |
cf627156 | 2850 | return pte; |
c4bce90e DM |
2851 | } |
2852 | ||
2853 | static unsigned long kern_large_tte(unsigned long paddr) | |
2854 | { | |
2855 | unsigned long val; | |
2856 | ||
2857 | val = (_PAGE_VALID | _PAGE_SZ4MB_4U | | |
2858 | _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U | | |
2859 | _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U); | |
2860 | if (tlb_type == hypervisor) | |
2861 | val = (_PAGE_VALID | _PAGE_SZ4MB_4V | | |
494e5b6f | 2862 | page_cache4v_flag | _PAGE_P_4V | |
c4bce90e DM |
2863 | _PAGE_EXEC_4V | _PAGE_W_4V); |
2864 | ||
2865 | return val | paddr; | |
2866 | } | |
2867 | ||
c4bce90e DM |
2868 | /* If not locked, zap it. */ |
2869 | void __flush_tlb_all(void) | |
2870 | { | |
2871 | unsigned long pstate; | |
2872 | int i; | |
2873 | ||
2874 | __asm__ __volatile__("flushw\n\t" | |
2875 | "rdpr %%pstate, %0\n\t" | |
2876 | "wrpr %0, %1, %%pstate" | |
2877 | : "=r" (pstate) | |
2878 | : "i" (PSTATE_IE)); | |
8f361453 DM |
2879 | if (tlb_type == hypervisor) { |
2880 | sun4v_mmu_demap_all(); | |
2881 | } else if (tlb_type == spitfire) { | |
c4bce90e DM |
2882 | for (i = 0; i < 64; i++) { |
2883 | /* Spitfire Errata #32 workaround */ | |
2884 | /* NOTE: Always runs on spitfire, so no | |
2885 | * cheetah+ page size encodings. | |
2886 | */ | |
2887 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2888 | "flush %%g6" | |
2889 | : /* No outputs */ | |
2890 | : "r" (0), | |
2891 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2892 | ||
2893 | if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) { | |
2894 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2895 | "membar #Sync" | |
2896 | : /* no outputs */ | |
2897 | : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU)); | |
2898 | spitfire_put_dtlb_data(i, 0x0UL); | |
2899 | } | |
2900 | ||
2901 | /* Spitfire Errata #32 workaround */ | |
2902 | /* NOTE: Always runs on spitfire, so no | |
2903 | * cheetah+ page size encodings. | |
2904 | */ | |
2905 | __asm__ __volatile__("stxa %0, [%1] %2\n\t" | |
2906 | "flush %%g6" | |
2907 | : /* No outputs */ | |
2908 | : "r" (0), | |
2909 | "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU)); | |
2910 | ||
2911 | if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) { | |
2912 | __asm__ __volatile__("stxa %%g0, [%0] %1\n\t" | |
2913 | "membar #Sync" | |
2914 | : /* no outputs */ | |
2915 | : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU)); | |
2916 | spitfire_put_itlb_data(i, 0x0UL); | |
2917 | } | |
2918 | } | |
2919 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
2920 | cheetah_flush_dtlb_all(); | |
2921 | cheetah_flush_itlb_all(); | |
2922 | } | |
2923 | __asm__ __volatile__("wrpr %0, 0, %%pstate" | |
2924 | : : "r" (pstate)); | |
2925 | } | |
c460bec7 | 2926 | |
c460bec7 DM |
2927 | pte_t *pte_alloc_one_kernel(struct mm_struct *mm, |
2928 | unsigned long address) | |
2929 | { | |
32d6bd90 | 2930 | struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO); |
37b3a8ff | 2931 | pte_t *pte = NULL; |
c460bec7 | 2932 | |
c460bec7 DM |
2933 | if (page) |
2934 | pte = (pte_t *) page_address(page); | |
2935 | ||
2936 | return pte; | |
2937 | } | |
2938 | ||
2939 | pgtable_t pte_alloc_one(struct mm_struct *mm, | |
2940 | unsigned long address) | |
2941 | { | |
32d6bd90 | 2942 | struct page *page = alloc_page(GFP_KERNEL | __GFP_NOTRACK | __GFP_ZERO); |
1ae9ae5f KS |
2943 | if (!page) |
2944 | return NULL; | |
2945 | if (!pgtable_page_ctor(page)) { | |
2946 | free_hot_cold_page(page, 0); | |
2947 | return NULL; | |
c460bec7 | 2948 | } |
1ae9ae5f | 2949 | return (pte_t *) page_address(page); |
c460bec7 DM |
2950 | } |
2951 | ||
2952 | void pte_free_kernel(struct mm_struct *mm, pte_t *pte) | |
2953 | { | |
37b3a8ff | 2954 | free_page((unsigned long)pte); |
c460bec7 DM |
2955 | } |
2956 | ||
2957 | static void __pte_free(pgtable_t pte) | |
2958 | { | |
2959 | struct page *page = virt_to_page(pte); | |
37b3a8ff DM |
2960 | |
2961 | pgtable_page_dtor(page); | |
2962 | __free_page(page); | |
c460bec7 DM |
2963 | } |
2964 | ||
2965 | void pte_free(struct mm_struct *mm, pgtable_t pte) | |
2966 | { | |
2967 | __pte_free(pte); | |
2968 | } | |
2969 | ||
2970 | void pgtable_free(void *table, bool is_page) | |
2971 | { | |
2972 | if (is_page) | |
2973 | __pte_free(table); | |
2974 | else | |
2975 | kmem_cache_free(pgtable_cache, table); | |
2976 | } | |
9e695d2e DM |
2977 | |
2978 | #ifdef CONFIG_TRANSPARENT_HUGEPAGE | |
9e695d2e DM |
2979 | void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr, |
2980 | pmd_t *pmd) | |
2981 | { | |
2982 | unsigned long pte, flags; | |
2983 | struct mm_struct *mm; | |
2984 | pmd_t entry = *pmd; | |
9e695d2e DM |
2985 | |
2986 | if (!pmd_large(entry) || !pmd_young(entry)) | |
2987 | return; | |
2988 | ||
a7b9403f | 2989 | pte = pmd_val(entry); |
9e695d2e | 2990 | |
18f38132 DM |
2991 | /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */ |
2992 | if (!(pte & _PAGE_VALID)) | |
2993 | return; | |
2994 | ||
37b3a8ff DM |
2995 | /* We are fabricating 8MB pages using 4MB real hw pages. */ |
2996 | pte |= (addr & (1UL << REAL_HPAGE_SHIFT)); | |
9e695d2e DM |
2997 | |
2998 | mm = vma->vm_mm; | |
2999 | ||
3000 | spin_lock_irqsave(&mm->context.lock, flags); | |
3001 | ||
3002 | if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL) | |
37b3a8ff | 3003 | __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT, |
9e695d2e DM |
3004 | addr, pte); |
3005 | ||
3006 | spin_unlock_irqrestore(&mm->context.lock, flags); | |
3007 | } | |
3008 | #endif /* CONFIG_TRANSPARENT_HUGEPAGE */ | |
3009 | ||
3010 | #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE) | |
3011 | static void context_reload(void *__data) | |
3012 | { | |
3013 | struct mm_struct *mm = __data; | |
3014 | ||
3015 | if (mm == current->mm) | |
3016 | load_secondary_context(mm); | |
3017 | } | |
3018 | ||
0fbebed6 | 3019 | void hugetlb_setup(struct pt_regs *regs) |
9e695d2e | 3020 | { |
0fbebed6 DM |
3021 | struct mm_struct *mm = current->mm; |
3022 | struct tsb_config *tp; | |
9e695d2e | 3023 | |
70ffdb93 | 3024 | if (faulthandler_disabled() || !mm) { |
0fbebed6 DM |
3025 | const struct exception_table_entry *entry; |
3026 | ||
3027 | entry = search_exception_tables(regs->tpc); | |
3028 | if (entry) { | |
3029 | regs->tpc = entry->fixup; | |
3030 | regs->tnpc = regs->tpc + 4; | |
3031 | return; | |
3032 | } | |
3033 | pr_alert("Unexpected HugeTLB setup in atomic context.\n"); | |
3034 | die_if_kernel("HugeTSB in atomic", regs); | |
3035 | } | |
3036 | ||
3037 | tp = &mm->context.tsb_block[MM_TSB_HUGE]; | |
3038 | if (likely(tp->tsb == NULL)) | |
3039 | tsb_grow(mm, MM_TSB_HUGE, 0); | |
9e695d2e | 3040 | |
9e695d2e DM |
3041 | tsb_context_switch(mm); |
3042 | smp_tsb_sync(mm); | |
3043 | ||
3044 | /* On UltraSPARC-III+ and later, configure the second half of | |
3045 | * the Data-TLB for huge pages. | |
3046 | */ | |
3047 | if (tlb_type == cheetah_plus) { | |
9ea46abe | 3048 | bool need_context_reload = false; |
9e695d2e DM |
3049 | unsigned long ctx; |
3050 | ||
9ea46abe | 3051 | spin_lock_irq(&ctx_alloc_lock); |
9e695d2e DM |
3052 | ctx = mm->context.sparc64_ctx_val; |
3053 | ctx &= ~CTX_PGSZ_MASK; | |
3054 | ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT; | |
3055 | ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT; | |
3056 | ||
3057 | if (ctx != mm->context.sparc64_ctx_val) { | |
3058 | /* When changing the page size fields, we | |
3059 | * must perform a context flush so that no | |
3060 | * stale entries match. This flush must | |
3061 | * occur with the original context register | |
3062 | * settings. | |
3063 | */ | |
3064 | do_flush_tlb_mm(mm); | |
3065 | ||
3066 | /* Reload the context register of all processors | |
3067 | * also executing in this address space. | |
3068 | */ | |
3069 | mm->context.sparc64_ctx_val = ctx; | |
9ea46abe | 3070 | need_context_reload = true; |
9e695d2e | 3071 | } |
9ea46abe DM |
3072 | spin_unlock_irq(&ctx_alloc_lock); |
3073 | ||
3074 | if (need_context_reload) | |
3075 | on_each_cpu(context_reload, mm, 0); | |
9e695d2e DM |
3076 | } |
3077 | } | |
3078 | #endif | |
f6d4fb5c | 3079 | |
3080 | static struct resource code_resource = { | |
3081 | .name = "Kernel code", | |
35d98e93 | 3082 | .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM |
f6d4fb5c | 3083 | }; |
3084 | ||
3085 | static struct resource data_resource = { | |
3086 | .name = "Kernel data", | |
35d98e93 | 3087 | .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM |
f6d4fb5c | 3088 | }; |
3089 | ||
3090 | static struct resource bss_resource = { | |
3091 | .name = "Kernel bss", | |
35d98e93 | 3092 | .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM |
f6d4fb5c | 3093 | }; |
3094 | ||
3095 | static inline resource_size_t compute_kern_paddr(void *addr) | |
3096 | { | |
3097 | return (resource_size_t) (addr - KERNBASE + kern_base); | |
3098 | } | |
3099 | ||
3100 | static void __init kernel_lds_init(void) | |
3101 | { | |
3102 | code_resource.start = compute_kern_paddr(_text); | |
3103 | code_resource.end = compute_kern_paddr(_etext - 1); | |
3104 | data_resource.start = compute_kern_paddr(_etext); | |
3105 | data_resource.end = compute_kern_paddr(_edata - 1); | |
3106 | bss_resource.start = compute_kern_paddr(__bss_start); | |
3107 | bss_resource.end = compute_kern_paddr(_end - 1); | |
3108 | } | |
3109 | ||
3110 | static int __init report_memory(void) | |
3111 | { | |
3112 | int i; | |
3113 | struct resource *res; | |
3114 | ||
3115 | kernel_lds_init(); | |
3116 | ||
3117 | for (i = 0; i < pavail_ents; i++) { | |
3118 | res = kzalloc(sizeof(struct resource), GFP_KERNEL); | |
3119 | ||
3120 | if (!res) { | |
3121 | pr_warn("Failed to allocate source.\n"); | |
3122 | break; | |
3123 | } | |
3124 | ||
3125 | res->name = "System RAM"; | |
3126 | res->start = pavail[i].phys_addr; | |
3127 | res->end = pavail[i].phys_addr + pavail[i].reg_size - 1; | |
35d98e93 | 3128 | res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM; |
f6d4fb5c | 3129 | |
3130 | if (insert_resource(&iomem_resource, res) < 0) { | |
3131 | pr_warn("Resource insertion failed.\n"); | |
3132 | break; | |
3133 | } | |
3134 | ||
3135 | insert_resource(res, &code_resource); | |
3136 | insert_resource(res, &data_resource); | |
3137 | insert_resource(res, &bss_resource); | |
3138 | } | |
3139 | ||
3140 | return 0; | |
3141 | } | |
3c08158e | 3142 | arch_initcall(report_memory); |
e9011d08 | 3143 | |
4ca9a237 DM |
3144 | #ifdef CONFIG_SMP |
3145 | #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range | |
3146 | #else | |
3147 | #define do_flush_tlb_kernel_range __flush_tlb_kernel_range | |
3148 | #endif | |
3149 | ||
3150 | void flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
3151 | { | |
3152 | if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) { | |
3153 | if (start < LOW_OBP_ADDRESS) { | |
3154 | flush_tsb_kernel_range(start, LOW_OBP_ADDRESS); | |
3155 | do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS); | |
3156 | } | |
3157 | if (end > HI_OBP_ADDRESS) { | |
473ad7f4 DM |
3158 | flush_tsb_kernel_range(HI_OBP_ADDRESS, end); |
3159 | do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end); | |
4ca9a237 DM |
3160 | } |
3161 | } else { | |
3162 | flush_tsb_kernel_range(start, end); | |
3163 | do_flush_tlb_kernel_range(start, end); | |
3164 | } | |
3165 | } |