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[SPARC64]: Do not assume sun4v chips have load-twin/store-init support.
[mirror_ubuntu-hirsute-kernel.git] / arch / sparc64 / kernel / head.S
CommitLineData
1966287d 1/* head.S: Initial boot code for the Sparc64 port of Linux.
1da177e4 2 *
1966287d 3 * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
1da177e4 4 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
1966287d 5 * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
1da177e4
LT		 6 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
7 */
8
1da177e4
LT		 9#include <linux/version.h>
10#include <linux/errno.h>
951bc82c 11#include <linux/threads.h>
1966287d 12#include <linux/init.h>
1da177e4
LT		 13#include <asm/thread_info.h>
14#include <asm/asi.h>
15#include <asm/pstate.h>
16#include <asm/ptrace.h>
17#include <asm/spitfire.h>
18#include <asm/page.h>
19#include <asm/pgtable.h>
20#include <asm/errno.h>
21#include <asm/signal.h>
22#include <asm/processor.h>
23#include <asm/lsu.h>
24#include <asm/dcr.h>
25#include <asm/dcu.h>
26#include <asm/head.h>
27#include <asm/ttable.h>
28#include <asm/mmu.h>
56fb4df6 29#include <asm/cpudata.h>
1da177e4
LT		 30
31/* This section from from _start to sparc64_boot_end should fit into
c9c10830 32 * 0x0000000000404000 to 0x0000000000408000.
1da177e4 33 */
1da177e4
LT		 34 .text
35 .globl start, _start, stext, _stext
36_start:
37start:
38_stext:
39stext:
1da177e4
LT		 40! 0x0000000000404000
41 b sparc64_boot
42 flushw /* Flush register file. */
43
44/* This stuff has to be in sync with SILO and other potential boot loaders
45 * Fields should be kept upward compatible and whenever any change is made,
46 * HdrS version should be incremented.
47 */
48 .global root_flags, ram_flags, root_dev
49 .global sparc_ramdisk_image, sparc_ramdisk_size
50 .global sparc_ramdisk_image64
51
52 .ascii "HdrS"
53 .word LINUX_VERSION_CODE
54
55 /* History:
56 *
57 * 0x0300 : Supports being located at other than 0x4000
58 * 0x0202 : Supports kernel params string
59 * 0x0201 : Supports reboot_command
60 */
61 .half 0x0301 /* HdrS version */
62
63root_flags:
64 .half 1
65root_dev:
66 .half 0
67ram_flags:
68 .half 0
69sparc_ramdisk_image:
70 .word 0
71sparc_ramdisk_size:
72 .word 0
73 .xword reboot_command
74 .xword bootstr_info
75sparc_ramdisk_image64:
76 .xword 0
77 .word _end
78
bff06d55
DM		 79 /* PROM cif handler code address is in %o4. */
80sparc64_boot:
15f14834 81 mov %o4, %l7
bff06d55
DM		 82
83 /* We need to remap the kernel. Use position independant
84 * code to remap us to KERNBASE.
1da177e4 85 *
bff06d55
DM		 86 * SILO can invoke us with 32-bit address masking enabled,
87 * so make sure that's clear.
1da177e4 88 */
bff06d55
DM		 89 rdpr %pstate, %g1
90 andn %g1, PSTATE_AM, %g1
91 wrpr %g1, 0x0, %pstate
92 ba,a,pt %xcc, 1f
93
d82ace7d
DM		 94 .globl prom_finddev_name, prom_chosen_path, prom_root_node
95 .globl prom_getprop_name, prom_mmu_name, prom_peer_name
96 .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
bff06d55
DM		 97 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
98 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
99 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
6c70b6fc
DM		 100 .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
101 .globl is_sun4v, sun4v_chip_type
d82ace7d
DM		 102prom_peer_name:
103 .asciz "peer"
104prom_compatible_name:
105 .asciz "compatible"
bff06d55
DM		 106prom_finddev_name:
107 .asciz "finddevice"
108prom_chosen_path:
109 .asciz "/chosen"
6c70b6fc
DM		 110prom_cpu_path:
111 .asciz "/cpu"
bff06d55
DM		 112prom_getprop_name:
113 .asciz "getprop"
114prom_mmu_name:
115 .asciz "mmu"
116prom_callmethod_name:
117 .asciz "call-method"
118prom_translate_name:
119 .asciz "translate"
120prom_map_name:
121 .asciz "map"
122prom_unmap_name:
123 .asciz "unmap"
d82ace7d 124prom_sun4v_name:
6cebb520 125 .asciz "sun4v"
6c70b6fc
DM		 126prom_niagara_prefix:
127 .asciz "SUNW,UltraSPARC-T"
bff06d55 128 .align 4
d82ace7d
DM		 129prom_root_compatible:
130 .skip 64
6c70b6fc
DM		 131prom_cpu_compatible:
132 .skip 64
d82ace7d
DM		 133prom_root_node:
134 .word 0
bff06d55
DM		 135prom_mmu_ihandle_cache:
136 .word 0
137prom_boot_mapped_pc:
138 .word 0
139prom_boot_mapping_mode:
140 .word 0
141 .align 8
142prom_boot_mapping_phys_high:
143 .xword 0
144prom_boot_mapping_phys_low:
145 .xword 0
d82ace7d
DM		 146is_sun4v:
147 .word 0
6c70b6fc
DM		 148sun4v_chip_type:
149 .word SUN4V_CHIP_INVALID
bff06d55
DM		 1501:
151 rd %pc, %l0
d82ace7d
DM		 152
153 mov (1b - prom_peer_name), %l1
154 sub %l0, %l1, %l1
155 mov 0, %l2
156
157 /* prom_root_node = prom_peer(0) */
158 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
159 mov 1, %l3
160 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
161 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
162 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
163 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
164 call %l7
165 add %sp, (2047 + 128), %o0 ! argument array
166
167 ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
168 mov (1b - prom_root_node), %l1
169 sub %l0, %l1, %l1
170 stw %l4, [%l1]
171
172 mov (1b - prom_getprop_name), %l1
173 mov (1b - prom_compatible_name), %l2
174 mov (1b - prom_root_compatible), %l5
175 sub %l0, %l1, %l1
176 sub %l0, %l2, %l2
177 sub %l0, %l5, %l5
178
179 /* prom_getproperty(prom_root_node, "compatible",
180 * &prom_root_compatible, 64)
181 */
182 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
183 mov 4, %l3
184 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
185 mov 1, %l3
186 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
187 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
188 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
189 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
190 mov 64, %l3
191 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
192 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
193 call %l7
194 add %sp, (2047 + 128), %o0 ! argument array
195
bff06d55
DM		 196 mov (1b - prom_finddev_name), %l1
197 mov (1b - prom_chosen_path), %l2
198 mov (1b - prom_boot_mapped_pc), %l3
199 sub %l0, %l1, %l1
200 sub %l0, %l2, %l2
201 sub %l0, %l3, %l3
202 stw %l0, [%l3]
203 sub %sp, (192 + 128), %sp
204
205 /* chosen_node = prom_finddevice("/chosen") */
206 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
207 mov 1, %l3
208 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
209 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
210 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
211 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
212 call %l7
213 add %sp, (2047 + 128), %o0 ! argument array
214
215 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
216
217 mov (1b - prom_getprop_name), %l1
218 mov (1b - prom_mmu_name), %l2
219 mov (1b - prom_mmu_ihandle_cache), %l5
220 sub %l0, %l1, %l1
221 sub %l0, %l2, %l2
222 sub %l0, %l5, %l5
223
224 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
225 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
226 mov 4, %l3
227 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
228 mov 1, %l3
229 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
230 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
231 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
232 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
233 mov 4, %l3
234 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
235 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
236 call %l7
237 add %sp, (2047 + 128), %o0 ! argument array
238
239 mov (1b - prom_callmethod_name), %l1
240 mov (1b - prom_translate_name), %l2
241 sub %l0, %l1, %l1
242 sub %l0, %l2, %l2
243 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
244
245 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
246 mov 3, %l3
247 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
248 mov 5, %l3
249 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
250 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
251 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
b1b510aa
DM		 252 /* PAGE align */
253 srlx %l0, 13, %l3
254 sllx %l3, 13, %l3
bff06d55
DM		 255 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
256 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
257 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
258 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
259 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
260 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
261 call %l7
262 add %sp, (2047 + 128), %o0 ! argument array
263
264 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
265 mov (1b - prom_boot_mapping_mode), %l4
266 sub %l0, %l4, %l4
267 stw %l1, [%l4]
268 mov (1b - prom_boot_mapping_phys_high), %l4
269 sub %l0, %l4, %l4
270 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
271 stx %l2, [%l4 + 0x0]
272 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
b1b510aa
DM		 273 /* 4MB align */
274 srlx %l3, 22, %l3
275 sllx %l3, 22, %l3
bff06d55
DM		 276 stx %l3, [%l4 + 0x8]
277
278 /* Leave service as-is, "call-method" */
279 mov 7, %l3
280 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
281 mov 1, %l3
a8201c61 282 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
bff06d55
DM		 283 mov (1b - prom_map_name), %l3
284 sub %l0, %l3, %l3
285 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
286 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
287 mov -1, %l3
288 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
289 sethi %hi(8 * 1024 * 1024), %l3
290 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: size (8MB)
291 sethi %hi(KERNBASE), %l3
292 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
293 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
294 mov (1b - prom_boot_mapping_phys_low), %l3
295 sub %l0, %l3, %l3
296 ldx [%l3], %l3
297 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
298 call %l7
299 add %sp, (2047 + 128), %o0 ! argument array
300
301 add %sp, (192 + 128), %sp
302
d82ace7d
DM		 303 sethi %hi(prom_root_compatible), %g1
304 or %g1, %lo(prom_root_compatible), %g1
305 sethi %hi(prom_sun4v_name), %g7
306 or %g7, %lo(prom_sun4v_name), %g7
6cebb520 307 mov 5, %g3
6c70b6fc 30890: ldub [%g7], %g2
d82ace7d
DM		 309 ldub [%g1], %g4
310 cmp %g2, %g4
6c70b6fc 311 bne,pn %icc, 80f
d82ace7d
DM		 312 add %g7, 1, %g7
313 subcc %g3, 1, %g3
6c70b6fc 314 bne,pt %xcc, 90b
d82ace7d
DM		 315 add %g1, 1, %g1
316
317 sethi %hi(is_sun4v), %g1
318 or %g1, %lo(is_sun4v), %g1
319 mov 1, %g7
320 stw %g7, [%g1]
321
6c70b6fc
DM		 322 /* cpu_node = prom_finddevice("/cpu") */
323 mov (1b - prom_finddev_name), %l1
324 mov (1b - prom_cpu_path), %l2
325 sub %l0, %l1, %l1
326 sub %l0, %l2, %l2
327 sub %sp, (192 + 128), %sp
328
329 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
330 mov 1, %l3
331 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
332 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
333 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
334 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
335 call %l7
336 add %sp, (2047 + 128), %o0 ! argument array
337
338 ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
339
340 mov (1b - prom_getprop_name), %l1
341 mov (1b - prom_compatible_name), %l2
342 mov (1b - prom_cpu_compatible), %l5
343 sub %l0, %l1, %l1
344 sub %l0, %l2, %l2
345 sub %l0, %l5, %l5
346
347 /* prom_getproperty(cpu_node, "compatible",
348 * &prom_cpu_compatible, 64)
349 */
350 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
351 mov 4, %l3
352 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
353 mov 1, %l3
354 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
355 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
356 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
357 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
358 mov 64, %l3
359 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
360 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
361 call %l7
362 add %sp, (2047 + 128), %o0 ! argument array
363
364 add %sp, (192 + 128), %sp
365
366 sethi %hi(prom_cpu_compatible), %g1
367 or %g1, %lo(prom_cpu_compatible), %g1
368 sethi %hi(prom_niagara_prefix), %g7
369 or %g7, %lo(prom_niagara_prefix), %g7
370 mov 17, %g3
37190: ldub [%g7], %g2
372 ldub [%g1], %g4
373 cmp %g2, %g4
374 bne,pn %icc, 4f
375 add %g7, 1, %g7
376 subcc %g3, 1, %g3
377 bne,pt %xcc, 90b
378 add %g1, 1, %g1
379
380 sethi %hi(prom_cpu_compatible), %g1
381 or %g1, %lo(prom_cpu_compatible), %g1
382 ldub [%g1 + 17], %g2
383 cmp %g2, '1'
384 be,pt %xcc, 5f
385 mov SUN4V_CHIP_NIAGARA1, %g4
386 cmp %g2, '2'
387 be,pt %xcc, 5f
388 mov SUN4V_CHIP_NIAGARA2, %g4
3894:
390 mov SUN4V_CHIP_UNKNOWN, %g4
3915: sethi %hi(sun4v_chip_type), %g2
392 or %g2, %lo(sun4v_chip_type), %g2
393 stw %g4, [%g2]
394
39580:
d82ace7d 396 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
1da177e4
LT		 397 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
398 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
399 ba,pt %xcc, spitfire_boot
400 nop
401
402cheetah_plus_boot:
403 /* Preserve OBP chosen DCU and DCR register settings. */
404 ba,pt %xcc, cheetah_generic_boot
405 nop
406
407cheetah_boot:
408 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
409 wr %g1, %asr18
410
411 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
412 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
413 sllx %g7, 32, %g7
414 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
415 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
416 membar #Sync
417
418cheetah_generic_boot:
419 mov TSB_EXTENSION_P, %g3
420 stxa %g0, [%g3] ASI_DMMU
421 stxa %g0, [%g3] ASI_IMMU
422 membar #Sync
423
424 mov TSB_EXTENSION_S, %g3
425 stxa %g0, [%g3] ASI_DMMU
426 membar #Sync
427
428 mov TSB_EXTENSION_N, %g3
429 stxa %g0, [%g3] ASI_DMMU
430 stxa %g0, [%g3] ASI_IMMU
431 membar #Sync
432
bff06d55 433 ba,a,pt %xcc, jump_to_sun4u_init
1da177e4
LT		 434
435spitfire_boot:
436 /* Typically PROM has already enabled both MMU's and both on-chip
437 * caches, but we do it here anyway just to be paranoid.
438 */
439 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
440 stxa %g1, [%g0] ASI_LSU_CONTROL
441 membar #Sync
442
bff06d55 443jump_to_sun4u_init:
1da177e4
LT		 444 /*
445 * Make sure we are in privileged mode, have address masking,
446 * using the ordinary globals and have enabled floating
447 * point.
448 *
449 * Again, typically PROM has left %pil at 13 or similar, and
450 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
451 */
452 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
453 wr %g0, 0, %fprs
454
1da177e4
LT		 455 set sun4u_init, %g2
456 jmpl %g2 + %g0, %g0
457 nop
458
1966287d 459 .section .text.init.refok
1da177e4 460sun4u_init:
6cebb520
DM		 461 BRANCH_IF_SUN4V(g1, sun4v_init)
462
1da177e4 463 /* Set ctx 0 */
8b11bd12 464 mov PRIMARY_CONTEXT, %g7
6cebb520 465 stxa %g0, [%g7] ASI_DMMU
8b11bd12
DM		 466 membar #Sync
467
468 mov SECONDARY_CONTEXT, %g7
6cebb520
DM		 469 stxa %g0, [%g7] ASI_DMMU
470 membar #Sync
471
472 ba,pt %xcc, sun4u_continue
473 nop
8b11bd12 474
6cebb520
DM		 475sun4v_init:
476 /* Set ctx 0 */
477 mov PRIMARY_CONTEXT, %g7
8b11bd12 478 stxa %g0, [%g7] ASI_MMU
6cebb520 479 membar #Sync
1da177e4 480
6cebb520
DM		 481 mov SECONDARY_CONTEXT, %g7
482 stxa %g0, [%g7] ASI_MMU
483 membar #Sync
484 ba,pt %xcc, niagara_tlb_fixup
485 nop
1da177e4 486
6cebb520 487sun4u_continue:
d82ace7d 488 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
1da177e4
LT		 489
490 ba,pt %xcc, spitfire_tlb_fixup
491 nop
492
8591e302
DM		 493niagara_tlb_fixup:
494 mov 3, %g2 /* Set TLB type to hypervisor. */
495 sethi %hi(tlb_type), %g1
496 stw %g2, [%g1 + %lo(tlb_type)]
497
498 /* Patch copy/clear ops. */
6c70b6fc
DM		 499 sethi %hi(sun4v_chip_type), %g1
500 lduw [%g1 + %lo(sun4v_chip_type)], %g1
501 cmp %g1, SUN4V_CHIP_NIAGARA1
502 be,pt %xcc, niagara_patch
503 cmp %g1, SUN4V_CHIP_NIAGARA2
504 be,pt %xcc, niagara_patch
505 nop
506
507 call generic_patch_copyops
508 nop
509 call generic_patch_bzero
510 nop
511 call generic_patch_pageops
512 nop
513
514 ba,a,pt %xcc, 80f
515
516niagara_patch:
8591e302
DM		 517 call niagara_patch_copyops
518 nop
8ca2557c
DM		 519 call niagara_patch_bzero
520 nop
8591e302
DM		 521 call niagara_patch_pageops
522 nop
523
6c70b6fc 52480:
8591e302
DM		 525 /* Patch TLB/cache ops. */
526 call hypervisor_patch_cachetlbops
527 nop
528
d82ace7d
DM		 529 ba,pt %xcc, tlb_fixup_done
530 nop
531
1da177e4 532cheetah_tlb_fixup:
1da177e4
LT		 533 mov 2, %g2 /* Set TLB type to cheetah+. */
534 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
535
536 mov 1, %g2 /* Set TLB type to cheetah. */
537
5381: sethi %hi(tlb_type), %g1
539 stw %g2, [%g1 + %lo(tlb_type)]
540
0835ae0f 541 /* Patch copy/page operations to cheetah optimized versions. */
1da177e4
LT		 542 call cheetah_patch_copyops
543 nop
dbd2fdf5
DM		 544 call cheetah_patch_copy_page
545 nop
1da177e4
LT		 546 call cheetah_patch_cachetlbops
547 nop
548
549 ba,pt %xcc, tlb_fixup_done
550 nop
551
552spitfire_tlb_fixup:
1da177e4
LT		 553 /* Set TLB type to spitfire. */
554 mov 0, %g2
555 sethi %hi(tlb_type), %g1
556 stw %g2, [%g1 + %lo(tlb_type)]
557
558tlb_fixup_done:
559 sethi %hi(init_thread_union), %g6
560 or %g6, %lo(init_thread_union), %g6
561 ldx [%g6 + TI_TASK], %g4
562 mov %sp, %l6
1da177e4 563
1da177e4
LT		 564 wr %g0, ASI_P, %asi
565 mov 1, %g1
566 sllx %g1, THREAD_SHIFT, %g1
567 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
568 add %g6, %g1, %sp
569 mov 0, %fp
570
571 /* Set per-cpu pointer initially to zero, this makes
572 * the boot-cpu use the in-kernel-image per-cpu areas
573 * before setup_per_cpu_area() is invoked.
574 */
575 clr %g5
576
577 wrpr %g0, 0, %wstate
578 wrpr %g0, 0x0, %tl
579
580 /* Clear the bss */
581 sethi %hi(__bss_start), %o0
582 or %o0, %lo(__bss_start), %o0
583 sethi %hi(_end), %o1
584 or %o1, %lo(_end), %o1
585 call __bzero
586 sub %o1, %o0, %o1
587
10e26723
DM		 588#ifdef CONFIG_LOCKDEP
589 /* We have this call this super early, as even prom_init can grab
590 * spinlocks and thus call into the lockdep code.
591 */
592 call lockdep_init
593 nop
594#endif
595
1da177e4
LT		 596 mov %l6, %o1 ! OpenPROM stack
597 call prom_init
598 mov %l7, %o0 ! OpenPROM cif handler
599
951bc82c
DM		 600 /* Initialize current_thread_info()->cpu as early as possible.
601 * In order to do that accurately we have to patch up the get_cpuid()
602 * assembler sequences. And that, in turn, requires that we know
603 * if we are on a Starfire box or not. While we're here, patch up
604 * the sun4v sequences as well.
605 */
606 call check_if_starfire
607 nop
608 call per_cpu_patch
609 nop
610 call sun4v_patch
611 nop
612
613#ifdef CONFIG_SMP
614 call hard_smp_processor_id
615 nop
616 cmp %o0, NR_CPUS
617 blu,pt %xcc, 1f
618 nop
619 call boot_cpu_id_too_large
620 nop
621 /* Not reached... */
622
6231:
624#else
625 mov 0, %o0
626#endif
22adb358 627 sth %o0, [%g6 + TI_CPU]
951bc82c 628
1da177e4
LT		 629 /* Off we go.... */
630 call start_kernel
631 nop
632 /* Not reached... */
633
1966287d
DM		 634 .previous
635
5d8e1b18
DM		 636 /* This is meant to allow the sharing of this code between
637 * boot processor invocation (via setup_tba() below) and
638 * secondary processor startup (via trampoline.S). The
639 * former does use this code, the latter does not yet due
640 * to some complexities. That should be fixed up at some
641 * point.
c9c10830
DM		 642 *
643 * There used to be enormous complexity wrt. transferring
644 * over from the firwmare's trap table to the Linux kernel's.
645 * For example, there was a chicken & egg problem wrt. building
646 * the OBP page tables, yet needing to be on the Linux kernel
647 * trap table (to translate PAGE_OFFSET addresses) in order to
648 * do that.
649 *
650 * We now handle OBP tlb misses differently, via linear lookups
651 * into the prom_trans[] array. So that specific problem no
652 * longer exists. Yet, unfortunately there are still some issues
653 * preventing trampoline.S from using this code... ho hum.
5d8e1b18
DM		 654 */
655 .globl setup_trap_table
656setup_trap_table:
657 save %sp, -192, %sp
658
c9c10830 659 /* Force interrupts to be disabled. */
d8573e20
DM		 660 rdpr %pstate, %l0
661 andn %l0, PSTATE_IE, %o1
5d8e1b18 662 wrpr %o1, 0x0, %pstate
d8573e20 663 rdpr %pil, %l1
5d8e1b18 664 wrpr %g0, 15, %pil
1da177e4 665
c9c10830 666 /* Make the firmware call to jump over to the Linux trap table. */
12eaa328
DM		 667 sethi %hi(is_sun4v), %o0
668 lduw [%o0 + %lo(is_sun4v)], %o0
669 brz,pt %o0, 1f
670 nop
671
672 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
673 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
674 stxa %g2, [%g0] ASI_SCRATCHPAD
675
676 /* Compute physical address:
677 *
678 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
679 */
680 sethi %hi(KERNBASE), %g3
681 sub %g2, %g3, %g2
682 sethi %hi(kern_base), %g3
683 ldx [%g3 + %lo(kern_base)], %g3
684 add %g2, %g3, %o1
685
686 call prom_set_trap_table_sun4v
687 sethi %hi(sparc64_ttable_tl0), %o0
688
689 ba,pt %xcc, 2f
690 nop
691
6921: call prom_set_trap_table
5d8e1b18
DM		 693 sethi %hi(sparc64_ttable_tl0), %o0
694
695 /* Start using proper page size encodings in ctx register. */
12eaa328 6962: sethi %hi(sparc64_kern_pri_context), %g3
5d8e1b18 697 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
8b11bd12
DM		 698
699 mov PRIMARY_CONTEXT, %g1
700
701661: stxa %g2, [%g1] ASI_DMMU
702 .section .sun4v_1insn_patch, "ax"
703 .word 661b
704 stxa %g2, [%g1] ASI_MMU
705 .previous
706
5d8e1b18
DM		 707 membar #Sync
708
1da177e4
LT		 709 /* Kill PROM timer */
710 sethi %hi(0x80000000), %o2
711 sllx %o2, 32, %o2
712 wr %o2, 0, %tick_cmpr
713
d82ace7d
DM		 714 BRANCH_IF_SUN4V(o2, 1f)
715 BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
1da177e4
LT		 716
717 ba,pt %xcc, 2f
718 nop
719
720 /* Disable STICK_INT interrupts. */
7211:
722 sethi %hi(0x80000000), %o2
723 sllx %o2, 32, %o2
724 wr %o2, %asr25
725
1da177e4
LT		 7262:
727 wrpr %g0, %g0, %wstate
1da177e4
LT		 728
729 call init_irqwork_curcpu
730 nop
731
d8573e20
DM		 732 /* Now we can restore interrupt state. */
733 wrpr %l0, 0, %pstate
734 wrpr %l1, 0x0, %pil
5d8e1b18
DM		 735
736 ret
737 restore
738
739 .globl setup_tba
a8b900d8 740setup_tba:
5d8e1b18
DM		 741 save %sp, -192, %sp
742
743 /* The boot processor is the only cpu which invokes this
744 * routine, the other cpus set things up via trampoline.S.
745 * So save the OBP trap table address here.
746 */
747 rdpr %tba, %g7
748 sethi %hi(prom_tba), %o1
749 or %o1, %lo(prom_tba), %o1
750 stx %g7, [%o1]
751
752 call setup_trap_table
753 nop
1da177e4
LT		 754
755 ret
756 restore
c9c10830
DM		 757sparc64_boot_end:
758
c9c10830
DM		 759#include "etrap.S"
760#include "rtrap.S"
761#include "winfixup.S"
762#include "entry.S"
5b0c0572
DM		 763#include "sun4v_tlb_miss.S"
764#include "sun4v_ivec.S"
2d9e2763
DM		 765#include "ktlb.S"
766#include "tsb.S"
1da177e4
LT		 767
768/*
c9c10830 769 * The following skip makes sure the trap table in ttable.S is aligned
1da177e4 770 * on a 32K boundary as required by the v9 specs for TBA register.
2f7ee7c6
DM		 771 *
772 * We align to a 32K boundary, then we have the 32K kernel TSB,
2d9e2763 773 * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
1da177e4 774 */
c9c10830
DM		 7751:
776 .skip 0x4000 + _start - 1b
1da177e4 777
2d9e2763
DM		 778! 0x0000000000408000
779
2f7ee7c6
DM		 780 .globl swapper_tsb
781swapper_tsb:
782 .skip (32 * 1024)
1da177e4 783
2d9e2763
DM		 784 .globl swapper_4m_tsb
785swapper_4m_tsb:
786 .skip (64 * 1024)
787
788! 0x0000000000420000
1da177e4 789
2d9e2763
DM		 790 /* Some care needs to be exercised if you try to move the
791 * location of the trap table relative to other things. For
792 * one thing there are br* instructions in some of the
793 * trap table entires which branch back to code in ktlb.S
794 * Those instructions can only handle a signed 16-bit
795 * displacement.
796 *
797 * There is a binutils bug (bugzilla #4558) which causes
798 * the relocation overflow checks for such instructions to
799 * not be done correctly. So bintuils will not notice the
800 * error and will instead write junk into the relocation and
801 * you'll have an unbootable kernel.
802 */
1da177e4 803#include "ttable.S"
1da177e4 804
2d9e2763
DM		 805! 0x0000000000428000
806
074d82cf
DM		 807#include "systbls.S"
808
1da177e4
LT		 809 .data
810 .align 8
811 .globl prom_tba, tlb_type
812prom_tba: .xword 0
813tlb_type: .word 0 /* Must NOT end up in BSS */
814 .section ".fixup",#alloc,#execinstr
5fd29752
DM		 815
816 .globl __ret_efault, __retl_efault
1da177e4
LT		 817__ret_efault:
818 ret
819 restore %g0, -EFAULT, %o0
5fd29752
DM		 820__retl_efault:
821 retl
822 mov -EFAULT, %o0
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