]>
Commit | Line | Data |
---|---|---|
ad7ad57c | 1 | /* iommu.c: Generic sparc64 IOMMU support. |
1da177e4 | 2 | * |
d284142c | 3 | * Copyright (C) 1999, 2007, 2008 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1999, 2000 Jakub Jelinek (jakub@redhat.com) |
5 | */ | |
6 | ||
7 | #include <linux/kernel.h> | |
ad7ad57c | 8 | #include <linux/module.h> |
4dbc30fb | 9 | #include <linux/delay.h> |
ad7ad57c DM |
10 | #include <linux/device.h> |
11 | #include <linux/dma-mapping.h> | |
12 | #include <linux/errno.h> | |
d284142c | 13 | #include <linux/iommu-helper.h> |
ad7ad57c DM |
14 | |
15 | #ifdef CONFIG_PCI | |
c57c2ffb | 16 | #include <linux/pci.h> |
ad7ad57c | 17 | #endif |
1da177e4 | 18 | |
ad7ad57c | 19 | #include <asm/iommu.h> |
1da177e4 LT |
20 | |
21 | #include "iommu_common.h" | |
22 | ||
ad7ad57c | 23 | #define STC_CTXMATCH_ADDR(STC, CTX) \ |
1da177e4 | 24 | ((STC)->strbuf_ctxmatch_base + ((CTX) << 3)) |
ad7ad57c DM |
25 | #define STC_FLUSHFLAG_INIT(STC) \ |
26 | (*((STC)->strbuf_flushflag) = 0UL) | |
27 | #define STC_FLUSHFLAG_SET(STC) \ | |
28 | (*((STC)->strbuf_flushflag) != 0UL) | |
1da177e4 | 29 | |
ad7ad57c | 30 | #define iommu_read(__reg) \ |
1da177e4 LT |
31 | ({ u64 __ret; \ |
32 | __asm__ __volatile__("ldxa [%1] %2, %0" \ | |
33 | : "=r" (__ret) \ | |
34 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ | |
35 | : "memory"); \ | |
36 | __ret; \ | |
37 | }) | |
ad7ad57c | 38 | #define iommu_write(__reg, __val) \ |
1da177e4 LT |
39 | __asm__ __volatile__("stxa %0, [%1] %2" \ |
40 | : /* no outputs */ \ | |
41 | : "r" (__val), "r" (__reg), \ | |
42 | "i" (ASI_PHYS_BYPASS_EC_E)) | |
43 | ||
44 | /* Must be invoked under the IOMMU lock. */ | |
d284142c | 45 | static void iommu_flushall(struct iommu *iommu) |
1da177e4 | 46 | { |
861fe906 | 47 | if (iommu->iommu_flushinv) { |
ad7ad57c | 48 | iommu_write(iommu->iommu_flushinv, ~(u64)0); |
861fe906 DM |
49 | } else { |
50 | unsigned long tag; | |
51 | int entry; | |
1da177e4 | 52 | |
ad7ad57c | 53 | tag = iommu->iommu_tags; |
861fe906 | 54 | for (entry = 0; entry < 16; entry++) { |
ad7ad57c | 55 | iommu_write(tag, 0); |
861fe906 DM |
56 | tag += 8; |
57 | } | |
1da177e4 | 58 | |
861fe906 | 59 | /* Ensure completion of previous PIO writes. */ |
ad7ad57c | 60 | (void) iommu_read(iommu->write_complete_reg); |
861fe906 | 61 | } |
1da177e4 LT |
62 | } |
63 | ||
64 | #define IOPTE_CONSISTENT(CTX) \ | |
65 | (IOPTE_VALID | IOPTE_CACHE | \ | |
66 | (((CTX) << 47) & IOPTE_CONTEXT)) | |
67 | ||
68 | #define IOPTE_STREAMING(CTX) \ | |
69 | (IOPTE_CONSISTENT(CTX) | IOPTE_STBUF) | |
70 | ||
71 | /* Existing mappings are never marked invalid, instead they | |
72 | * are pointed to a dummy page. | |
73 | */ | |
74 | #define IOPTE_IS_DUMMY(iommu, iopte) \ | |
75 | ((iopte_val(*iopte) & IOPTE_PAGE) == (iommu)->dummy_page_pa) | |
76 | ||
16ce82d8 | 77 | static inline void iopte_make_dummy(struct iommu *iommu, iopte_t *iopte) |
1da177e4 LT |
78 | { |
79 | unsigned long val = iopte_val(*iopte); | |
80 | ||
81 | val &= ~IOPTE_PAGE; | |
82 | val |= iommu->dummy_page_pa; | |
83 | ||
84 | iopte_val(*iopte) = val; | |
85 | } | |
86 | ||
d284142c DM |
87 | /* Based almost entirely upon the ppc64 iommu allocator. If you use the 'handle' |
88 | * facility it must all be done in one pass while under the iommu lock. | |
89 | * | |
90 | * On sun4u platforms, we only flush the IOMMU once every time we've passed | |
91 | * over the entire page table doing allocations. Therefore we only ever advance | |
92 | * the hint and cannot backtrack it. | |
93 | */ | |
94 | unsigned long iommu_range_alloc(struct device *dev, | |
95 | struct iommu *iommu, | |
96 | unsigned long npages, | |
97 | unsigned long *handle) | |
688cb30b | 98 | { |
d284142c | 99 | unsigned long n, end, start, limit, boundary_size; |
9b3627f3 | 100 | struct iommu_arena *arena = &iommu->arena; |
d284142c DM |
101 | int pass = 0; |
102 | ||
103 | /* This allocator was derived from x86_64's bit string search */ | |
104 | ||
105 | /* Sanity check */ | |
106 | if (unlikely(npages == 0)) { | |
107 | if (printk_ratelimit()) | |
108 | WARN_ON(1); | |
109 | return DMA_ERROR_CODE; | |
110 | } | |
111 | ||
112 | if (handle && *handle) | |
113 | start = *handle; | |
114 | else | |
115 | start = arena->hint; | |
688cb30b DM |
116 | |
117 | limit = arena->limit; | |
688cb30b | 118 | |
d284142c DM |
119 | /* The case below can happen if we have a small segment appended |
120 | * to a large, or when the previous alloc was at the very end of | |
121 | * the available space. If so, go back to the beginning and flush. | |
122 | */ | |
123 | if (start >= limit) { | |
124 | start = 0; | |
125 | if (iommu->flush_all) | |
126 | iommu->flush_all(iommu); | |
127 | } | |
128 | ||
129 | again: | |
130 | ||
131 | if (dev) | |
132 | boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1, | |
133 | 1 << IO_PAGE_SHIFT); | |
134 | else | |
135 | boundary_size = ALIGN(1UL << 32, 1 << IO_PAGE_SHIFT); | |
136 | ||
89c94f2f FT |
137 | n = iommu_area_alloc(arena->map, limit, start, npages, |
138 | iommu->page_table_map_base >> IO_PAGE_SHIFT, | |
d284142c DM |
139 | boundary_size >> IO_PAGE_SHIFT, 0); |
140 | if (n == -1) { | |
688cb30b | 141 | if (likely(pass < 1)) { |
d284142c | 142 | /* First failure, rescan from the beginning. */ |
688cb30b | 143 | start = 0; |
d284142c DM |
144 | if (iommu->flush_all) |
145 | iommu->flush_all(iommu); | |
688cb30b DM |
146 | pass++; |
147 | goto again; | |
148 | } else { | |
d284142c DM |
149 | /* Second failure, give up */ |
150 | return DMA_ERROR_CODE; | |
688cb30b DM |
151 | } |
152 | } | |
153 | ||
d284142c | 154 | end = n + npages; |
688cb30b DM |
155 | |
156 | arena->hint = end; | |
157 | ||
d284142c DM |
158 | /* Update handle for SG allocations */ |
159 | if (handle) | |
160 | *handle = end; | |
161 | ||
688cb30b DM |
162 | return n; |
163 | } | |
164 | ||
d284142c | 165 | void iommu_range_free(struct iommu *iommu, dma_addr_t dma_addr, unsigned long npages) |
688cb30b | 166 | { |
d284142c DM |
167 | struct iommu_arena *arena = &iommu->arena; |
168 | unsigned long entry; | |
688cb30b | 169 | |
d284142c DM |
170 | entry = (dma_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT; |
171 | ||
172 | iommu_area_free(arena->map, entry, npages); | |
688cb30b DM |
173 | } |
174 | ||
ad7ad57c DM |
175 | int iommu_table_init(struct iommu *iommu, int tsbsize, |
176 | u32 dma_offset, u32 dma_addr_mask) | |
1da177e4 | 177 | { |
688cb30b DM |
178 | unsigned long i, tsbbase, order, sz, num_tsb_entries; |
179 | ||
180 | num_tsb_entries = tsbsize / sizeof(iopte_t); | |
51e85136 DM |
181 | |
182 | /* Setup initial software IOMMU state. */ | |
183 | spin_lock_init(&iommu->lock); | |
184 | iommu->ctx_lowest_free = 1; | |
185 | iommu->page_table_map_base = dma_offset; | |
186 | iommu->dma_addr_mask = dma_addr_mask; | |
187 | ||
688cb30b DM |
188 | /* Allocate and initialize the free area map. */ |
189 | sz = num_tsb_entries / 8; | |
190 | sz = (sz + 7UL) & ~7UL; | |
9132983a | 191 | iommu->arena.map = kzalloc(sz, GFP_KERNEL); |
688cb30b | 192 | if (!iommu->arena.map) { |
ad7ad57c DM |
193 | printk(KERN_ERR "IOMMU: Error, kmalloc(arena.map) failed.\n"); |
194 | return -ENOMEM; | |
51e85136 | 195 | } |
688cb30b | 196 | iommu->arena.limit = num_tsb_entries; |
1da177e4 | 197 | |
d284142c DM |
198 | if (tlb_type != hypervisor) |
199 | iommu->flush_all = iommu_flushall; | |
200 | ||
51e85136 DM |
201 | /* Allocate and initialize the dummy page which we |
202 | * set inactive IO PTEs to point to. | |
203 | */ | |
b83ebf56 | 204 | iommu->dummy_page = get_zeroed_page(GFP_KERNEL); |
51e85136 | 205 | if (!iommu->dummy_page) { |
ad7ad57c DM |
206 | printk(KERN_ERR "IOMMU: Error, gfp(dummy_page) failed.\n"); |
207 | goto out_free_map; | |
51e85136 | 208 | } |
51e85136 DM |
209 | iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page); |
210 | ||
211 | /* Now allocate and setup the IOMMU page table itself. */ | |
212 | order = get_order(tsbsize); | |
213 | tsbbase = __get_free_pages(GFP_KERNEL, order); | |
214 | if (!tsbbase) { | |
ad7ad57c DM |
215 | printk(KERN_ERR "IOMMU: Error, gfp(tsb) failed.\n"); |
216 | goto out_free_dummy_page; | |
51e85136 DM |
217 | } |
218 | iommu->page_table = (iopte_t *)tsbbase; | |
1da177e4 | 219 | |
688cb30b | 220 | for (i = 0; i < num_tsb_entries; i++) |
1da177e4 | 221 | iopte_make_dummy(iommu, &iommu->page_table[i]); |
ad7ad57c DM |
222 | |
223 | return 0; | |
224 | ||
225 | out_free_dummy_page: | |
226 | free_page(iommu->dummy_page); | |
227 | iommu->dummy_page = 0UL; | |
228 | ||
229 | out_free_map: | |
230 | kfree(iommu->arena.map); | |
231 | iommu->arena.map = NULL; | |
232 | ||
233 | return -ENOMEM; | |
1da177e4 LT |
234 | } |
235 | ||
d284142c DM |
236 | static inline iopte_t *alloc_npages(struct device *dev, struct iommu *iommu, |
237 | unsigned long npages) | |
1da177e4 | 238 | { |
d284142c | 239 | unsigned long entry; |
1da177e4 | 240 | |
d284142c DM |
241 | entry = iommu_range_alloc(dev, iommu, npages, NULL); |
242 | if (unlikely(entry == DMA_ERROR_CODE)) | |
688cb30b | 243 | return NULL; |
1da177e4 | 244 | |
688cb30b | 245 | return iommu->page_table + entry; |
1da177e4 LT |
246 | } |
247 | ||
16ce82d8 | 248 | static int iommu_alloc_ctx(struct iommu *iommu) |
7c963ad1 DM |
249 | { |
250 | int lowest = iommu->ctx_lowest_free; | |
251 | int sz = IOMMU_NUM_CTXS - lowest; | |
252 | int n = find_next_zero_bit(iommu->ctx_bitmap, sz, lowest); | |
253 | ||
254 | if (unlikely(n == sz)) { | |
255 | n = find_next_zero_bit(iommu->ctx_bitmap, lowest, 1); | |
256 | if (unlikely(n == lowest)) { | |
257 | printk(KERN_WARNING "IOMMU: Ran out of contexts.\n"); | |
258 | n = 0; | |
259 | } | |
260 | } | |
261 | if (n) | |
262 | __set_bit(n, iommu->ctx_bitmap); | |
263 | ||
264 | return n; | |
265 | } | |
266 | ||
16ce82d8 | 267 | static inline void iommu_free_ctx(struct iommu *iommu, int ctx) |
7c963ad1 DM |
268 | { |
269 | if (likely(ctx)) { | |
270 | __clear_bit(ctx, iommu->ctx_bitmap); | |
271 | if (ctx < iommu->ctx_lowest_free) | |
272 | iommu->ctx_lowest_free = ctx; | |
273 | } | |
274 | } | |
275 | ||
ad7ad57c DM |
276 | static void *dma_4u_alloc_coherent(struct device *dev, size_t size, |
277 | dma_addr_t *dma_addrp, gfp_t gfp) | |
1da177e4 | 278 | { |
16ce82d8 | 279 | struct iommu *iommu; |
1da177e4 | 280 | iopte_t *iopte; |
688cb30b | 281 | unsigned long flags, order, first_page; |
1da177e4 LT |
282 | void *ret; |
283 | int npages; | |
284 | ||
285 | size = IO_PAGE_ALIGN(size); | |
286 | order = get_order(size); | |
287 | if (order >= 10) | |
288 | return NULL; | |
289 | ||
42f14237 | 290 | first_page = __get_free_pages(gfp, order); |
1da177e4 LT |
291 | if (first_page == 0UL) |
292 | return NULL; | |
293 | memset((char *)first_page, 0, PAGE_SIZE << order); | |
294 | ||
ad7ad57c | 295 | iommu = dev->archdata.iommu; |
1da177e4 LT |
296 | |
297 | spin_lock_irqsave(&iommu->lock, flags); | |
d284142c | 298 | iopte = alloc_npages(dev, iommu, size >> IO_PAGE_SHIFT); |
688cb30b DM |
299 | spin_unlock_irqrestore(&iommu->lock, flags); |
300 | ||
301 | if (unlikely(iopte == NULL)) { | |
1da177e4 LT |
302 | free_pages(first_page, order); |
303 | return NULL; | |
304 | } | |
305 | ||
306 | *dma_addrp = (iommu->page_table_map_base + | |
307 | ((iopte - iommu->page_table) << IO_PAGE_SHIFT)); | |
308 | ret = (void *) first_page; | |
309 | npages = size >> IO_PAGE_SHIFT; | |
1da177e4 LT |
310 | first_page = __pa(first_page); |
311 | while (npages--) { | |
688cb30b | 312 | iopte_val(*iopte) = (IOPTE_CONSISTENT(0UL) | |
1da177e4 LT |
313 | IOPTE_WRITE | |
314 | (first_page & IOPTE_PAGE)); | |
315 | iopte++; | |
316 | first_page += IO_PAGE_SIZE; | |
317 | } | |
318 | ||
1da177e4 LT |
319 | return ret; |
320 | } | |
321 | ||
ad7ad57c DM |
322 | static void dma_4u_free_coherent(struct device *dev, size_t size, |
323 | void *cpu, dma_addr_t dvma) | |
1da177e4 | 324 | { |
16ce82d8 | 325 | struct iommu *iommu; |
1da177e4 | 326 | iopte_t *iopte; |
688cb30b | 327 | unsigned long flags, order, npages; |
1da177e4 LT |
328 | |
329 | npages = IO_PAGE_ALIGN(size) >> IO_PAGE_SHIFT; | |
ad7ad57c | 330 | iommu = dev->archdata.iommu; |
1da177e4 LT |
331 | iopte = iommu->page_table + |
332 | ((dvma - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
333 | ||
334 | spin_lock_irqsave(&iommu->lock, flags); | |
335 | ||
d284142c | 336 | iommu_range_free(iommu, dvma, npages); |
7c963ad1 | 337 | |
1da177e4 LT |
338 | spin_unlock_irqrestore(&iommu->lock, flags); |
339 | ||
340 | order = get_order(size); | |
341 | if (order < 10) | |
342 | free_pages((unsigned long)cpu, order); | |
343 | } | |
344 | ||
ad7ad57c DM |
345 | static dma_addr_t dma_4u_map_single(struct device *dev, void *ptr, size_t sz, |
346 | enum dma_data_direction direction) | |
1da177e4 | 347 | { |
16ce82d8 DM |
348 | struct iommu *iommu; |
349 | struct strbuf *strbuf; | |
1da177e4 LT |
350 | iopte_t *base; |
351 | unsigned long flags, npages, oaddr; | |
352 | unsigned long i, base_paddr, ctx; | |
353 | u32 bus_addr, ret; | |
354 | unsigned long iopte_protection; | |
355 | ||
ad7ad57c DM |
356 | iommu = dev->archdata.iommu; |
357 | strbuf = dev->archdata.stc; | |
1da177e4 | 358 | |
ad7ad57c | 359 | if (unlikely(direction == DMA_NONE)) |
688cb30b | 360 | goto bad_no_ctx; |
1da177e4 LT |
361 | |
362 | oaddr = (unsigned long)ptr; | |
363 | npages = IO_PAGE_ALIGN(oaddr + sz) - (oaddr & IO_PAGE_MASK); | |
364 | npages >>= IO_PAGE_SHIFT; | |
365 | ||
366 | spin_lock_irqsave(&iommu->lock, flags); | |
d284142c | 367 | base = alloc_npages(dev, iommu, npages); |
688cb30b DM |
368 | ctx = 0; |
369 | if (iommu->iommu_ctxflush) | |
370 | ctx = iommu_alloc_ctx(iommu); | |
371 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1da177e4 | 372 | |
688cb30b | 373 | if (unlikely(!base)) |
1da177e4 | 374 | goto bad; |
688cb30b | 375 | |
1da177e4 LT |
376 | bus_addr = (iommu->page_table_map_base + |
377 | ((base - iommu->page_table) << IO_PAGE_SHIFT)); | |
378 | ret = bus_addr | (oaddr & ~IO_PAGE_MASK); | |
379 | base_paddr = __pa(oaddr & IO_PAGE_MASK); | |
1da177e4 LT |
380 | if (strbuf->strbuf_enabled) |
381 | iopte_protection = IOPTE_STREAMING(ctx); | |
382 | else | |
383 | iopte_protection = IOPTE_CONSISTENT(ctx); | |
ad7ad57c | 384 | if (direction != DMA_TO_DEVICE) |
1da177e4 LT |
385 | iopte_protection |= IOPTE_WRITE; |
386 | ||
387 | for (i = 0; i < npages; i++, base++, base_paddr += IO_PAGE_SIZE) | |
388 | iopte_val(*base) = iopte_protection | base_paddr; | |
389 | ||
1da177e4 LT |
390 | return ret; |
391 | ||
392 | bad: | |
688cb30b DM |
393 | iommu_free_ctx(iommu, ctx); |
394 | bad_no_ctx: | |
395 | if (printk_ratelimit()) | |
396 | WARN_ON(1); | |
ad7ad57c | 397 | return DMA_ERROR_CODE; |
1da177e4 LT |
398 | } |
399 | ||
ad7ad57c DM |
400 | static void strbuf_flush(struct strbuf *strbuf, struct iommu *iommu, |
401 | u32 vaddr, unsigned long ctx, unsigned long npages, | |
402 | enum dma_data_direction direction) | |
4dbc30fb DM |
403 | { |
404 | int limit; | |
405 | ||
4dbc30fb DM |
406 | if (strbuf->strbuf_ctxflush && |
407 | iommu->iommu_ctxflush) { | |
408 | unsigned long matchreg, flushreg; | |
7c963ad1 | 409 | u64 val; |
4dbc30fb DM |
410 | |
411 | flushreg = strbuf->strbuf_ctxflush; | |
ad7ad57c | 412 | matchreg = STC_CTXMATCH_ADDR(strbuf, ctx); |
4dbc30fb | 413 | |
ad7ad57c DM |
414 | iommu_write(flushreg, ctx); |
415 | val = iommu_read(matchreg); | |
88314ee7 DM |
416 | val &= 0xffff; |
417 | if (!val) | |
7c963ad1 DM |
418 | goto do_flush_sync; |
419 | ||
7c963ad1 DM |
420 | while (val) { |
421 | if (val & 0x1) | |
ad7ad57c | 422 | iommu_write(flushreg, ctx); |
7c963ad1 | 423 | val >>= 1; |
a228dfd5 | 424 | } |
ad7ad57c | 425 | val = iommu_read(matchreg); |
7c963ad1 | 426 | if (unlikely(val)) { |
ad7ad57c | 427 | printk(KERN_WARNING "strbuf_flush: ctx flush " |
7c963ad1 DM |
428 | "timeout matchreg[%lx] ctx[%lx]\n", |
429 | val, ctx); | |
430 | goto do_page_flush; | |
431 | } | |
4dbc30fb DM |
432 | } else { |
433 | unsigned long i; | |
434 | ||
7c963ad1 | 435 | do_page_flush: |
4dbc30fb | 436 | for (i = 0; i < npages; i++, vaddr += IO_PAGE_SIZE) |
ad7ad57c | 437 | iommu_write(strbuf->strbuf_pflush, vaddr); |
4dbc30fb DM |
438 | } |
439 | ||
7c963ad1 DM |
440 | do_flush_sync: |
441 | /* If the device could not have possibly put dirty data into | |
442 | * the streaming cache, no flush-flag synchronization needs | |
443 | * to be performed. | |
444 | */ | |
ad7ad57c | 445 | if (direction == DMA_TO_DEVICE) |
7c963ad1 DM |
446 | return; |
447 | ||
ad7ad57c DM |
448 | STC_FLUSHFLAG_INIT(strbuf); |
449 | iommu_write(strbuf->strbuf_fsync, strbuf->strbuf_flushflag_pa); | |
450 | (void) iommu_read(iommu->write_complete_reg); | |
4dbc30fb | 451 | |
a228dfd5 | 452 | limit = 100000; |
ad7ad57c | 453 | while (!STC_FLUSHFLAG_SET(strbuf)) { |
4dbc30fb DM |
454 | limit--; |
455 | if (!limit) | |
456 | break; | |
a228dfd5 | 457 | udelay(1); |
4f07118f | 458 | rmb(); |
4dbc30fb DM |
459 | } |
460 | if (!limit) | |
ad7ad57c | 461 | printk(KERN_WARNING "strbuf_flush: flushflag timeout " |
4dbc30fb DM |
462 | "vaddr[%08x] ctx[%lx] npages[%ld]\n", |
463 | vaddr, ctx, npages); | |
464 | } | |
465 | ||
ad7ad57c DM |
466 | static void dma_4u_unmap_single(struct device *dev, dma_addr_t bus_addr, |
467 | size_t sz, enum dma_data_direction direction) | |
1da177e4 | 468 | { |
16ce82d8 DM |
469 | struct iommu *iommu; |
470 | struct strbuf *strbuf; | |
1da177e4 | 471 | iopte_t *base; |
688cb30b | 472 | unsigned long flags, npages, ctx, i; |
1da177e4 | 473 | |
ad7ad57c | 474 | if (unlikely(direction == DMA_NONE)) { |
688cb30b DM |
475 | if (printk_ratelimit()) |
476 | WARN_ON(1); | |
477 | return; | |
478 | } | |
1da177e4 | 479 | |
ad7ad57c DM |
480 | iommu = dev->archdata.iommu; |
481 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
482 | |
483 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
484 | npages >>= IO_PAGE_SHIFT; | |
485 | base = iommu->page_table + | |
486 | ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
1da177e4 LT |
487 | bus_addr &= IO_PAGE_MASK; |
488 | ||
489 | spin_lock_irqsave(&iommu->lock, flags); | |
490 | ||
491 | /* Record the context, if any. */ | |
492 | ctx = 0; | |
493 | if (iommu->iommu_ctxflush) | |
494 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
495 | ||
496 | /* Step 1: Kick data out of streaming buffers if necessary. */ | |
4dbc30fb | 497 | if (strbuf->strbuf_enabled) |
ad7ad57c DM |
498 | strbuf_flush(strbuf, iommu, bus_addr, ctx, |
499 | npages, direction); | |
1da177e4 | 500 | |
688cb30b DM |
501 | /* Step 2: Clear out TSB entries. */ |
502 | for (i = 0; i < npages; i++) | |
503 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 504 | |
d284142c | 505 | iommu_range_free(iommu, bus_addr, npages); |
1da177e4 | 506 | |
7c963ad1 DM |
507 | iommu_free_ctx(iommu, ctx); |
508 | ||
1da177e4 LT |
509 | spin_unlock_irqrestore(&iommu->lock, flags); |
510 | } | |
511 | ||
ad7ad57c DM |
512 | static int dma_4u_map_sg(struct device *dev, struct scatterlist *sglist, |
513 | int nelems, enum dma_data_direction direction) | |
1da177e4 | 514 | { |
13fa14e1 DM |
515 | struct scatterlist *s, *outs, *segstart; |
516 | unsigned long flags, handle, prot, ctx; | |
517 | dma_addr_t dma_next = 0, dma_addr; | |
518 | unsigned int max_seg_size; | |
519 | int outcount, incount, i; | |
16ce82d8 | 520 | struct strbuf *strbuf; |
38192d52 | 521 | struct iommu *iommu; |
13fa14e1 DM |
522 | |
523 | BUG_ON(direction == DMA_NONE); | |
1da177e4 | 524 | |
ad7ad57c DM |
525 | iommu = dev->archdata.iommu; |
526 | strbuf = dev->archdata.stc; | |
13fa14e1 DM |
527 | if (nelems == 0 || !iommu) |
528 | return 0; | |
1da177e4 LT |
529 | |
530 | spin_lock_irqsave(&iommu->lock, flags); | |
531 | ||
688cb30b DM |
532 | ctx = 0; |
533 | if (iommu->iommu_ctxflush) | |
534 | ctx = iommu_alloc_ctx(iommu); | |
535 | ||
1da177e4 | 536 | if (strbuf->strbuf_enabled) |
13fa14e1 | 537 | prot = IOPTE_STREAMING(ctx); |
1da177e4 | 538 | else |
13fa14e1 | 539 | prot = IOPTE_CONSISTENT(ctx); |
ad7ad57c | 540 | if (direction != DMA_TO_DEVICE) |
13fa14e1 DM |
541 | prot |= IOPTE_WRITE; |
542 | ||
543 | outs = s = segstart = &sglist[0]; | |
544 | outcount = 1; | |
545 | incount = nelems; | |
546 | handle = 0; | |
547 | ||
548 | /* Init first segment length for backout at failure */ | |
549 | outs->dma_length = 0; | |
550 | ||
551 | max_seg_size = dma_get_max_seg_size(dev); | |
552 | for_each_sg(sglist, s, nelems, i) { | |
553 | unsigned long paddr, npages, entry, slen; | |
554 | iopte_t *base; | |
555 | ||
556 | slen = s->length; | |
557 | /* Sanity check */ | |
558 | if (slen == 0) { | |
559 | dma_next = 0; | |
560 | continue; | |
561 | } | |
562 | /* Allocate iommu entries for that segment */ | |
563 | paddr = (unsigned long) SG_ENT_PHYS_ADDRESS(s); | |
564 | npages = iommu_num_pages(paddr, slen); | |
565 | entry = iommu_range_alloc(dev, iommu, npages, &handle); | |
566 | ||
567 | /* Handle failure */ | |
568 | if (unlikely(entry == DMA_ERROR_CODE)) { | |
569 | if (printk_ratelimit()) | |
570 | printk(KERN_INFO "iommu_alloc failed, iommu %p paddr %lx" | |
571 | " npages %lx\n", iommu, paddr, npages); | |
572 | goto iommu_map_failed; | |
573 | } | |
688cb30b | 574 | |
13fa14e1 | 575 | base = iommu->page_table + entry; |
1da177e4 | 576 | |
13fa14e1 DM |
577 | /* Convert entry to a dma_addr_t */ |
578 | dma_addr = iommu->page_table_map_base + | |
579 | (entry << IO_PAGE_SHIFT); | |
580 | dma_addr |= (s->offset & ~IO_PAGE_MASK); | |
38192d52 | 581 | |
13fa14e1 | 582 | /* Insert into HW table */ |
38192d52 | 583 | paddr &= IO_PAGE_MASK; |
13fa14e1 DM |
584 | while (npages--) { |
585 | iopte_val(*base) = prot | paddr; | |
38192d52 DM |
586 | base++; |
587 | paddr += IO_PAGE_SIZE; | |
38192d52 | 588 | } |
13fa14e1 DM |
589 | |
590 | /* If we are in an open segment, try merging */ | |
591 | if (segstart != s) { | |
592 | /* We cannot merge if: | |
593 | * - allocated dma_addr isn't contiguous to previous allocation | |
594 | */ | |
595 | if ((dma_addr != dma_next) || | |
596 | (outs->dma_length + s->length > max_seg_size)) { | |
597 | /* Can't merge: create a new segment */ | |
598 | segstart = s; | |
599 | outcount++; | |
600 | outs = sg_next(outs); | |
601 | } else { | |
602 | outs->dma_length += s->length; | |
603 | } | |
604 | } | |
605 | ||
606 | if (segstart == s) { | |
607 | /* This is a new segment, fill entries */ | |
608 | outs->dma_address = dma_addr; | |
609 | outs->dma_length = slen; | |
610 | } | |
611 | ||
612 | /* Calculate next page pointer for contiguous check */ | |
613 | dma_next = dma_addr + slen; | |
38192d52 DM |
614 | } |
615 | ||
13fa14e1 DM |
616 | spin_unlock_irqrestore(&iommu->lock, flags); |
617 | ||
618 | if (outcount < incount) { | |
619 | outs = sg_next(outs); | |
620 | outs->dma_address = DMA_ERROR_CODE; | |
621 | outs->dma_length = 0; | |
622 | } | |
623 | ||
624 | return outcount; | |
625 | ||
626 | iommu_map_failed: | |
627 | for_each_sg(sglist, s, nelems, i) { | |
628 | if (s->dma_length != 0) { | |
629 | unsigned long vaddr, npages, entry, i; | |
630 | iopte_t *base; | |
631 | ||
632 | vaddr = s->dma_address & IO_PAGE_MASK; | |
633 | npages = iommu_num_pages(s->dma_address, s->dma_length); | |
634 | iommu_range_free(iommu, vaddr, npages); | |
635 | ||
636 | entry = (vaddr - iommu->page_table_map_base) | |
637 | >> IO_PAGE_SHIFT; | |
638 | base = iommu->page_table + entry; | |
639 | ||
640 | for (i = 0; i < npages; i++) | |
641 | iopte_make_dummy(iommu, base + i); | |
642 | ||
643 | s->dma_address = DMA_ERROR_CODE; | |
644 | s->dma_length = 0; | |
645 | } | |
646 | if (s == outs) | |
647 | break; | |
648 | } | |
649 | spin_unlock_irqrestore(&iommu->lock, flags); | |
1da177e4 | 650 | |
688cb30b | 651 | return 0; |
1da177e4 LT |
652 | } |
653 | ||
13fa14e1 DM |
654 | /* If contexts are being used, they are the same in all of the mappings |
655 | * we make for a particular SG. | |
656 | */ | |
657 | static unsigned long fetch_sg_ctx(struct iommu *iommu, struct scatterlist *sg) | |
658 | { | |
659 | unsigned long ctx = 0; | |
660 | ||
661 | if (iommu->iommu_ctxflush) { | |
662 | iopte_t *base; | |
663 | u32 bus_addr; | |
664 | ||
665 | bus_addr = sg->dma_address & IO_PAGE_MASK; | |
666 | base = iommu->page_table + | |
667 | ((bus_addr - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
668 | ||
669 | ctx = (iopte_val(*base) & IOPTE_CONTEXT) >> 47UL; | |
670 | } | |
671 | return ctx; | |
672 | } | |
673 | ||
ad7ad57c DM |
674 | static void dma_4u_unmap_sg(struct device *dev, struct scatterlist *sglist, |
675 | int nelems, enum dma_data_direction direction) | |
1da177e4 | 676 | { |
13fa14e1 DM |
677 | unsigned long flags, ctx; |
678 | struct scatterlist *sg; | |
16ce82d8 | 679 | struct strbuf *strbuf; |
38192d52 | 680 | struct iommu *iommu; |
1da177e4 | 681 | |
13fa14e1 | 682 | BUG_ON(direction == DMA_NONE); |
1da177e4 | 683 | |
ad7ad57c DM |
684 | iommu = dev->archdata.iommu; |
685 | strbuf = dev->archdata.stc; | |
686 | ||
13fa14e1 | 687 | ctx = fetch_sg_ctx(iommu, sglist); |
1da177e4 | 688 | |
13fa14e1 | 689 | spin_lock_irqsave(&iommu->lock, flags); |
1da177e4 | 690 | |
13fa14e1 DM |
691 | sg = sglist; |
692 | while (nelems--) { | |
693 | dma_addr_t dma_handle = sg->dma_address; | |
694 | unsigned int len = sg->dma_length; | |
695 | unsigned long npages, entry; | |
696 | iopte_t *base; | |
697 | int i; | |
1da177e4 | 698 | |
13fa14e1 DM |
699 | if (!len) |
700 | break; | |
701 | npages = iommu_num_pages(dma_handle, len); | |
702 | iommu_range_free(iommu, dma_handle, npages); | |
1da177e4 | 703 | |
13fa14e1 DM |
704 | entry = ((dma_handle - iommu->page_table_map_base) |
705 | >> IO_PAGE_SHIFT); | |
706 | base = iommu->page_table + entry; | |
1da177e4 | 707 | |
13fa14e1 DM |
708 | dma_handle &= IO_PAGE_MASK; |
709 | if (strbuf->strbuf_enabled) | |
710 | strbuf_flush(strbuf, iommu, dma_handle, ctx, | |
711 | npages, direction); | |
1da177e4 | 712 | |
13fa14e1 DM |
713 | for (i = 0; i < npages; i++) |
714 | iopte_make_dummy(iommu, base + i); | |
1da177e4 | 715 | |
13fa14e1 DM |
716 | sg = sg_next(sg); |
717 | } | |
1da177e4 | 718 | |
7c963ad1 DM |
719 | iommu_free_ctx(iommu, ctx); |
720 | ||
1da177e4 LT |
721 | spin_unlock_irqrestore(&iommu->lock, flags); |
722 | } | |
723 | ||
ad7ad57c DM |
724 | static void dma_4u_sync_single_for_cpu(struct device *dev, |
725 | dma_addr_t bus_addr, size_t sz, | |
726 | enum dma_data_direction direction) | |
1da177e4 | 727 | { |
16ce82d8 DM |
728 | struct iommu *iommu; |
729 | struct strbuf *strbuf; | |
1da177e4 LT |
730 | unsigned long flags, ctx, npages; |
731 | ||
ad7ad57c DM |
732 | iommu = dev->archdata.iommu; |
733 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
734 | |
735 | if (!strbuf->strbuf_enabled) | |
736 | return; | |
737 | ||
738 | spin_lock_irqsave(&iommu->lock, flags); | |
739 | ||
740 | npages = IO_PAGE_ALIGN(bus_addr + sz) - (bus_addr & IO_PAGE_MASK); | |
741 | npages >>= IO_PAGE_SHIFT; | |
742 | bus_addr &= IO_PAGE_MASK; | |
743 | ||
744 | /* Step 1: Record the context, if any. */ | |
745 | ctx = 0; | |
746 | if (iommu->iommu_ctxflush && | |
747 | strbuf->strbuf_ctxflush) { | |
748 | iopte_t *iopte; | |
749 | ||
750 | iopte = iommu->page_table + | |
751 | ((bus_addr - iommu->page_table_map_base)>>IO_PAGE_SHIFT); | |
752 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; | |
753 | } | |
754 | ||
755 | /* Step 2: Kick data out of streaming buffers. */ | |
ad7ad57c | 756 | strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
757 | |
758 | spin_unlock_irqrestore(&iommu->lock, flags); | |
759 | } | |
760 | ||
ad7ad57c DM |
761 | static void dma_4u_sync_sg_for_cpu(struct device *dev, |
762 | struct scatterlist *sglist, int nelems, | |
763 | enum dma_data_direction direction) | |
1da177e4 | 764 | { |
16ce82d8 DM |
765 | struct iommu *iommu; |
766 | struct strbuf *strbuf; | |
4dbc30fb | 767 | unsigned long flags, ctx, npages, i; |
2c941a20 | 768 | struct scatterlist *sg, *sgprv; |
4dbc30fb | 769 | u32 bus_addr; |
1da177e4 | 770 | |
ad7ad57c DM |
771 | iommu = dev->archdata.iommu; |
772 | strbuf = dev->archdata.stc; | |
1da177e4 LT |
773 | |
774 | if (!strbuf->strbuf_enabled) | |
775 | return; | |
776 | ||
777 | spin_lock_irqsave(&iommu->lock, flags); | |
778 | ||
779 | /* Step 1: Record the context, if any. */ | |
780 | ctx = 0; | |
781 | if (iommu->iommu_ctxflush && | |
782 | strbuf->strbuf_ctxflush) { | |
783 | iopte_t *iopte; | |
784 | ||
785 | iopte = iommu->page_table + | |
786 | ((sglist[0].dma_address - iommu->page_table_map_base) >> IO_PAGE_SHIFT); | |
787 | ctx = (iopte_val(*iopte) & IOPTE_CONTEXT) >> 47UL; | |
788 | } | |
789 | ||
790 | /* Step 2: Kick data out of streaming buffers. */ | |
4dbc30fb | 791 | bus_addr = sglist[0].dma_address & IO_PAGE_MASK; |
2c941a20 JA |
792 | sgprv = NULL; |
793 | for_each_sg(sglist, sg, nelems, i) { | |
794 | if (sg->dma_length == 0) | |
4dbc30fb | 795 | break; |
2c941a20 JA |
796 | sgprv = sg; |
797 | } | |
798 | ||
799 | npages = (IO_PAGE_ALIGN(sgprv->dma_address + sgprv->dma_length) | |
4dbc30fb | 800 | - bus_addr) >> IO_PAGE_SHIFT; |
ad7ad57c | 801 | strbuf_flush(strbuf, iommu, bus_addr, ctx, npages, direction); |
1da177e4 LT |
802 | |
803 | spin_unlock_irqrestore(&iommu->lock, flags); | |
804 | } | |
805 | ||
ad7ad57c DM |
806 | const struct dma_ops sun4u_dma_ops = { |
807 | .alloc_coherent = dma_4u_alloc_coherent, | |
808 | .free_coherent = dma_4u_free_coherent, | |
809 | .map_single = dma_4u_map_single, | |
810 | .unmap_single = dma_4u_unmap_single, | |
811 | .map_sg = dma_4u_map_sg, | |
812 | .unmap_sg = dma_4u_unmap_sg, | |
813 | .sync_single_for_cpu = dma_4u_sync_single_for_cpu, | |
814 | .sync_sg_for_cpu = dma_4u_sync_sg_for_cpu, | |
8f6a93a1 DM |
815 | }; |
816 | ||
ad7ad57c DM |
817 | const struct dma_ops *dma_ops = &sun4u_dma_ops; |
818 | EXPORT_SYMBOL(dma_ops); | |
1da177e4 | 819 | |
ad7ad57c | 820 | int dma_supported(struct device *dev, u64 device_mask) |
1da177e4 | 821 | { |
ad7ad57c DM |
822 | struct iommu *iommu = dev->archdata.iommu; |
823 | u64 dma_addr_mask = iommu->dma_addr_mask; | |
1da177e4 | 824 | |
ad7ad57c DM |
825 | if (device_mask >= (1UL << 32UL)) |
826 | return 0; | |
1da177e4 | 827 | |
ad7ad57c DM |
828 | if ((device_mask & dma_addr_mask) == dma_addr_mask) |
829 | return 1; | |
1da177e4 | 830 | |
ad7ad57c DM |
831 | #ifdef CONFIG_PCI |
832 | if (dev->bus == &pci_bus_type) | |
833 | return pci_dma_supported(to_pci_dev(dev), device_mask); | |
834 | #endif | |
1da177e4 | 835 | |
ad7ad57c DM |
836 | return 0; |
837 | } | |
838 | EXPORT_SYMBOL(dma_supported); | |
1da177e4 | 839 | |
ad7ad57c DM |
840 | int dma_set_mask(struct device *dev, u64 dma_mask) |
841 | { | |
842 | #ifdef CONFIG_PCI | |
843 | if (dev->bus == &pci_bus_type) | |
844 | return pci_set_dma_mask(to_pci_dev(dev), dma_mask); | |
845 | #endif | |
846 | return -EINVAL; | |
1da177e4 | 847 | } |
ad7ad57c | 848 | EXPORT_SYMBOL(dma_set_mask); |