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1da177e4 LT |
1 | /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $ |
2 | * irq.c: UltraSparc IRQ handling/init/registry. | |
3 | * | |
4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
9 | #include <linux/config.h> | |
10 | #include <linux/module.h> | |
11 | #include <linux/sched.h> | |
12 | #include <linux/ptrace.h> | |
13 | #include <linux/errno.h> | |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/signal.h> | |
16 | #include <linux/mm.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/slab.h> | |
19 | #include <linux/random.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/proc_fs.h> | |
23 | #include <linux/seq_file.h> | |
b5a37e96 | 24 | #include <linux/bootmem.h> |
1da177e4 LT |
25 | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/processor.h> | |
28 | #include <asm/atomic.h> | |
29 | #include <asm/system.h> | |
30 | #include <asm/irq.h> | |
2e457ef6 | 31 | #include <asm/io.h> |
1da177e4 LT |
32 | #include <asm/sbus.h> |
33 | #include <asm/iommu.h> | |
34 | #include <asm/upa.h> | |
35 | #include <asm/oplib.h> | |
36 | #include <asm/timer.h> | |
37 | #include <asm/smp.h> | |
38 | #include <asm/starfire.h> | |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/cache.h> | |
41 | #include <asm/cpudata.h> | |
63b61452 | 42 | #include <asm/auxio.h> |
92704a1c | 43 | #include <asm/head.h> |
1da177e4 LT |
44 | |
45 | #ifdef CONFIG_SMP | |
46 | static void distribute_irqs(void); | |
47 | #endif | |
48 | ||
49 | /* UPA nodes send interrupt packet to UltraSparc with first data reg | |
50 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
51 | * delivered. We must translate this into a non-vector IRQ so we can | |
52 | * set the softint on this cpu. | |
53 | * | |
54 | * To make processing these packets efficient and race free we use | |
55 | * an array of irq buckets below. The interrupt vector handler in | |
56 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
57 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
58 | * code uses CAS to get an atomic snapshot of the list and clear it | |
59 | * at the same time. | |
60 | */ | |
61 | ||
62 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); | |
63 | ||
64 | /* This has to be in the main kernel image, it cannot be | |
65 | * turned into per-cpu data. The reason is that the main | |
66 | * kernel image is locked into the TLB and this structure | |
67 | * is accessed from the vectored interrupt trap handler. If | |
68 | * access to this structure takes a TLB miss it could cause | |
69 | * the 5-level sparc v9 trap stack to overflow. | |
70 | */ | |
71 | struct irq_work_struct { | |
72 | unsigned int irq_worklists[16]; | |
73 | }; | |
74 | struct irq_work_struct __irq_work[NR_CPUS]; | |
75 | #define irq_work(__cpu, __pil) &(__irq_work[(__cpu)].irq_worklists[(__pil)]) | |
76 | ||
088dd1f8 | 77 | static struct irqaction *irq_action[NR_IRQS+1]; |
1da177e4 LT |
78 | |
79 | /* This only synchronizes entities which modify IRQ handler | |
80 | * state and some selected user-level spots that want to | |
81 | * read things in the table. IRQ handler processing orders | |
82 | * its' accesses such that no locking is needed. | |
83 | */ | |
84 | static DEFINE_SPINLOCK(irq_action_lock); | |
85 | ||
86 | static void register_irq_proc (unsigned int irq); | |
87 | ||
88 | /* | |
89 | * Upper 2b of irqaction->flags holds the ino. | |
90 | * irqaction->mask holds the smp affinity information. | |
91 | */ | |
92 | #define put_ino_in_irqaction(action, irq) \ | |
93 | action->flags &= 0xffffffffffffUL; \ | |
94 | if (__bucket(irq) == &pil0_dummy_bucket) \ | |
95 | action->flags |= 0xdeadUL << 48; \ | |
96 | else \ | |
97 | action->flags |= __irq_ino(irq) << 48; | |
98 | #define get_ino_in_irqaction(action) (action->flags >> 48) | |
99 | ||
100 | #define put_smpaff_in_irqaction(action, smpaff) (action)->mask = (smpaff) | |
101 | #define get_smpaff_in_irqaction(action) ((action)->mask) | |
102 | ||
103 | int show_interrupts(struct seq_file *p, void *v) | |
104 | { | |
105 | unsigned long flags; | |
106 | int i = *(loff_t *) v; | |
107 | struct irqaction *action; | |
108 | #ifdef CONFIG_SMP | |
109 | int j; | |
110 | #endif | |
111 | ||
112 | spin_lock_irqsave(&irq_action_lock, flags); | |
113 | if (i <= NR_IRQS) { | |
114 | if (!(action = *(i + irq_action))) | |
115 | goto out_unlock; | |
116 | seq_printf(p, "%3d: ", i); | |
117 | #ifndef CONFIG_SMP | |
118 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
119 | #else | |
394e3902 | 120 | for_each_online_cpu(j) { |
1da177e4 LT |
121 | seq_printf(p, "%10u ", |
122 | kstat_cpu(j).irqs[i]); | |
123 | } | |
124 | #endif | |
125 | seq_printf(p, " %s:%lx", action->name, | |
126 | get_ino_in_irqaction(action)); | |
127 | for (action = action->next; action; action = action->next) { | |
128 | seq_printf(p, ", %s:%lx", action->name, | |
129 | get_ino_in_irqaction(action)); | |
130 | } | |
131 | seq_putc(p, '\n'); | |
132 | } | |
133 | out_unlock: | |
134 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
ebd8c56c DM |
139 | extern unsigned long real_hard_smp_processor_id(void); |
140 | ||
141 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) | |
142 | { | |
143 | unsigned int tid; | |
144 | ||
145 | if (this_is_starfire) { | |
146 | tid = starfire_translate(imap, cpuid); | |
147 | tid <<= IMAP_TID_SHIFT; | |
148 | tid &= IMAP_TID_UPA; | |
149 | } else { | |
150 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
151 | unsigned long ver; | |
152 | ||
153 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
154 | if ((ver >> 32UL) == __JALAPENO_ID || | |
155 | (ver >> 32UL) == __SERRANO_ID) { | |
156 | tid = cpuid << IMAP_TID_SHIFT; | |
157 | tid &= IMAP_TID_JBUS; | |
158 | } else { | |
159 | unsigned int a = cpuid & 0x1f; | |
160 | unsigned int n = (cpuid >> 5) & 0x1f; | |
161 | ||
162 | tid = ((a << IMAP_AID_SHIFT) | | |
163 | (n << IMAP_NID_SHIFT)); | |
164 | tid &= (IMAP_AID_SAFARI | | |
165 | IMAP_NID_SAFARI);; | |
166 | } | |
167 | } else { | |
168 | tid = cpuid << IMAP_TID_SHIFT; | |
169 | tid &= IMAP_TID_UPA; | |
170 | } | |
171 | } | |
172 | ||
173 | return tid; | |
174 | } | |
175 | ||
1da177e4 LT |
176 | /* Now these are always passed a true fully specified sun4u INO. */ |
177 | void enable_irq(unsigned int irq) | |
178 | { | |
179 | struct ino_bucket *bucket = __bucket(irq); | |
ebd8c56c | 180 | unsigned long imap, cpuid; |
1da177e4 LT |
181 | |
182 | imap = bucket->imap; | |
183 | if (imap == 0UL) | |
184 | return; | |
185 | ||
186 | preempt_disable(); | |
187 | ||
ebd8c56c DM |
188 | /* This gets the physical processor ID, even on uniprocessor, |
189 | * so we can always program the interrupt target correctly. | |
190 | */ | |
191 | cpuid = real_hard_smp_processor_id(); | |
192 | ||
d82ace7d | 193 | if (tlb_type == hypervisor) { |
4bf447d6 | 194 | unsigned int ino = __irq_ino(irq); |
c4bea288 | 195 | int err; |
10951ee6 | 196 | |
ebd8c56c | 197 | err = sun4v_intr_settarget(ino, cpuid); |
c4bea288 | 198 | if (err != HV_EOK) |
ebd8c56c DM |
199 | printk("sun4v_intr_settarget(%x,%lu): err(%d)\n", |
200 | ino, cpuid, err); | |
abd92b2d | 201 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); |
c4bea288 DM |
202 | if (err != HV_EOK) |
203 | printk("sun4v_intr_setenabled(%x): err(%d)\n", | |
204 | ino, err); | |
d82ace7d | 205 | } else { |
ebd8c56c | 206 | unsigned int tid = sun4u_compute_tid(imap, cpuid); |
1da177e4 | 207 | |
d82ace7d DM |
208 | /* NOTE NOTE NOTE, IGN and INO are read-only, IGN is a product |
209 | * of this SYSIO's preconfigured IGN in the SYSIO Control | |
210 | * Register, the hardware just mirrors that value here. | |
211 | * However for Graphics and UPA Slave devices the full | |
212 | * IMAP_INR field can be set by the programmer here. | |
213 | * | |
214 | * Things like FFB can now be handled via the new IRQ | |
215 | * mechanism. | |
216 | */ | |
217 | upa_writel(tid | IMAP_VALID, imap); | |
218 | } | |
1da177e4 LT |
219 | |
220 | preempt_enable(); | |
221 | } | |
222 | ||
223 | /* This now gets passed true ino's as well. */ | |
224 | void disable_irq(unsigned int irq) | |
225 | { | |
226 | struct ino_bucket *bucket = __bucket(irq); | |
227 | unsigned long imap; | |
228 | ||
229 | imap = bucket->imap; | |
230 | if (imap != 0UL) { | |
10951ee6 | 231 | if (tlb_type == hypervisor) { |
4bf447d6 | 232 | unsigned int ino = __irq_ino(irq); |
c4bea288 | 233 | int err; |
4bf447d6 | 234 | |
c4bea288 DM |
235 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
236 | if (err != HV_EOK) | |
237 | printk("sun4v_intr_setenabled(%x): " | |
238 | "err(%d)\n", ino, err); | |
10951ee6 DM |
239 | } else { |
240 | u32 tmp; | |
1da177e4 | 241 | |
10951ee6 DM |
242 | /* NOTE: We do not want to futz with the IRQ clear registers |
243 | * and move the state to IDLE, the SCSI code does call | |
244 | * disable_irq() to assure atomicity in the queue cmd | |
245 | * SCSI adapter driver code. Thus we'd lose interrupts. | |
246 | */ | |
247 | tmp = upa_readl(imap); | |
248 | tmp &= ~IMAP_VALID; | |
249 | upa_writel(tmp, imap); | |
250 | } | |
1da177e4 LT |
251 | } |
252 | } | |
253 | ||
254 | /* The timer is the one "weird" interrupt which is generated by | |
255 | * the CPU %tick register and not by some normal vectored interrupt | |
256 | * source. To handle this special case, we use this dummy INO bucket. | |
257 | */ | |
088dd1f8 | 258 | static struct irq_desc pil0_dummy_desc; |
1da177e4 | 259 | static struct ino_bucket pil0_dummy_bucket = { |
088dd1f8 | 260 | .irq_info = &pil0_dummy_desc, |
1da177e4 LT |
261 | }; |
262 | ||
088dd1f8 DM |
263 | static void build_irq_error(const char *msg, unsigned int ino, int pil, int inofixup, |
264 | unsigned long iclr, unsigned long imap, | |
265 | struct ino_bucket *bucket) | |
266 | { | |
267 | prom_printf("IRQ: INO %04x (%d:%016lx:%016lx) --> " | |
268 | "(%d:%d:%016lx:%016lx), halting...\n", | |
269 | ino, bucket->pil, bucket->iclr, bucket->imap, | |
270 | pil, inofixup, iclr, imap); | |
271 | prom_halt(); | |
272 | } | |
273 | ||
1da177e4 LT |
274 | unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap) |
275 | { | |
276 | struct ino_bucket *bucket; | |
277 | int ino; | |
278 | ||
279 | if (pil == 0) { | |
280 | if (iclr != 0UL || imap != 0UL) { | |
281 | prom_printf("Invalid dummy bucket for PIL0 (%lx:%lx)\n", | |
282 | iclr, imap); | |
283 | prom_halt(); | |
284 | } | |
285 | return __irq(&pil0_dummy_bucket); | |
286 | } | |
287 | ||
10951ee6 DM |
288 | BUG_ON(tlb_type == hypervisor); |
289 | ||
1da177e4 LT |
290 | /* RULE: Both must be specified in all other cases. */ |
291 | if (iclr == 0UL || imap == 0UL) { | |
292 | prom_printf("Invalid build_irq %d %d %016lx %016lx\n", | |
293 | pil, inofixup, iclr, imap); | |
294 | prom_halt(); | |
295 | } | |
296 | ||
297 | ino = (upa_readl(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; | |
298 | if (ino > NUM_IVECS) { | |
299 | prom_printf("Invalid INO %04x (%d:%d:%016lx:%016lx)\n", | |
300 | ino, pil, inofixup, iclr, imap); | |
301 | prom_halt(); | |
302 | } | |
303 | ||
1da177e4 | 304 | bucket = &ivector_table[ino]; |
088dd1f8 DM |
305 | if (bucket->flags & IBF_ACTIVE) |
306 | build_irq_error("IRQ: Trying to build active INO bucket.\n", | |
307 | ino, pil, inofixup, iclr, imap, bucket); | |
308 | ||
309 | if (bucket->irq_info) { | |
310 | if (bucket->imap != imap || bucket->iclr != iclr) | |
311 | build_irq_error("IRQ: Trying to reinit INO bucket.\n", | |
312 | ino, pil, inofixup, iclr, imap, bucket); | |
313 | ||
314 | goto out; | |
315 | } | |
316 | ||
9132983a | 317 | bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC); |
088dd1f8 DM |
318 | if (!bucket->irq_info) { |
319 | prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n"); | |
1da177e4 LT |
320 | prom_halt(); |
321 | } | |
088dd1f8 DM |
322 | |
323 | /* Ok, looks good, set it up. Don't touch the irq_chain or | |
324 | * the pending flag. | |
325 | */ | |
1da177e4 LT |
326 | bucket->imap = imap; |
327 | bucket->iclr = iclr; | |
328 | bucket->pil = pil; | |
329 | bucket->flags = 0; | |
330 | ||
088dd1f8 | 331 | out: |
1da177e4 LT |
332 | return __irq(bucket); |
333 | } | |
334 | ||
e3999574 DM |
335 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino, int pil, unsigned char flags) |
336 | { | |
337 | struct ino_bucket *bucket; | |
338 | unsigned long sysino; | |
339 | ||
340 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
341 | ||
e3999574 DM |
342 | bucket = &ivector_table[sysino]; |
343 | ||
344 | /* Catch accidental accesses to these things. IMAP/ICLR handling | |
345 | * is done by hypervisor calls on sun4v platforms, not by direct | |
346 | * register accesses. | |
22780e23 DM |
347 | * |
348 | * But we need to make them look unique for the disable_irq() logic | |
349 | * in free_irq(). | |
e3999574 | 350 | */ |
22780e23 DM |
351 | bucket->imap = ~0UL - sysino; |
352 | bucket->iclr = ~0UL - sysino; | |
e3999574 DM |
353 | |
354 | bucket->pil = pil; | |
355 | bucket->flags = flags; | |
356 | ||
9132983a | 357 | bucket->irq_info = kzalloc(sizeof(struct irq_desc), GFP_ATOMIC); |
e3999574 DM |
358 | if (!bucket->irq_info) { |
359 | prom_printf("IRQ: Error, kmalloc(irq_desc) failed.\n"); | |
360 | prom_halt(); | |
361 | } | |
e3999574 DM |
362 | |
363 | return __irq(bucket); | |
364 | } | |
365 | ||
1da177e4 LT |
366 | static void atomic_bucket_insert(struct ino_bucket *bucket) |
367 | { | |
368 | unsigned long pstate; | |
369 | unsigned int *ent; | |
370 | ||
371 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
372 | __asm__ __volatile__("wrpr %0, %1, %%pstate" | |
373 | : : "r" (pstate), "i" (PSTATE_IE)); | |
374 | ent = irq_work(smp_processor_id(), bucket->pil); | |
375 | bucket->irq_chain = *ent; | |
376 | *ent = __irq(bucket); | |
377 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate)); | |
378 | } | |
379 | ||
088dd1f8 DM |
380 | static int check_irq_sharing(int pil, unsigned long irqflags) |
381 | { | |
382 | struct irqaction *action, *tmp; | |
383 | ||
384 | action = *(irq_action + pil); | |
385 | if (action) { | |
386 | if ((action->flags & SA_SHIRQ) && (irqflags & SA_SHIRQ)) { | |
387 | for (tmp = action; tmp->next; tmp = tmp->next) | |
388 | ; | |
389 | } else { | |
390 | return -EBUSY; | |
391 | } | |
392 | } | |
393 | return 0; | |
394 | } | |
395 | ||
396 | static void append_irq_action(int pil, struct irqaction *action) | |
397 | { | |
398 | struct irqaction **pp = irq_action + pil; | |
399 | ||
400 | while (*pp) | |
401 | pp = &((*pp)->next); | |
402 | *pp = action; | |
403 | } | |
404 | ||
405 | static struct irqaction *get_action_slot(struct ino_bucket *bucket) | |
406 | { | |
407 | struct irq_desc *desc = bucket->irq_info; | |
408 | int max_irq, i; | |
409 | ||
410 | max_irq = 1; | |
411 | if (bucket->flags & IBF_PCI) | |
412 | max_irq = MAX_IRQ_DESC_ACTION; | |
413 | for (i = 0; i < max_irq; i++) { | |
414 | struct irqaction *p = &desc->action[i]; | |
415 | u32 mask = (1 << i); | |
416 | ||
417 | if (desc->action_active_mask & mask) | |
418 | continue; | |
419 | ||
420 | desc->action_active_mask |= mask; | |
421 | return p; | |
422 | } | |
423 | return NULL; | |
424 | } | |
425 | ||
1da177e4 LT |
426 | int request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), |
427 | unsigned long irqflags, const char *name, void *dev_id) | |
428 | { | |
088dd1f8 | 429 | struct irqaction *action; |
1da177e4 LT |
430 | struct ino_bucket *bucket = __bucket(irq); |
431 | unsigned long flags; | |
432 | int pending = 0; | |
433 | ||
088dd1f8 | 434 | if (unlikely(!handler)) |
1da177e4 | 435 | return -EINVAL; |
088dd1f8 DM |
436 | |
437 | if (unlikely(!bucket->irq_info)) | |
438 | return -ENODEV; | |
1da177e4 LT |
439 | |
440 | if ((bucket != &pil0_dummy_bucket) && (irqflags & SA_SAMPLE_RANDOM)) { | |
441 | /* | |
442 | * This function might sleep, we want to call it first, | |
443 | * outside of the atomic block. In SA_STATIC_ALLOC case, | |
444 | * random driver's kmalloc will fail, but it is safe. | |
445 | * If already initialized, random driver will not reinit. | |
446 | * Yes, this might clear the entropy pool if the wrong | |
447 | * driver is attempted to be loaded, without actually | |
448 | * installing a new handler, but is this really a problem, | |
449 | * only the sysadmin is able to do this. | |
450 | */ | |
451 | rand_initialize_irq(irq); | |
452 | } | |
453 | ||
454 | spin_lock_irqsave(&irq_action_lock, flags); | |
455 | ||
088dd1f8 DM |
456 | if (check_irq_sharing(bucket->pil, irqflags)) { |
457 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
458 | return -EBUSY; | |
1da177e4 LT |
459 | } |
460 | ||
088dd1f8 | 461 | action = get_action_slot(bucket); |
1da177e4 LT |
462 | if (!action) { |
463 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
464 | return -ENOMEM; | |
465 | } | |
466 | ||
088dd1f8 DM |
467 | bucket->flags |= IBF_ACTIVE; |
468 | pending = 0; | |
469 | if (bucket != &pil0_dummy_bucket) { | |
1da177e4 LT |
470 | pending = bucket->pending; |
471 | if (pending) | |
472 | bucket->pending = 0; | |
473 | } | |
474 | ||
475 | action->handler = handler; | |
476 | action->flags = irqflags; | |
477 | action->name = name; | |
478 | action->next = NULL; | |
479 | action->dev_id = dev_id; | |
480 | put_ino_in_irqaction(action, irq); | |
481 | put_smpaff_in_irqaction(action, CPU_MASK_NONE); | |
482 | ||
088dd1f8 | 483 | append_irq_action(bucket->pil, action); |
1da177e4 LT |
484 | |
485 | enable_irq(irq); | |
486 | ||
487 | /* We ate the IVEC already, this makes sure it does not get lost. */ | |
488 | if (pending) { | |
489 | atomic_bucket_insert(bucket); | |
490 | set_softint(1 << bucket->pil); | |
491 | } | |
088dd1f8 | 492 | |
1da177e4 | 493 | spin_unlock_irqrestore(&irq_action_lock, flags); |
088dd1f8 DM |
494 | |
495 | if (bucket != &pil0_dummy_bucket) | |
1da177e4 LT |
496 | register_irq_proc(__irq_ino(irq)); |
497 | ||
498 | #ifdef CONFIG_SMP | |
499 | distribute_irqs(); | |
500 | #endif | |
501 | return 0; | |
1da177e4 LT |
502 | } |
503 | ||
504 | EXPORT_SYMBOL(request_irq); | |
505 | ||
088dd1f8 | 506 | static struct irqaction *unlink_irq_action(unsigned int irq, void *dev_id) |
1da177e4 | 507 | { |
088dd1f8 DM |
508 | struct ino_bucket *bucket = __bucket(irq); |
509 | struct irqaction *action, **pp; | |
1da177e4 | 510 | |
088dd1f8 DM |
511 | pp = irq_action + bucket->pil; |
512 | action = *pp; | |
513 | if (unlikely(!action)) | |
514 | return NULL; | |
1da177e4 | 515 | |
088dd1f8 | 516 | if (unlikely(!action->handler)) { |
1da177e4 | 517 | printk("Freeing free IRQ %d\n", bucket->pil); |
088dd1f8 | 518 | return NULL; |
1da177e4 LT |
519 | } |
520 | ||
088dd1f8 DM |
521 | while (action && action->dev_id != dev_id) { |
522 | pp = &action->next; | |
523 | action = *pp; | |
1da177e4 LT |
524 | } |
525 | ||
088dd1f8 DM |
526 | if (likely(action)) |
527 | *pp = action->next; | |
528 | ||
529 | return action; | |
530 | } | |
531 | ||
532 | void free_irq(unsigned int irq, void *dev_id) | |
533 | { | |
534 | struct irqaction *action; | |
535 | struct ino_bucket *bucket; | |
536 | unsigned long flags; | |
537 | ||
538 | spin_lock_irqsave(&irq_action_lock, flags); | |
539 | ||
540 | action = unlink_irq_action(irq, dev_id); | |
1da177e4 LT |
541 | |
542 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
543 | ||
088dd1f8 DM |
544 | if (unlikely(!action)) |
545 | return; | |
546 | ||
1da177e4 LT |
547 | synchronize_irq(irq); |
548 | ||
549 | spin_lock_irqsave(&irq_action_lock, flags); | |
550 | ||
088dd1f8 | 551 | bucket = __bucket(irq); |
1da177e4 | 552 | if (bucket != &pil0_dummy_bucket) { |
088dd1f8 | 553 | struct irq_desc *desc = bucket->irq_info; |
088dd1f8 | 554 | int ent, i; |
1da177e4 | 555 | |
088dd1f8 DM |
556 | for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) { |
557 | struct irqaction *p = &desc->action[i]; | |
558 | ||
559 | if (p == action) { | |
560 | desc->action_active_mask &= ~(1 << i); | |
561 | break; | |
1da177e4 | 562 | } |
1da177e4 LT |
563 | } |
564 | ||
088dd1f8 | 565 | if (!desc->action_active_mask) { |
22780e23 DM |
566 | unsigned long imap = bucket->imap; |
567 | ||
088dd1f8 DM |
568 | /* This unique interrupt source is now inactive. */ |
569 | bucket->flags &= ~IBF_ACTIVE; | |
1da177e4 | 570 | |
088dd1f8 DM |
571 | /* See if any other buckets share this bucket's IMAP |
572 | * and are still active. | |
573 | */ | |
574 | for (ent = 0; ent < NUM_IVECS; ent++) { | |
575 | struct ino_bucket *bp = &ivector_table[ent]; | |
576 | if (bp != bucket && | |
577 | bp->imap == imap && | |
578 | (bp->flags & IBF_ACTIVE) != 0) | |
579 | break; | |
580 | } | |
1da177e4 | 581 | |
088dd1f8 DM |
582 | /* Only disable when no other sub-irq levels of |
583 | * the same IMAP are active. | |
584 | */ | |
585 | if (ent == NUM_IVECS) | |
586 | disable_irq(irq); | |
587 | } | |
1da177e4 LT |
588 | } |
589 | ||
1da177e4 LT |
590 | spin_unlock_irqrestore(&irq_action_lock, flags); |
591 | } | |
592 | ||
593 | EXPORT_SYMBOL(free_irq); | |
594 | ||
595 | #ifdef CONFIG_SMP | |
596 | void synchronize_irq(unsigned int irq) | |
597 | { | |
598 | struct ino_bucket *bucket = __bucket(irq); | |
599 | ||
600 | #if 0 | |
601 | /* The following is how I wish I could implement this. | |
602 | * Unfortunately the ICLR registers are read-only, you can | |
603 | * only write ICLR_foo values to them. To get the current | |
604 | * IRQ status you would need to get at the IRQ diag registers | |
605 | * in the PCI/SBUS controller and the layout of those vary | |
606 | * from one controller to the next, sigh... -DaveM | |
607 | */ | |
608 | unsigned long iclr = bucket->iclr; | |
609 | ||
610 | while (1) { | |
611 | u32 tmp = upa_readl(iclr); | |
612 | ||
613 | if (tmp == ICLR_TRANSMIT || | |
614 | tmp == ICLR_PENDING) { | |
615 | cpu_relax(); | |
616 | continue; | |
617 | } | |
618 | break; | |
619 | } | |
620 | #else | |
621 | /* So we have to do this with a INPROGRESS bit just like x86. */ | |
622 | while (bucket->flags & IBF_INPROGRESS) | |
623 | cpu_relax(); | |
624 | #endif | |
625 | } | |
626 | #endif /* CONFIG_SMP */ | |
627 | ||
088dd1f8 | 628 | static void process_bucket(int irq, struct ino_bucket *bp, struct pt_regs *regs) |
1da177e4 | 629 | { |
088dd1f8 DM |
630 | struct irq_desc *desc = bp->irq_info; |
631 | unsigned char flags = bp->flags; | |
632 | u32 action_mask, i; | |
633 | int random; | |
1da177e4 | 634 | |
088dd1f8 | 635 | bp->flags |= IBF_INPROGRESS; |
1da177e4 | 636 | |
088dd1f8 DM |
637 | if (unlikely(!(flags & IBF_ACTIVE))) { |
638 | bp->pending = 1; | |
1da177e4 | 639 | goto out; |
1da177e4 LT |
640 | } |
641 | ||
088dd1f8 DM |
642 | if (desc->pre_handler) |
643 | desc->pre_handler(bp, | |
644 | desc->pre_handler_arg1, | |
645 | desc->pre_handler_arg2); | |
1da177e4 | 646 | |
088dd1f8 DM |
647 | action_mask = desc->action_active_mask; |
648 | random = 0; | |
649 | for (i = 0; i < MAX_IRQ_DESC_ACTION; i++) { | |
650 | struct irqaction *p = &desc->action[i]; | |
651 | u32 mask = (1 << i); | |
1da177e4 | 652 | |
088dd1f8 DM |
653 | if (!(action_mask & mask)) |
654 | continue; | |
1da177e4 | 655 | |
088dd1f8 | 656 | action_mask &= ~mask; |
1da177e4 | 657 | |
088dd1f8 DM |
658 | if (p->handler(__irq(bp), p->dev_id, regs) == IRQ_HANDLED) |
659 | random |= p->flags; | |
660 | ||
661 | if (!action_mask) | |
662 | break; | |
663 | } | |
664 | if (bp->pil != 0) { | |
10951ee6 | 665 | if (tlb_type == hypervisor) { |
4bf447d6 | 666 | unsigned int ino = __irq_ino(bp); |
c4bea288 | 667 | int err; |
10951ee6 | 668 | |
c4bea288 DM |
669 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
670 | if (err != HV_EOK) | |
671 | printk("sun4v_intr_setstate(%x): " | |
672 | "err(%d)\n", ino, err); | |
10951ee6 DM |
673 | } else { |
674 | upa_writel(ICLR_IDLE, bp->iclr); | |
10951ee6 | 675 | } |
ab66a50e DM |
676 | |
677 | /* Test and add entropy */ | |
678 | if (random & SA_SAMPLE_RANDOM) | |
679 | add_interrupt_randomness(irq); | |
088dd1f8 | 680 | } |
1da177e4 | 681 | out: |
088dd1f8 | 682 | bp->flags &= ~IBF_INPROGRESS; |
1da177e4 LT |
683 | } |
684 | ||
1da177e4 LT |
685 | void handler_irq(int irq, struct pt_regs *regs) |
686 | { | |
088dd1f8 | 687 | struct ino_bucket *bp; |
1da177e4 LT |
688 | int cpu = smp_processor_id(); |
689 | ||
690 | #ifndef CONFIG_SMP | |
691 | /* | |
692 | * Check for TICK_INT on level 14 softint. | |
693 | */ | |
694 | { | |
695 | unsigned long clr_mask = 1 << irq; | |
696 | unsigned long tick_mask = tick_ops->softint_mask; | |
697 | ||
698 | if ((irq == 14) && (get_softint() & tick_mask)) { | |
699 | irq = 0; | |
700 | clr_mask = tick_mask; | |
701 | } | |
702 | clear_softint(clr_mask); | |
703 | } | |
704 | #else | |
1da177e4 LT |
705 | clear_softint(1 << irq); |
706 | #endif | |
707 | ||
708 | irq_enter(); | |
709 | kstat_this_cpu.irqs[irq]++; | |
710 | ||
711 | /* Sliiiick... */ | |
712 | #ifndef CONFIG_SMP | |
713 | bp = ((irq != 0) ? | |
714 | __bucket(xchg32(irq_work(cpu, irq), 0)) : | |
715 | &pil0_dummy_bucket); | |
716 | #else | |
717 | bp = __bucket(xchg32(irq_work(cpu, irq), 0)); | |
718 | #endif | |
088dd1f8 DM |
719 | while (bp) { |
720 | struct ino_bucket *nbp = __bucket(bp->irq_chain); | |
1da177e4 | 721 | |
1da177e4 | 722 | bp->irq_chain = 0; |
088dd1f8 DM |
723 | process_bucket(irq, bp, regs); |
724 | bp = nbp; | |
1da177e4 LT |
725 | } |
726 | irq_exit(); | |
727 | } | |
728 | ||
729 | #ifdef CONFIG_BLK_DEV_FD | |
63b61452 | 730 | extern irqreturn_t floppy_interrupt(int, void *, struct pt_regs *);; |
1da177e4 | 731 | |
63b61452 DM |
732 | /* XXX No easy way to include asm/floppy.h XXX */ |
733 | extern unsigned char *pdma_vaddr; | |
734 | extern unsigned long pdma_size; | |
735 | extern volatile int doing_pdma; | |
736 | extern unsigned long fdc_status; | |
1da177e4 | 737 | |
63b61452 | 738 | irqreturn_t sparc_floppy_irq(int irq, void *dev_cookie, struct pt_regs *regs) |
1da177e4 | 739 | { |
63b61452 DM |
740 | if (likely(doing_pdma)) { |
741 | void __iomem *stat = (void __iomem *) fdc_status; | |
742 | unsigned char *vaddr = pdma_vaddr; | |
743 | unsigned long size = pdma_size; | |
744 | u8 val; | |
745 | ||
746 | while (size) { | |
747 | val = readb(stat); | |
748 | if (unlikely(!(val & 0x80))) { | |
749 | pdma_vaddr = vaddr; | |
750 | pdma_size = size; | |
751 | return IRQ_HANDLED; | |
752 | } | |
753 | if (unlikely(!(val & 0x20))) { | |
754 | pdma_vaddr = vaddr; | |
755 | pdma_size = size; | |
756 | doing_pdma = 0; | |
757 | goto main_interrupt; | |
758 | } | |
759 | if (val & 0x40) { | |
760 | /* read */ | |
761 | *vaddr++ = readb(stat + 1); | |
762 | } else { | |
763 | unsigned char data = *vaddr++; | |
1da177e4 | 764 | |
63b61452 DM |
765 | /* write */ |
766 | writeb(data, stat + 1); | |
767 | } | |
768 | size--; | |
769 | } | |
1da177e4 | 770 | |
63b61452 DM |
771 | pdma_vaddr = vaddr; |
772 | pdma_size = size; | |
1da177e4 | 773 | |
63b61452 DM |
774 | /* Send Terminal Count pulse to floppy controller. */ |
775 | val = readb(auxio_register); | |
776 | val |= AUXIO_AUX1_FTCNT; | |
777 | writeb(val, auxio_register); | |
94bbc176 | 778 | val &= ~AUXIO_AUX1_FTCNT; |
63b61452 | 779 | writeb(val, auxio_register); |
1da177e4 | 780 | |
63b61452 | 781 | doing_pdma = 0; |
1da177e4 | 782 | } |
1da177e4 | 783 | |
63b61452 DM |
784 | main_interrupt: |
785 | return floppy_interrupt(irq, dev_cookie, regs); | |
1da177e4 | 786 | } |
63b61452 DM |
787 | EXPORT_SYMBOL(sparc_floppy_irq); |
788 | #endif | |
1da177e4 LT |
789 | |
790 | /* We really don't need these at all on the Sparc. We only have | |
791 | * stubs here because they are exported to modules. | |
792 | */ | |
793 | unsigned long probe_irq_on(void) | |
794 | { | |
795 | return 0; | |
796 | } | |
797 | ||
798 | EXPORT_SYMBOL(probe_irq_on); | |
799 | ||
800 | int probe_irq_off(unsigned long mask) | |
801 | { | |
802 | return 0; | |
803 | } | |
804 | ||
805 | EXPORT_SYMBOL(probe_irq_off); | |
806 | ||
807 | #ifdef CONFIG_SMP | |
808 | static int retarget_one_irq(struct irqaction *p, int goal_cpu) | |
809 | { | |
810 | struct ino_bucket *bucket = get_ino_in_irqaction(p) + ivector_table; | |
1da177e4 LT |
811 | |
812 | while (!cpu_online(goal_cpu)) { | |
813 | if (++goal_cpu >= NR_CPUS) | |
814 | goal_cpu = 0; | |
815 | } | |
816 | ||
10951ee6 | 817 | if (tlb_type == hypervisor) { |
4bf447d6 | 818 | unsigned int ino = __irq_ino(bucket); |
10951ee6 | 819 | |
4bf447d6 DM |
820 | sun4v_intr_settarget(ino, goal_cpu); |
821 | sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
1da177e4 | 822 | } else { |
22780e23 | 823 | unsigned long imap = bucket->imap; |
ebd8c56c | 824 | unsigned int tid = sun4u_compute_tid(imap, goal_cpu); |
10951ee6 | 825 | |
10951ee6 | 826 | upa_writel(tid | IMAP_VALID, imap); |
1da177e4 | 827 | } |
1da177e4 | 828 | |
cee2824f | 829 | do { |
1da177e4 LT |
830 | if (++goal_cpu >= NR_CPUS) |
831 | goal_cpu = 0; | |
cee2824f | 832 | } while (!cpu_online(goal_cpu)); |
1da177e4 LT |
833 | |
834 | return goal_cpu; | |
835 | } | |
836 | ||
837 | /* Called from request_irq. */ | |
838 | static void distribute_irqs(void) | |
839 | { | |
840 | unsigned long flags; | |
841 | int cpu, level; | |
842 | ||
843 | spin_lock_irqsave(&irq_action_lock, flags); | |
844 | cpu = 0; | |
845 | ||
846 | /* | |
847 | * Skip the timer at [0], and very rare error/power intrs at [15]. | |
848 | * Also level [12], it causes problems on Ex000 systems. | |
849 | */ | |
850 | for (level = 1; level < NR_IRQS; level++) { | |
851 | struct irqaction *p = irq_action[level]; | |
088dd1f8 DM |
852 | |
853 | if (level == 12) | |
854 | continue; | |
855 | ||
1da177e4 LT |
856 | while(p) { |
857 | cpu = retarget_one_irq(p, cpu); | |
858 | p = p->next; | |
859 | } | |
860 | } | |
861 | spin_unlock_irqrestore(&irq_action_lock, flags); | |
862 | } | |
863 | #endif | |
864 | ||
cdd5186f DM |
865 | struct sun5_timer { |
866 | u64 count0; | |
867 | u64 limit0; | |
868 | u64 count1; | |
869 | u64 limit1; | |
870 | }; | |
1da177e4 | 871 | |
cdd5186f | 872 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
873 | static u64 prom_limit0, prom_limit1; |
874 | ||
875 | static void map_prom_timers(void) | |
876 | { | |
877 | unsigned int addr[3]; | |
878 | int tnode, err; | |
879 | ||
880 | /* PROM timer node hangs out in the top level of device siblings... */ | |
881 | tnode = prom_finddevice("/counter-timer"); | |
882 | ||
883 | /* Assume if node is not present, PROM uses different tick mechanism | |
884 | * which we should not care about. | |
885 | */ | |
886 | if (tnode == 0 || tnode == -1) { | |
887 | prom_timers = (struct sun5_timer *) 0; | |
888 | return; | |
889 | } | |
890 | ||
891 | /* If PROM is really using this, it must be mapped by him. */ | |
892 | err = prom_getproperty(tnode, "address", (char *)addr, sizeof(addr)); | |
893 | if (err == -1) { | |
894 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); | |
895 | prom_timers = (struct sun5_timer *) 0; | |
896 | return; | |
897 | } | |
898 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
899 | } | |
900 | ||
901 | static void kill_prom_timer(void) | |
902 | { | |
903 | if (!prom_timers) | |
904 | return; | |
905 | ||
906 | /* Save them away for later. */ | |
907 | prom_limit0 = prom_timers->limit0; | |
908 | prom_limit1 = prom_timers->limit1; | |
909 | ||
910 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
911 | * We turn both off here just to be paranoid. | |
912 | */ | |
913 | prom_timers->limit0 = 0; | |
914 | prom_timers->limit1 = 0; | |
915 | ||
916 | /* Wheee, eat the interrupt packet too... */ | |
917 | __asm__ __volatile__( | |
918 | " mov 0x40, %%g2\n" | |
919 | " ldxa [%%g0] %0, %%g1\n" | |
920 | " ldxa [%%g2] %1, %%g1\n" | |
921 | " stxa %%g0, [%%g0] %0\n" | |
922 | " membar #Sync\n" | |
923 | : /* no outputs */ | |
924 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
925 | : "g1", "g2"); | |
926 | } | |
927 | ||
1da177e4 LT |
928 | void init_irqwork_curcpu(void) |
929 | { | |
1da177e4 LT |
930 | int cpu = hard_smp_processor_id(); |
931 | ||
56fb4df6 | 932 | memset(__irq_work + cpu, 0, sizeof(struct irq_work_struct)); |
1da177e4 LT |
933 | } |
934 | ||
b5a37e96 | 935 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type) |
ac29c11d | 936 | { |
94f8762d DM |
937 | unsigned long num_entries = 128; |
938 | unsigned long status; | |
939 | ||
940 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
941 | if (status != HV_EOK) { | |
942 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
943 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
944 | prom_halt(); |
945 | } | |
946 | } | |
947 | ||
b5a37e96 | 948 | static void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 949 | { |
b5a37e96 DM |
950 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
951 | ||
952 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO); | |
953 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO); | |
954 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR); | |
955 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR); | |
956 | } | |
957 | ||
958 | static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, int use_bootmem) | |
959 | { | |
960 | void *page; | |
961 | ||
962 | if (use_bootmem) | |
963 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
964 | else | |
965 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
966 | ||
967 | if (!page) { | |
968 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); | |
969 | prom_halt(); | |
970 | } | |
971 | ||
972 | *pa_ptr = __pa(page); | |
973 | } | |
974 | ||
975 | static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, int use_bootmem) | |
976 | { | |
977 | void *page; | |
978 | ||
979 | if (use_bootmem) | |
980 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
981 | else | |
982 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
5b0c0572 DM |
983 | |
984 | if (!page) { | |
985 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); | |
986 | prom_halt(); | |
987 | } | |
988 | ||
989 | *pa_ptr = __pa(page); | |
990 | } | |
991 | ||
b5a37e96 | 992 | static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem) |
1d2f1f90 DM |
993 | { |
994 | #ifdef CONFIG_SMP | |
b5a37e96 | 995 | void *page; |
1d2f1f90 DM |
996 | |
997 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
998 | ||
b5a37e96 DM |
999 | if (use_bootmem) |
1000 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
1001 | else | |
1002 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
1003 | ||
1d2f1f90 DM |
1004 | if (!page) { |
1005 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
1006 | prom_halt(); | |
1007 | } | |
1008 | ||
1009 | tb->cpu_mondo_block_pa = __pa(page); | |
1010 | tb->cpu_list_pa = __pa(page + 64); | |
1011 | #endif | |
1012 | } | |
1013 | ||
b5a37e96 | 1014 | /* Allocate and register the mondo and error queues for this cpu. */ |
72aff53f | 1015 | void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load) |
ac29c11d | 1016 | { |
ac29c11d DM |
1017 | struct trap_per_cpu *tb = &trap_block[cpu]; |
1018 | ||
72aff53f DM |
1019 | if (alloc) { |
1020 | alloc_one_mondo(&tb->cpu_mondo_pa, use_bootmem); | |
1021 | alloc_one_mondo(&tb->dev_mondo_pa, use_bootmem); | |
1022 | alloc_one_mondo(&tb->resum_mondo_pa, use_bootmem); | |
1023 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, use_bootmem); | |
1024 | alloc_one_mondo(&tb->nonresum_mondo_pa, use_bootmem); | |
1025 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, use_bootmem); | |
1d2f1f90 | 1026 | |
72aff53f DM |
1027 | init_cpu_send_mondo_info(tb, use_bootmem); |
1028 | } | |
1d2f1f90 | 1029 | |
72aff53f DM |
1030 | if (load) { |
1031 | if (cpu != hard_smp_processor_id()) { | |
1032 | prom_printf("SUN4V: init mondo on cpu %d not %d\n", | |
1033 | cpu, hard_smp_processor_id()); | |
1034 | prom_halt(); | |
1035 | } | |
1036 | sun4v_register_mondo_queues(cpu); | |
1037 | } | |
ac29c11d DM |
1038 | } |
1039 | ||
1da177e4 LT |
1040 | /* Only invoked on boot processor. */ |
1041 | void __init init_IRQ(void) | |
1042 | { | |
1043 | map_prom_timers(); | |
1044 | kill_prom_timer(); | |
1045 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
1046 | ||
ac29c11d | 1047 | if (tlb_type == hypervisor) |
72aff53f | 1048 | sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1); |
ac29c11d | 1049 | |
1da177e4 LT |
1050 | /* We need to clear any IRQ's pending in the soft interrupt |
1051 | * registers, a spurious one could be left around from the | |
1052 | * PROM timer which we just disabled. | |
1053 | */ | |
1054 | clear_softint(get_softint()); | |
1055 | ||
1056 | /* Now that ivector table is initialized, it is safe | |
1057 | * to receive IRQ vector traps. We will normally take | |
1058 | * one or two right now, in case some device PROM used | |
1059 | * to boot us wants to speak to us. We just ignore them. | |
1060 | */ | |
1061 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
1062 | "or %%g1, %0, %%g1\n\t" | |
1063 | "wrpr %%g1, 0x0, %%pstate" | |
1064 | : /* No outputs */ | |
1065 | : "i" (PSTATE_IE) | |
1066 | : "g1"); | |
1067 | } | |
1068 | ||
1069 | static struct proc_dir_entry * root_irq_dir; | |
1070 | static struct proc_dir_entry * irq_dir [NUM_IVECS]; | |
1071 | ||
1072 | #ifdef CONFIG_SMP | |
1073 | ||
1074 | static int irq_affinity_read_proc (char *page, char **start, off_t off, | |
1075 | int count, int *eof, void *data) | |
1076 | { | |
1077 | struct ino_bucket *bp = ivector_table + (long)data; | |
12cf649f ED |
1078 | struct irq_desc *desc = bp->irq_info; |
1079 | struct irqaction *ap = desc->action; | |
1da177e4 LT |
1080 | cpumask_t mask; |
1081 | int len; | |
1082 | ||
1083 | mask = get_smpaff_in_irqaction(ap); | |
1084 | if (cpus_empty(mask)) | |
1085 | mask = cpu_online_map; | |
1086 | ||
1087 | len = cpumask_scnprintf(page, count, mask); | |
1088 | if (count - len < 2) | |
1089 | return -EINVAL; | |
1090 | len += sprintf(page + len, "\n"); | |
1091 | return len; | |
1092 | } | |
1093 | ||
1094 | static inline void set_intr_affinity(int irq, cpumask_t hw_aff) | |
1095 | { | |
1096 | struct ino_bucket *bp = ivector_table + irq; | |
12cf649f ED |
1097 | struct irq_desc *desc = bp->irq_info; |
1098 | struct irqaction *ap = desc->action; | |
1da177e4 LT |
1099 | |
1100 | /* Users specify affinity in terms of hw cpu ids. | |
1101 | * As soon as we do this, handler_irq() might see and take action. | |
1102 | */ | |
12cf649f | 1103 | put_smpaff_in_irqaction(ap, hw_aff); |
1da177e4 LT |
1104 | |
1105 | /* Migration is simply done by the next cpu to service this | |
1106 | * interrupt. | |
1107 | */ | |
1108 | } | |
1109 | ||
1110 | static int irq_affinity_write_proc (struct file *file, const char __user *buffer, | |
1111 | unsigned long count, void *data) | |
1112 | { | |
1113 | int irq = (long) data, full_count = count, err; | |
1114 | cpumask_t new_value; | |
1115 | ||
1116 | err = cpumask_parse(buffer, count, new_value); | |
1117 | ||
1118 | /* | |
1119 | * Do not allow disabling IRQs completely - it's a too easy | |
1120 | * way to make the system unusable accidentally :-) At least | |
1121 | * one online CPU still has to be targeted. | |
1122 | */ | |
1123 | cpus_and(new_value, new_value, cpu_online_map); | |
1124 | if (cpus_empty(new_value)) | |
1125 | return -EINVAL; | |
1126 | ||
1127 | set_intr_affinity(irq, new_value); | |
1128 | ||
1129 | return full_count; | |
1130 | } | |
1131 | ||
1132 | #endif | |
1133 | ||
1134 | #define MAX_NAMELEN 10 | |
1135 | ||
1136 | static void register_irq_proc (unsigned int irq) | |
1137 | { | |
1138 | char name [MAX_NAMELEN]; | |
1139 | ||
1140 | if (!root_irq_dir || irq_dir[irq]) | |
1141 | return; | |
1142 | ||
1143 | memset(name, 0, MAX_NAMELEN); | |
1144 | sprintf(name, "%x", irq); | |
1145 | ||
1146 | /* create /proc/irq/1234 */ | |
1147 | irq_dir[irq] = proc_mkdir(name, root_irq_dir); | |
1148 | ||
1149 | #ifdef CONFIG_SMP | |
1150 | /* XXX SMP affinity not supported on starfire yet. */ | |
1151 | if (this_is_starfire == 0) { | |
1152 | struct proc_dir_entry *entry; | |
1153 | ||
1154 | /* create /proc/irq/1234/smp_affinity */ | |
1155 | entry = create_proc_entry("smp_affinity", 0600, irq_dir[irq]); | |
1156 | ||
1157 | if (entry) { | |
1158 | entry->nlink = 1; | |
1159 | entry->data = (void *)(long)irq; | |
1160 | entry->read_proc = irq_affinity_read_proc; | |
1161 | entry->write_proc = irq_affinity_write_proc; | |
1162 | } | |
1163 | } | |
1164 | #endif | |
1165 | } | |
1166 | ||
1167 | void init_irq_proc (void) | |
1168 | { | |
1169 | /* create /proc/irq */ | |
1170 | root_irq_dir = proc_mkdir("irq", NULL); | |
1171 | } | |
1172 |