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4a907dec | 1 | /* irq.c: UltraSparc IRQ handling/init/registry. |
1da177e4 | 2 | * |
4a907dec | 3 | * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
6 | */ | |
7 | ||
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/sched.h> | |
10 | #include <linux/ptrace.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/signal.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/random.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/proc_fs.h> | |
21 | #include <linux/seq_file.h> | |
b5a37e96 | 22 | #include <linux/bootmem.h> |
e18e2a00 | 23 | #include <linux/irq.h> |
1da177e4 LT |
24 | |
25 | #include <asm/ptrace.h> | |
26 | #include <asm/processor.h> | |
27 | #include <asm/atomic.h> | |
28 | #include <asm/system.h> | |
29 | #include <asm/irq.h> | |
2e457ef6 | 30 | #include <asm/io.h> |
1da177e4 LT |
31 | #include <asm/sbus.h> |
32 | #include <asm/iommu.h> | |
33 | #include <asm/upa.h> | |
34 | #include <asm/oplib.h> | |
25c7581b | 35 | #include <asm/prom.h> |
1da177e4 LT |
36 | #include <asm/timer.h> |
37 | #include <asm/smp.h> | |
38 | #include <asm/starfire.h> | |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/cache.h> | |
41 | #include <asm/cpudata.h> | |
63b61452 | 42 | #include <asm/auxio.h> |
92704a1c | 43 | #include <asm/head.h> |
4a907dec | 44 | #include <asm/hypervisor.h> |
42d5f99b | 45 | #include <asm/cacheflush.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | /* UPA nodes send interrupt packet to UltraSparc with first data reg |
48 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
49 | * delivered. We must translate this into a non-vector IRQ so we can | |
50 | * set the softint on this cpu. | |
51 | * | |
52 | * To make processing these packets efficient and race free we use | |
53 | * an array of irq buckets below. The interrupt vector handler in | |
54 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
e18e2a00 DM |
55 | * |
56 | * If you make changes to ino_bucket, please update hand coded assembler | |
57 | * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S | |
1da177e4 | 58 | */ |
e18e2a00 | 59 | struct ino_bucket { |
42d5f99b | 60 | /*0x00*/unsigned long __irq_chain_pa; |
1da177e4 | 61 | |
e18e2a00 | 62 | /* Virtual interrupt number assigned to this INO. */ |
42d5f99b | 63 | /*0x08*/unsigned int __virt_irq; |
a650d383 | 64 | /*0x0c*/unsigned int __pad; |
e18e2a00 DM |
65 | }; |
66 | ||
67 | #define NUM_IVECS (IMAP_INR + 1) | |
10397e40 | 68 | struct ino_bucket *ivector_table; |
eb2d8d60 | 69 | unsigned long ivector_table_pa; |
1da177e4 | 70 | |
42d5f99b DM |
71 | /* On several sun4u processors, it is illegal to mix bypass and |
72 | * non-bypass accesses. Therefore we access all INO buckets | |
73 | * using bypass accesses only. | |
74 | */ | |
75 | static unsigned long bucket_get_chain_pa(unsigned long bucket_pa) | |
76 | { | |
77 | unsigned long ret; | |
78 | ||
79 | __asm__ __volatile__("ldxa [%1] %2, %0" | |
80 | : "=&r" (ret) | |
81 | : "r" (bucket_pa + | |
82 | offsetof(struct ino_bucket, | |
83 | __irq_chain_pa)), | |
84 | "i" (ASI_PHYS_USE_EC)); | |
85 | ||
86 | return ret; | |
87 | } | |
88 | ||
89 | static void bucket_clear_chain_pa(unsigned long bucket_pa) | |
90 | { | |
91 | __asm__ __volatile__("stxa %%g0, [%0] %1" | |
92 | : /* no outputs */ | |
93 | : "r" (bucket_pa + | |
94 | offsetof(struct ino_bucket, | |
95 | __irq_chain_pa)), | |
96 | "i" (ASI_PHYS_USE_EC)); | |
97 | } | |
98 | ||
99 | static unsigned int bucket_get_virt_irq(unsigned long bucket_pa) | |
100 | { | |
101 | unsigned int ret; | |
102 | ||
103 | __asm__ __volatile__("lduwa [%1] %2, %0" | |
104 | : "=&r" (ret) | |
105 | : "r" (bucket_pa + | |
106 | offsetof(struct ino_bucket, | |
107 | __virt_irq)), | |
108 | "i" (ASI_PHYS_USE_EC)); | |
109 | ||
110 | return ret; | |
111 | } | |
112 | ||
113 | static void bucket_set_virt_irq(unsigned long bucket_pa, | |
114 | unsigned int virt_irq) | |
115 | { | |
116 | __asm__ __volatile__("stwa %0, [%1] %2" | |
117 | : /* no outputs */ | |
118 | : "r" (virt_irq), | |
119 | "r" (bucket_pa + | |
120 | offsetof(struct ino_bucket, | |
121 | __virt_irq)), | |
122 | "i" (ASI_PHYS_USE_EC)); | |
123 | } | |
124 | ||
eb2d8d60 | 125 | #define irq_work_pa(__cpu) &(trap_block[(__cpu)].irq_worklist_pa) |
1da177e4 | 126 | |
93b3238e | 127 | static struct { |
93b3238e DM |
128 | unsigned int dev_handle; |
129 | unsigned int dev_ino; | |
256c1df3 | 130 | unsigned int in_use; |
45b3f4cc | 131 | } virt_irq_table[NR_IRQS]; |
759f89e0 | 132 | static DEFINE_SPINLOCK(virt_irq_alloc_lock); |
8047e247 | 133 | |
256c1df3 | 134 | unsigned char virt_irq_alloc(unsigned int dev_handle, |
bb74b734 | 135 | unsigned int dev_ino) |
8047e247 | 136 | { |
759f89e0 | 137 | unsigned long flags; |
8047e247 DM |
138 | unsigned char ent; |
139 | ||
140 | BUILD_BUG_ON(NR_IRQS >= 256); | |
141 | ||
759f89e0 DM |
142 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
143 | ||
35a17eb6 | 144 | for (ent = 1; ent < NR_IRQS; ent++) { |
45b3f4cc | 145 | if (!virt_irq_table[ent].in_use) |
35a17eb6 DM |
146 | break; |
147 | } | |
8047e247 DM |
148 | if (ent >= NR_IRQS) { |
149 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
759f89e0 DM |
150 | ent = 0; |
151 | } else { | |
45b3f4cc DM |
152 | virt_irq_table[ent].dev_handle = dev_handle; |
153 | virt_irq_table[ent].dev_ino = dev_ino; | |
154 | virt_irq_table[ent].in_use = 1; | |
8047e247 DM |
155 | } |
156 | ||
759f89e0 | 157 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 DM |
158 | |
159 | return ent; | |
160 | } | |
161 | ||
5746c99d | 162 | #ifdef CONFIG_PCI_MSI |
759f89e0 | 163 | void virt_irq_free(unsigned int virt_irq) |
8047e247 | 164 | { |
759f89e0 | 165 | unsigned long flags; |
8047e247 | 166 | |
35a17eb6 DM |
167 | if (virt_irq >= NR_IRQS) |
168 | return; | |
169 | ||
759f89e0 DM |
170 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
171 | ||
45b3f4cc | 172 | virt_irq_table[virt_irq].in_use = 0; |
35a17eb6 | 173 | |
759f89e0 | 174 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 | 175 | } |
5746c99d | 176 | #endif |
8047e247 | 177 | |
1da177e4 | 178 | /* |
e18e2a00 | 179 | * /proc/interrupts printing: |
1da177e4 | 180 | */ |
1da177e4 LT |
181 | |
182 | int show_interrupts(struct seq_file *p, void *v) | |
183 | { | |
e18e2a00 DM |
184 | int i = *(loff_t *) v, j; |
185 | struct irqaction * action; | |
1da177e4 | 186 | unsigned long flags; |
1da177e4 | 187 | |
e18e2a00 DM |
188 | if (i == 0) { |
189 | seq_printf(p, " "); | |
190 | for_each_online_cpu(j) | |
191 | seq_printf(p, "CPU%d ",j); | |
192 | seq_putc(p, '\n'); | |
193 | } | |
194 | ||
195 | if (i < NR_IRQS) { | |
196 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
197 | action = irq_desc[i].action; | |
198 | if (!action) | |
199 | goto skip; | |
200 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
201 | #ifndef CONFIG_SMP |
202 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
203 | #else | |
e18e2a00 DM |
204 | for_each_online_cpu(j) |
205 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
1da177e4 | 206 | #endif |
d1bef4ed | 207 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
e18e2a00 DM |
208 | seq_printf(p, " %s", action->name); |
209 | ||
210 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 211 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 212 | |
1da177e4 | 213 | seq_putc(p, '\n'); |
e18e2a00 DM |
214 | skip: |
215 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
1da177e4 | 216 | } |
1da177e4 LT |
217 | return 0; |
218 | } | |
219 | ||
ebd8c56c DM |
220 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
221 | { | |
222 | unsigned int tid; | |
223 | ||
224 | if (this_is_starfire) { | |
225 | tid = starfire_translate(imap, cpuid); | |
226 | tid <<= IMAP_TID_SHIFT; | |
227 | tid &= IMAP_TID_UPA; | |
228 | } else { | |
229 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
230 | unsigned long ver; | |
231 | ||
232 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
233 | if ((ver >> 32UL) == __JALAPENO_ID || | |
234 | (ver >> 32UL) == __SERRANO_ID) { | |
235 | tid = cpuid << IMAP_TID_SHIFT; | |
236 | tid &= IMAP_TID_JBUS; | |
237 | } else { | |
238 | unsigned int a = cpuid & 0x1f; | |
239 | unsigned int n = (cpuid >> 5) & 0x1f; | |
240 | ||
241 | tid = ((a << IMAP_AID_SHIFT) | | |
242 | (n << IMAP_NID_SHIFT)); | |
243 | tid &= (IMAP_AID_SAFARI | | |
244 | IMAP_NID_SAFARI);; | |
245 | } | |
246 | } else { | |
247 | tid = cpuid << IMAP_TID_SHIFT; | |
248 | tid &= IMAP_TID_UPA; | |
249 | } | |
250 | } | |
251 | ||
252 | return tid; | |
253 | } | |
254 | ||
e18e2a00 DM |
255 | struct irq_handler_data { |
256 | unsigned long iclr; | |
257 | unsigned long imap; | |
8047e247 | 258 | |
e18e2a00 | 259 | void (*pre_handler)(unsigned int, void *, void *); |
8d57d3ad DM |
260 | void *arg1; |
261 | void *arg2; | |
e18e2a00 | 262 | }; |
1da177e4 | 263 | |
e18e2a00 DM |
264 | #ifdef CONFIG_SMP |
265 | static int irq_choose_cpu(unsigned int virt_irq) | |
088dd1f8 | 266 | { |
a53da52f | 267 | cpumask_t mask = irq_desc[virt_irq].affinity; |
e18e2a00 | 268 | int cpuid; |
088dd1f8 | 269 | |
e18e2a00 DM |
270 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
271 | static int irq_rover; | |
272 | static DEFINE_SPINLOCK(irq_rover_lock); | |
273 | unsigned long flags; | |
1da177e4 | 274 | |
e18e2a00 DM |
275 | /* Round-robin distribution... */ |
276 | do_round_robin: | |
277 | spin_lock_irqsave(&irq_rover_lock, flags); | |
10951ee6 | 278 | |
e18e2a00 DM |
279 | while (!cpu_online(irq_rover)) { |
280 | if (++irq_rover >= NR_CPUS) | |
281 | irq_rover = 0; | |
282 | } | |
283 | cpuid = irq_rover; | |
284 | do { | |
285 | if (++irq_rover >= NR_CPUS) | |
286 | irq_rover = 0; | |
287 | } while (!cpu_online(irq_rover)); | |
1da177e4 | 288 | |
e18e2a00 DM |
289 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
290 | } else { | |
291 | cpumask_t tmp; | |
088dd1f8 | 292 | |
e18e2a00 | 293 | cpus_and(tmp, cpu_online_map, mask); |
088dd1f8 | 294 | |
e18e2a00 DM |
295 | if (cpus_empty(tmp)) |
296 | goto do_round_robin; | |
088dd1f8 | 297 | |
e18e2a00 | 298 | cpuid = first_cpu(tmp); |
1da177e4 | 299 | } |
088dd1f8 | 300 | |
e18e2a00 DM |
301 | return cpuid; |
302 | } | |
303 | #else | |
304 | static int irq_choose_cpu(unsigned int virt_irq) | |
305 | { | |
306 | return real_hard_smp_processor_id(); | |
1da177e4 | 307 | } |
e18e2a00 | 308 | #endif |
1da177e4 | 309 | |
e18e2a00 | 310 | static void sun4u_irq_enable(unsigned int virt_irq) |
e3999574 | 311 | { |
68c92186 | 312 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
e3999574 | 313 | |
e18e2a00 | 314 | if (likely(data)) { |
861fe906 | 315 | unsigned long cpuid, imap, val; |
e18e2a00 | 316 | unsigned int tid; |
e3999574 | 317 | |
e18e2a00 DM |
318 | cpuid = irq_choose_cpu(virt_irq); |
319 | imap = data->imap; | |
e3999574 | 320 | |
e18e2a00 | 321 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 322 | |
861fe906 DM |
323 | val = upa_readq(imap); |
324 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
325 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
326 | val |= tid | IMAP_VALID; | |
327 | upa_writeq(val, imap); | |
e3999574 | 328 | } |
e3999574 DM |
329 | } |
330 | ||
b53bcb67 DM |
331 | static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask) |
332 | { | |
333 | sun4u_irq_enable(virt_irq); | |
334 | } | |
335 | ||
e18e2a00 | 336 | static void sun4u_irq_disable(unsigned int virt_irq) |
1da177e4 | 337 | { |
68c92186 | 338 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 339 | |
e18e2a00 DM |
340 | if (likely(data)) { |
341 | unsigned long imap = data->imap; | |
6e69d606 | 342 | unsigned long tmp = upa_readq(imap); |
1da177e4 | 343 | |
e18e2a00 | 344 | tmp &= ~IMAP_VALID; |
861fe906 | 345 | upa_writeq(tmp, imap); |
088dd1f8 | 346 | } |
088dd1f8 DM |
347 | } |
348 | ||
8d57d3ad | 349 | static void sun4u_irq_eoi(unsigned int virt_irq) |
088dd1f8 | 350 | { |
68c92186 | 351 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
5a606b72 DM |
352 | struct irq_desc *desc = irq_desc + virt_irq; |
353 | ||
354 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
355 | return; | |
088dd1f8 | 356 | |
e18e2a00 | 357 | if (likely(data)) |
861fe906 | 358 | upa_writeq(ICLR_IDLE, data->iclr); |
088dd1f8 DM |
359 | } |
360 | ||
e18e2a00 | 361 | static void sun4v_irq_enable(unsigned int virt_irq) |
088dd1f8 | 362 | { |
45b3f4cc | 363 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
77182300 DM |
364 | unsigned long cpuid = irq_choose_cpu(virt_irq); |
365 | int err; | |
366 | ||
367 | err = sun4v_intr_settarget(ino, cpuid); | |
368 | if (err != HV_EOK) | |
369 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
370 | "err(%d)\n", ino, cpuid, err); | |
371 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); | |
372 | if (err != HV_EOK) | |
373 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
374 | "err(%d)\n", ino, err); | |
375 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
376 | if (err != HV_EOK) | |
377 | printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", | |
378 | ino, err); | |
088dd1f8 DM |
379 | } |
380 | ||
b53bcb67 DM |
381 | static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask) |
382 | { | |
45b3f4cc | 383 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
77182300 DM |
384 | unsigned long cpuid = irq_choose_cpu(virt_irq); |
385 | int err; | |
386 | ||
387 | err = sun4v_intr_settarget(ino, cpuid); | |
388 | if (err != HV_EOK) | |
389 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " | |
390 | "err(%d)\n", ino, cpuid, err); | |
b53bcb67 DM |
391 | } |
392 | ||
e18e2a00 | 393 | static void sun4v_irq_disable(unsigned int virt_irq) |
1da177e4 | 394 | { |
45b3f4cc | 395 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
77182300 | 396 | int err; |
1da177e4 | 397 | |
77182300 DM |
398 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
399 | if (err != HV_EOK) | |
400 | printk(KERN_ERR "sun4v_intr_setenabled(%x): " | |
401 | "err(%d)\n", ino, err); | |
e18e2a00 | 402 | } |
1da177e4 | 403 | |
8d57d3ad | 404 | static void sun4v_irq_eoi(unsigned int virt_irq) |
e18e2a00 | 405 | { |
45b3f4cc | 406 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
5a606b72 | 407 | struct irq_desc *desc = irq_desc + virt_irq; |
77182300 | 408 | int err; |
5a606b72 DM |
409 | |
410 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
411 | return; | |
1da177e4 | 412 | |
77182300 DM |
413 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
414 | if (err != HV_EOK) | |
415 | printk(KERN_ERR "sun4v_intr_setstate(%x): " | |
416 | "err(%d)\n", ino, err); | |
1da177e4 LT |
417 | } |
418 | ||
4a907dec DM |
419 | static void sun4v_virq_enable(unsigned int virt_irq) |
420 | { | |
77182300 DM |
421 | unsigned long cpuid, dev_handle, dev_ino; |
422 | int err; | |
423 | ||
424 | cpuid = irq_choose_cpu(virt_irq); | |
425 | ||
45b3f4cc DM |
426 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
427 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
77182300 DM |
428 | |
429 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
430 | if (err != HV_EOK) | |
431 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
432 | "err(%d)\n", | |
433 | dev_handle, dev_ino, cpuid, err); | |
434 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
435 | HV_INTR_STATE_IDLE); | |
436 | if (err != HV_EOK) | |
437 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
438 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
439 | dev_handle, dev_ino, err); | |
440 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
441 | HV_INTR_ENABLED); | |
442 | if (err != HV_EOK) | |
443 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
444 | "HV_INTR_ENABLED): err(%d)\n", | |
445 | dev_handle, dev_ino, err); | |
4a907dec DM |
446 | } |
447 | ||
b53bcb67 DM |
448 | static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask) |
449 | { | |
77182300 DM |
450 | unsigned long cpuid, dev_handle, dev_ino; |
451 | int err; | |
b53bcb67 | 452 | |
77182300 | 453 | cpuid = irq_choose_cpu(virt_irq); |
b53bcb67 | 454 | |
45b3f4cc DM |
455 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
456 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
b53bcb67 | 457 | |
77182300 DM |
458 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); |
459 | if (err != HV_EOK) | |
460 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " | |
461 | "err(%d)\n", | |
462 | dev_handle, dev_ino, cpuid, err); | |
b53bcb67 DM |
463 | } |
464 | ||
4a907dec DM |
465 | static void sun4v_virq_disable(unsigned int virt_irq) |
466 | { | |
77182300 DM |
467 | unsigned long dev_handle, dev_ino; |
468 | int err; | |
469 | ||
45b3f4cc DM |
470 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
471 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
77182300 DM |
472 | |
473 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
474 | HV_INTR_DISABLED); | |
475 | if (err != HV_EOK) | |
476 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
477 | "HV_INTR_DISABLED): err(%d)\n", | |
478 | dev_handle, dev_ino, err); | |
4a907dec DM |
479 | } |
480 | ||
8d57d3ad | 481 | static void sun4v_virq_eoi(unsigned int virt_irq) |
4a907dec | 482 | { |
5a606b72 | 483 | struct irq_desc *desc = irq_desc + virt_irq; |
77182300 DM |
484 | unsigned long dev_handle, dev_ino; |
485 | int err; | |
5a606b72 DM |
486 | |
487 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
488 | return; | |
4a907dec | 489 | |
45b3f4cc DM |
490 | dev_handle = virt_irq_table[virt_irq].dev_handle; |
491 | dev_ino = virt_irq_table[virt_irq].dev_ino; | |
4a907dec | 492 | |
77182300 DM |
493 | err = sun4v_vintr_set_state(dev_handle, dev_ino, |
494 | HV_INTR_STATE_IDLE); | |
495 | if (err != HV_EOK) | |
496 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," | |
497 | "HV_INTR_STATE_IDLE): err(%d)\n", | |
498 | dev_handle, dev_ino, err); | |
4a907dec DM |
499 | } |
500 | ||
729e7d7e | 501 | static struct irq_chip sun4u_irq = { |
e18e2a00 DM |
502 | .typename = "sun4u", |
503 | .enable = sun4u_irq_enable, | |
504 | .disable = sun4u_irq_disable, | |
8d57d3ad | 505 | .eoi = sun4u_irq_eoi, |
b53bcb67 | 506 | .set_affinity = sun4u_set_affinity, |
e18e2a00 | 507 | }; |
088dd1f8 | 508 | |
729e7d7e | 509 | static struct irq_chip sun4v_irq = { |
e18e2a00 DM |
510 | .typename = "sun4v", |
511 | .enable = sun4v_irq_enable, | |
512 | .disable = sun4v_irq_disable, | |
8d57d3ad | 513 | .eoi = sun4v_irq_eoi, |
b53bcb67 | 514 | .set_affinity = sun4v_set_affinity, |
e18e2a00 | 515 | }; |
1da177e4 | 516 | |
4a907dec DM |
517 | static struct irq_chip sun4v_virq = { |
518 | .typename = "vsun4v", | |
519 | .enable = sun4v_virq_enable, | |
520 | .disable = sun4v_virq_disable, | |
8d57d3ad | 521 | .eoi = sun4v_virq_eoi, |
b53bcb67 | 522 | .set_affinity = sun4v_virt_set_affinity, |
4a907dec DM |
523 | }; |
524 | ||
edde08f2 | 525 | static void pre_flow_handler(unsigned int virt_irq, |
8d57d3ad DM |
526 | struct irq_desc *desc) |
527 | { | |
528 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); | |
529 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; | |
530 | ||
531 | data->pre_handler(ino, data->arg1, data->arg2); | |
532 | ||
533 | handle_fasteoi_irq(virt_irq, desc); | |
534 | } | |
535 | ||
e18e2a00 DM |
536 | void irq_install_pre_handler(int virt_irq, |
537 | void (*func)(unsigned int, void *, void *), | |
538 | void *arg1, void *arg2) | |
539 | { | |
68c92186 | 540 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
8d57d3ad | 541 | struct irq_desc *desc = irq_desc + virt_irq; |
088dd1f8 | 542 | |
e18e2a00 | 543 | data->pre_handler = func; |
8d57d3ad DM |
544 | data->arg1 = arg1; |
545 | data->arg2 = arg2; | |
24ac26d4 | 546 | |
8d57d3ad | 547 | desc->handle_irq = pre_flow_handler; |
e18e2a00 | 548 | } |
1da177e4 | 549 | |
e18e2a00 DM |
550 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
551 | { | |
552 | struct ino_bucket *bucket; | |
553 | struct irq_handler_data *data; | |
42d5f99b | 554 | unsigned int virt_irq; |
e18e2a00 | 555 | int ino; |
1da177e4 | 556 | |
e18e2a00 | 557 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 558 | |
861fe906 | 559 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
e18e2a00 | 560 | bucket = &ivector_table[ino]; |
42d5f99b DM |
561 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
562 | if (!virt_irq) { | |
256c1df3 | 563 | virt_irq = virt_irq_alloc(0, ino); |
42d5f99b | 564 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
565 | set_irq_chip_and_handler_name(virt_irq, |
566 | &sun4u_irq, | |
567 | handle_fasteoi_irq, | |
568 | "IVEC"); | |
fd0504c3 | 569 | } |
1da177e4 | 570 | |
42d5f99b | 571 | data = get_irq_chip_data(virt_irq); |
68c92186 | 572 | if (unlikely(data)) |
e18e2a00 | 573 | goto out; |
fd0504c3 | 574 | |
e18e2a00 DM |
575 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
576 | if (unlikely(!data)) { | |
577 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
578 | prom_halt(); | |
1da177e4 | 579 | } |
42d5f99b | 580 | set_irq_chip_data(virt_irq, data); |
1da177e4 | 581 | |
e18e2a00 DM |
582 | data->imap = imap; |
583 | data->iclr = iclr; | |
1da177e4 | 584 | |
e18e2a00 | 585 | out: |
42d5f99b | 586 | return virt_irq; |
e18e2a00 | 587 | } |
1da177e4 | 588 | |
4a907dec DM |
589 | static unsigned int sun4v_build_common(unsigned long sysino, |
590 | struct irq_chip *chip) | |
1da177e4 | 591 | { |
8047e247 | 592 | struct ino_bucket *bucket; |
e18e2a00 | 593 | struct irq_handler_data *data; |
42d5f99b | 594 | unsigned int virt_irq; |
8047e247 | 595 | |
e18e2a00 | 596 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 597 | |
e18e2a00 | 598 | bucket = &ivector_table[sysino]; |
42d5f99b DM |
599 | virt_irq = bucket_get_virt_irq(__pa(bucket)); |
600 | if (!virt_irq) { | |
256c1df3 | 601 | virt_irq = virt_irq_alloc(0, sysino); |
42d5f99b | 602 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
603 | set_irq_chip_and_handler_name(virt_irq, chip, |
604 | handle_fasteoi_irq, | |
605 | "IVEC"); | |
1da177e4 | 606 | } |
1da177e4 | 607 | |
42d5f99b | 608 | data = get_irq_chip_data(virt_irq); |
68c92186 | 609 | if (unlikely(data)) |
1da177e4 | 610 | goto out; |
1da177e4 | 611 | |
e18e2a00 DM |
612 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
613 | if (unlikely(!data)) { | |
614 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
615 | prom_halt(); | |
616 | } | |
42d5f99b | 617 | set_irq_chip_data(virt_irq, data); |
1da177e4 | 618 | |
e18e2a00 DM |
619 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
620 | * is done by hypervisor calls on sun4v platforms, not by direct | |
621 | * register accesses. | |
622 | */ | |
623 | data->imap = ~0UL; | |
624 | data->iclr = ~0UL; | |
1da177e4 | 625 | |
e18e2a00 | 626 | out: |
42d5f99b | 627 | return virt_irq; |
e18e2a00 | 628 | } |
1da177e4 | 629 | |
4a907dec DM |
630 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
631 | { | |
632 | unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); | |
633 | ||
634 | return sun4v_build_common(sysino, &sun4v_irq); | |
635 | } | |
636 | ||
637 | unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |
638 | { | |
b80e6998 DM |
639 | struct irq_handler_data *data; |
640 | struct ino_bucket *bucket; | |
641 | unsigned long hv_err, cookie; | |
42d5f99b | 642 | unsigned int virt_irq; |
b80e6998 DM |
643 | |
644 | bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC); | |
645 | if (unlikely(!bucket)) | |
646 | return 0; | |
42d5f99b DM |
647 | __flush_dcache_range((unsigned long) bucket, |
648 | ((unsigned long) bucket + | |
649 | sizeof(struct ino_bucket))); | |
b80e6998 | 650 | |
256c1df3 | 651 | virt_irq = virt_irq_alloc(devhandle, devino); |
42d5f99b | 652 | bucket_set_virt_irq(__pa(bucket), virt_irq); |
8d57d3ad DM |
653 | |
654 | set_irq_chip_and_handler_name(virt_irq, &sun4v_virq, | |
655 | handle_fasteoi_irq, | |
656 | "IVEC"); | |
4a907dec | 657 | |
b80e6998 DM |
658 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
659 | if (unlikely(!data)) | |
660 | return 0; | |
4a907dec | 661 | |
42d5f99b | 662 | set_irq_chip_data(virt_irq, data); |
4a907dec | 663 | |
b80e6998 DM |
664 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
665 | * is done by hypervisor calls on sun4v platforms, not by direct | |
666 | * register accesses. | |
667 | */ | |
668 | data->imap = ~0UL; | |
669 | data->iclr = ~0UL; | |
670 | ||
671 | cookie = ~__pa(bucket); | |
672 | hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie); | |
4a907dec DM |
673 | if (hv_err) { |
674 | prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " | |
675 | "err=%lu\n", devhandle, devino, hv_err); | |
676 | prom_halt(); | |
677 | } | |
678 | ||
42d5f99b | 679 | return virt_irq; |
4a907dec DM |
680 | } |
681 | ||
e18e2a00 DM |
682 | void ack_bad_irq(unsigned int virt_irq) |
683 | { | |
45b3f4cc | 684 | unsigned int ino = virt_irq_table[virt_irq].dev_ino; |
ab66a50e | 685 | |
77182300 DM |
686 | if (!ino) |
687 | ino = 0xdeadbeef; | |
6a76267f | 688 | |
e18e2a00 DM |
689 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
690 | ino, virt_irq); | |
1da177e4 LT |
691 | } |
692 | ||
1da177e4 LT |
693 | void handler_irq(int irq, struct pt_regs *regs) |
694 | { | |
eb2d8d60 | 695 | unsigned long pstate, bucket_pa; |
6d24c8dc | 696 | struct pt_regs *old_regs; |
1da177e4 | 697 | |
1da177e4 | 698 | clear_softint(1 << irq); |
1da177e4 | 699 | |
6d24c8dc | 700 | old_regs = set_irq_regs(regs); |
1da177e4 | 701 | irq_enter(); |
1da177e4 | 702 | |
a650d383 DM |
703 | /* Grab an atomic snapshot of the pending IVECs. */ |
704 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
705 | "wrpr %0, %3, %%pstate\n\t" | |
706 | "ldx [%2], %1\n\t" | |
707 | "stx %%g0, [%2]\n\t" | |
708 | "wrpr %0, 0x0, %%pstate\n\t" | |
eb2d8d60 DM |
709 | : "=&r" (pstate), "=&r" (bucket_pa) |
710 | : "r" (irq_work_pa(smp_processor_id())), | |
a650d383 DM |
711 | "i" (PSTATE_IE) |
712 | : "memory"); | |
713 | ||
eb2d8d60 | 714 | while (bucket_pa) { |
8d57d3ad | 715 | struct irq_desc *desc; |
eb2d8d60 DM |
716 | unsigned long next_pa; |
717 | unsigned int virt_irq; | |
1da177e4 | 718 | |
42d5f99b DM |
719 | next_pa = bucket_get_chain_pa(bucket_pa); |
720 | virt_irq = bucket_get_virt_irq(bucket_pa); | |
721 | bucket_clear_chain_pa(bucket_pa); | |
fd0504c3 | 722 | |
8d57d3ad DM |
723 | desc = irq_desc + virt_irq; |
724 | ||
725 | desc->handle_irq(virt_irq, desc); | |
eb2d8d60 DM |
726 | |
727 | bucket_pa = next_pa; | |
1da177e4 | 728 | } |
e18e2a00 | 729 | |
1da177e4 | 730 | irq_exit(); |
6d24c8dc | 731 | set_irq_regs(old_regs); |
1da177e4 LT |
732 | } |
733 | ||
e0204409 DM |
734 | #ifdef CONFIG_HOTPLUG_CPU |
735 | void fixup_irqs(void) | |
736 | { | |
737 | unsigned int irq; | |
738 | ||
739 | for (irq = 0; irq < NR_IRQS; irq++) { | |
740 | unsigned long flags; | |
741 | ||
742 | spin_lock_irqsave(&irq_desc[irq].lock, flags); | |
743 | if (irq_desc[irq].action && | |
744 | !(irq_desc[irq].status & IRQ_PER_CPU)) { | |
745 | if (irq_desc[irq].chip->set_affinity) | |
746 | irq_desc[irq].chip->set_affinity(irq, | |
747 | irq_desc[irq].affinity); | |
748 | } | |
749 | spin_unlock_irqrestore(&irq_desc[irq].lock, flags); | |
750 | } | |
751 | } | |
752 | #endif | |
753 | ||
cdd5186f DM |
754 | struct sun5_timer { |
755 | u64 count0; | |
756 | u64 limit0; | |
757 | u64 count1; | |
758 | u64 limit1; | |
759 | }; | |
1da177e4 | 760 | |
cdd5186f | 761 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
762 | static u64 prom_limit0, prom_limit1; |
763 | ||
764 | static void map_prom_timers(void) | |
765 | { | |
25c7581b | 766 | struct device_node *dp; |
6a23acf3 | 767 | const unsigned int *addr; |
1da177e4 LT |
768 | |
769 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
770 | dp = of_find_node_by_path("/"); |
771 | dp = dp->child; | |
772 | while (dp) { | |
773 | if (!strcmp(dp->name, "counter-timer")) | |
774 | break; | |
775 | dp = dp->sibling; | |
776 | } | |
1da177e4 LT |
777 | |
778 | /* Assume if node is not present, PROM uses different tick mechanism | |
779 | * which we should not care about. | |
780 | */ | |
25c7581b | 781 | if (!dp) { |
1da177e4 LT |
782 | prom_timers = (struct sun5_timer *) 0; |
783 | return; | |
784 | } | |
785 | ||
786 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
787 | addr = of_get_property(dp, "address", NULL); |
788 | if (!addr) { | |
1da177e4 LT |
789 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
790 | prom_timers = (struct sun5_timer *) 0; | |
791 | return; | |
792 | } | |
793 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
794 | } | |
795 | ||
796 | static void kill_prom_timer(void) | |
797 | { | |
798 | if (!prom_timers) | |
799 | return; | |
800 | ||
801 | /* Save them away for later. */ | |
802 | prom_limit0 = prom_timers->limit0; | |
803 | prom_limit1 = prom_timers->limit1; | |
804 | ||
805 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
806 | * We turn both off here just to be paranoid. | |
807 | */ | |
808 | prom_timers->limit0 = 0; | |
809 | prom_timers->limit1 = 0; | |
810 | ||
811 | /* Wheee, eat the interrupt packet too... */ | |
812 | __asm__ __volatile__( | |
813 | " mov 0x40, %%g2\n" | |
814 | " ldxa [%%g0] %0, %%g1\n" | |
815 | " ldxa [%%g2] %1, %%g1\n" | |
816 | " stxa %%g0, [%%g0] %0\n" | |
817 | " membar #Sync\n" | |
818 | : /* no outputs */ | |
819 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
820 | : "g1", "g2"); | |
821 | } | |
822 | ||
1da177e4 LT |
823 | void init_irqwork_curcpu(void) |
824 | { | |
1da177e4 LT |
825 | int cpu = hard_smp_processor_id(); |
826 | ||
eb2d8d60 | 827 | trap_block[cpu].irq_worklist_pa = 0UL; |
1da177e4 LT |
828 | } |
829 | ||
5cbc3073 DM |
830 | /* Please be very careful with register_one_mondo() and |
831 | * sun4v_register_mondo_queues(). | |
832 | * | |
833 | * On SMP this gets invoked from the CPU trampoline before | |
834 | * the cpu has fully taken over the trap table from OBP, | |
835 | * and it's kernel stack + %g6 thread register state is | |
836 | * not fully cooked yet. | |
837 | * | |
838 | * Therefore you cannot make any OBP calls, not even prom_printf, | |
839 | * from these two routines. | |
840 | */ | |
841 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) | |
ac29c11d | 842 | { |
5cbc3073 | 843 | unsigned long num_entries = (qmask + 1) / 64; |
94f8762d DM |
844 | unsigned long status; |
845 | ||
846 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
847 | if (status != HV_EOK) { | |
848 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
849 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
850 | prom_halt(); |
851 | } | |
852 | } | |
853 | ||
b434e719 | 854 | void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 855 | { |
b5a37e96 DM |
856 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
857 | ||
5cbc3073 DM |
858 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
859 | tb->cpu_mondo_qmask); | |
860 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, | |
861 | tb->dev_mondo_qmask); | |
862 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, | |
863 | tb->resum_qmask); | |
864 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, | |
865 | tb->nonresum_qmask); | |
b5a37e96 DM |
866 | } |
867 | ||
b434e719 | 868 | static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 869 | { |
5cbc3073 | 870 | unsigned long size = PAGE_ALIGN(qmask + 1); |
719023fb | 871 | void *p = __alloc_bootmem(size, size, 0); |
5cbc3073 | 872 | if (!p) { |
b5a37e96 DM |
873 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); |
874 | prom_halt(); | |
875 | } | |
876 | ||
5cbc3073 | 877 | *pa_ptr = __pa(p); |
b5a37e96 DM |
878 | } |
879 | ||
b434e719 | 880 | static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 881 | { |
5cbc3073 | 882 | unsigned long size = PAGE_ALIGN(qmask + 1); |
719023fb | 883 | void *p = __alloc_bootmem(size, size, 0); |
5b0c0572 | 884 | |
5cbc3073 | 885 | if (!p) { |
5b0c0572 DM |
886 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); |
887 | prom_halt(); | |
888 | } | |
889 | ||
5cbc3073 | 890 | *pa_ptr = __pa(p); |
5b0c0572 DM |
891 | } |
892 | ||
b434e719 | 893 | static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) |
1d2f1f90 DM |
894 | { |
895 | #ifdef CONFIG_SMP | |
b5a37e96 | 896 | void *page; |
1d2f1f90 DM |
897 | |
898 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
899 | ||
719023fb | 900 | page = alloc_bootmem_pages(PAGE_SIZE); |
1d2f1f90 DM |
901 | if (!page) { |
902 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
903 | prom_halt(); | |
904 | } | |
905 | ||
906 | tb->cpu_mondo_block_pa = __pa(page); | |
907 | tb->cpu_list_pa = __pa(page + 64); | |
908 | #endif | |
909 | } | |
910 | ||
b434e719 DM |
911 | /* Allocate mondo and error queues for all possible cpus. */ |
912 | static void __init sun4v_init_mondo_queues(void) | |
ac29c11d | 913 | { |
b434e719 | 914 | int cpu; |
ac29c11d | 915 | |
b434e719 DM |
916 | for_each_possible_cpu(cpu) { |
917 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 918 | |
b434e719 DM |
919 | alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); |
920 | alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask); | |
921 | alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask); | |
922 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask); | |
923 | alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask); | |
924 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, | |
925 | tb->nonresum_qmask); | |
1d2f1f90 | 926 | |
b434e719 | 927 | init_cpu_send_mondo_info(tb); |
72aff53f | 928 | } |
b434e719 DM |
929 | |
930 | /* Load up the boot cpu's entries. */ | |
931 | sun4v_register_mondo_queues(hard_smp_processor_id()); | |
ac29c11d DM |
932 | } |
933 | ||
e18e2a00 DM |
934 | static struct irqaction timer_irq_action = { |
935 | .name = "timer", | |
936 | }; | |
937 | ||
1da177e4 LT |
938 | /* Only invoked on boot processor. */ |
939 | void __init init_IRQ(void) | |
940 | { | |
10397e40 DM |
941 | unsigned long size; |
942 | ||
1da177e4 LT |
943 | map_prom_timers(); |
944 | kill_prom_timer(); | |
1da177e4 | 945 | |
10397e40 | 946 | size = sizeof(struct ino_bucket) * NUM_IVECS; |
719023fb | 947 | ivector_table = alloc_bootmem(size); |
10397e40 DM |
948 | if (!ivector_table) { |
949 | prom_printf("Fatal error, cannot allocate ivector_table\n"); | |
950 | prom_halt(); | |
951 | } | |
42d5f99b DM |
952 | __flush_dcache_range((unsigned long) ivector_table, |
953 | ((unsigned long) ivector_table) + size); | |
10397e40 DM |
954 | |
955 | ivector_table_pa = __pa(ivector_table); | |
eb2d8d60 | 956 | |
ac29c11d | 957 | if (tlb_type == hypervisor) |
b434e719 | 958 | sun4v_init_mondo_queues(); |
ac29c11d | 959 | |
1da177e4 LT |
960 | /* We need to clear any IRQ's pending in the soft interrupt |
961 | * registers, a spurious one could be left around from the | |
962 | * PROM timer which we just disabled. | |
963 | */ | |
964 | clear_softint(get_softint()); | |
965 | ||
966 | /* Now that ivector table is initialized, it is safe | |
967 | * to receive IRQ vector traps. We will normally take | |
968 | * one or two right now, in case some device PROM used | |
969 | * to boot us wants to speak to us. We just ignore them. | |
970 | */ | |
971 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
972 | "or %%g1, %0, %%g1\n\t" | |
973 | "wrpr %%g1, 0x0, %%pstate" | |
974 | : /* No outputs */ | |
975 | : "i" (PSTATE_IE) | |
976 | : "g1"); | |
1da177e4 | 977 | |
e18e2a00 | 978 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 979 | } |