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1da177e4 LT |
1 | /* $Id: irq.c,v 1.114 2002/01/11 08:45:38 davem Exp $ |
2 | * irq.c: UltraSparc IRQ handling/init/registry. | |
3 | * | |
4 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
5 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) | |
6 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
7 | */ | |
8 | ||
1da177e4 LT |
9 | #include <linux/module.h> |
10 | #include <linux/sched.h> | |
11 | #include <linux/ptrace.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/kernel_stat.h> | |
14 | #include <linux/signal.h> | |
15 | #include <linux/mm.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/slab.h> | |
18 | #include <linux/random.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/delay.h> | |
21 | #include <linux/proc_fs.h> | |
22 | #include <linux/seq_file.h> | |
b5a37e96 | 23 | #include <linux/bootmem.h> |
e18e2a00 | 24 | #include <linux/irq.h> |
35a17eb6 | 25 | #include <linux/msi.h> |
1da177e4 LT |
26 | |
27 | #include <asm/ptrace.h> | |
28 | #include <asm/processor.h> | |
29 | #include <asm/atomic.h> | |
30 | #include <asm/system.h> | |
31 | #include <asm/irq.h> | |
2e457ef6 | 32 | #include <asm/io.h> |
1da177e4 LT |
33 | #include <asm/sbus.h> |
34 | #include <asm/iommu.h> | |
35 | #include <asm/upa.h> | |
36 | #include <asm/oplib.h> | |
25c7581b | 37 | #include <asm/prom.h> |
1da177e4 LT |
38 | #include <asm/timer.h> |
39 | #include <asm/smp.h> | |
40 | #include <asm/starfire.h> | |
41 | #include <asm/uaccess.h> | |
42 | #include <asm/cache.h> | |
43 | #include <asm/cpudata.h> | |
63b61452 | 44 | #include <asm/auxio.h> |
92704a1c | 45 | #include <asm/head.h> |
1da177e4 | 46 | |
1da177e4 LT |
47 | /* UPA nodes send interrupt packet to UltraSparc with first data reg |
48 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
49 | * delivered. We must translate this into a non-vector IRQ so we can | |
50 | * set the softint on this cpu. | |
51 | * | |
52 | * To make processing these packets efficient and race free we use | |
53 | * an array of irq buckets below. The interrupt vector handler in | |
54 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
55 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
56 | * code uses CAS to get an atomic snapshot of the list and clear it | |
57 | * at the same time. | |
e18e2a00 DM |
58 | * |
59 | * If you make changes to ino_bucket, please update hand coded assembler | |
60 | * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S | |
1da177e4 | 61 | */ |
e18e2a00 DM |
62 | struct ino_bucket { |
63 | /* Next handler in per-CPU IRQ worklist. We know that | |
64 | * bucket pointers have the high 32-bits clear, so to | |
65 | * save space we only store the bits we need. | |
66 | */ | |
67 | /*0x00*/unsigned int irq_chain; | |
1da177e4 | 68 | |
e18e2a00 DM |
69 | /* Virtual interrupt number assigned to this INO. */ |
70 | /*0x04*/unsigned int virt_irq; | |
71 | }; | |
72 | ||
73 | #define NUM_IVECS (IMAP_INR + 1) | |
1da177e4 LT |
74 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); |
75 | ||
e18e2a00 DM |
76 | #define __irq_ino(irq) \ |
77 | (((struct ino_bucket *)(unsigned long)(irq)) - &ivector_table[0]) | |
78 | #define __bucket(irq) ((struct ino_bucket *)(unsigned long)(irq)) | |
79 | #define __irq(bucket) ((unsigned int)(unsigned long)(bucket)) | |
80 | ||
1da177e4 LT |
81 | /* This has to be in the main kernel image, it cannot be |
82 | * turned into per-cpu data. The reason is that the main | |
83 | * kernel image is locked into the TLB and this structure | |
84 | * is accessed from the vectored interrupt trap handler. If | |
85 | * access to this structure takes a TLB miss it could cause | |
86 | * the 5-level sparc v9 trap stack to overflow. | |
87 | */ | |
fd0504c3 | 88 | #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist) |
1da177e4 | 89 | |
8047e247 | 90 | static unsigned int virt_to_real_irq_table[NR_IRQS]; |
8047e247 DM |
91 | |
92 | static unsigned char virt_irq_alloc(unsigned int real_irq) | |
93 | { | |
94 | unsigned char ent; | |
95 | ||
96 | BUILD_BUG_ON(NR_IRQS >= 256); | |
97 | ||
35a17eb6 DM |
98 | for (ent = 1; ent < NR_IRQS; ent++) { |
99 | if (!virt_to_real_irq_table[ent]) | |
100 | break; | |
101 | } | |
8047e247 DM |
102 | if (ent >= NR_IRQS) { |
103 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
104 | return 0; | |
105 | } | |
106 | ||
8047e247 DM |
107 | virt_to_real_irq_table[ent] = real_irq; |
108 | ||
109 | return ent; | |
110 | } | |
111 | ||
5746c99d | 112 | #ifdef CONFIG_PCI_MSI |
35a17eb6 | 113 | static void virt_irq_free(unsigned int virt_irq) |
8047e247 | 114 | { |
35a17eb6 | 115 | unsigned int real_irq; |
8047e247 | 116 | |
35a17eb6 DM |
117 | if (virt_irq >= NR_IRQS) |
118 | return; | |
119 | ||
120 | real_irq = virt_to_real_irq_table[virt_irq]; | |
121 | virt_to_real_irq_table[virt_irq] = 0; | |
122 | ||
123 | __bucket(real_irq)->virt_irq = 0; | |
8047e247 | 124 | } |
5746c99d | 125 | #endif |
8047e247 DM |
126 | |
127 | static unsigned int virt_to_real_irq(unsigned char virt_irq) | |
128 | { | |
129 | return virt_to_real_irq_table[virt_irq]; | |
130 | } | |
131 | ||
1da177e4 | 132 | /* |
e18e2a00 | 133 | * /proc/interrupts printing: |
1da177e4 | 134 | */ |
1da177e4 LT |
135 | |
136 | int show_interrupts(struct seq_file *p, void *v) | |
137 | { | |
e18e2a00 DM |
138 | int i = *(loff_t *) v, j; |
139 | struct irqaction * action; | |
1da177e4 | 140 | unsigned long flags; |
1da177e4 | 141 | |
e18e2a00 DM |
142 | if (i == 0) { |
143 | seq_printf(p, " "); | |
144 | for_each_online_cpu(j) | |
145 | seq_printf(p, "CPU%d ",j); | |
146 | seq_putc(p, '\n'); | |
147 | } | |
148 | ||
149 | if (i < NR_IRQS) { | |
150 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
151 | action = irq_desc[i].action; | |
152 | if (!action) | |
153 | goto skip; | |
154 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
155 | #ifndef CONFIG_SMP |
156 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
157 | #else | |
e18e2a00 DM |
158 | for_each_online_cpu(j) |
159 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
1da177e4 | 160 | #endif |
d1bef4ed | 161 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
e18e2a00 DM |
162 | seq_printf(p, " %s", action->name); |
163 | ||
164 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 165 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 166 | |
1da177e4 | 167 | seq_putc(p, '\n'); |
e18e2a00 DM |
168 | skip: |
169 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
1da177e4 | 170 | } |
1da177e4 LT |
171 | return 0; |
172 | } | |
173 | ||
ebd8c56c DM |
174 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
175 | { | |
176 | unsigned int tid; | |
177 | ||
178 | if (this_is_starfire) { | |
179 | tid = starfire_translate(imap, cpuid); | |
180 | tid <<= IMAP_TID_SHIFT; | |
181 | tid &= IMAP_TID_UPA; | |
182 | } else { | |
183 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
184 | unsigned long ver; | |
185 | ||
186 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
187 | if ((ver >> 32UL) == __JALAPENO_ID || | |
188 | (ver >> 32UL) == __SERRANO_ID) { | |
189 | tid = cpuid << IMAP_TID_SHIFT; | |
190 | tid &= IMAP_TID_JBUS; | |
191 | } else { | |
192 | unsigned int a = cpuid & 0x1f; | |
193 | unsigned int n = (cpuid >> 5) & 0x1f; | |
194 | ||
195 | tid = ((a << IMAP_AID_SHIFT) | | |
196 | (n << IMAP_NID_SHIFT)); | |
197 | tid &= (IMAP_AID_SAFARI | | |
198 | IMAP_NID_SAFARI);; | |
199 | } | |
200 | } else { | |
201 | tid = cpuid << IMAP_TID_SHIFT; | |
202 | tid &= IMAP_TID_UPA; | |
203 | } | |
204 | } | |
205 | ||
206 | return tid; | |
207 | } | |
208 | ||
e18e2a00 DM |
209 | struct irq_handler_data { |
210 | unsigned long iclr; | |
211 | unsigned long imap; | |
8047e247 | 212 | |
e18e2a00 DM |
213 | void (*pre_handler)(unsigned int, void *, void *); |
214 | void *pre_handler_arg1; | |
215 | void *pre_handler_arg2; | |
216 | }; | |
1da177e4 | 217 | |
e18e2a00 | 218 | static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq) |
1da177e4 | 219 | { |
8047e247 | 220 | unsigned int real_irq = virt_to_real_irq(virt_irq); |
e18e2a00 | 221 | struct ino_bucket *bucket = NULL; |
1da177e4 | 222 | |
e18e2a00 DM |
223 | if (likely(real_irq)) |
224 | bucket = __bucket(real_irq); | |
8047e247 | 225 | |
e18e2a00 | 226 | return bucket; |
1da177e4 LT |
227 | } |
228 | ||
e18e2a00 DM |
229 | #ifdef CONFIG_SMP |
230 | static int irq_choose_cpu(unsigned int virt_irq) | |
088dd1f8 | 231 | { |
a53da52f | 232 | cpumask_t mask = irq_desc[virt_irq].affinity; |
e18e2a00 | 233 | int cpuid; |
088dd1f8 | 234 | |
e18e2a00 DM |
235 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
236 | static int irq_rover; | |
237 | static DEFINE_SPINLOCK(irq_rover_lock); | |
238 | unsigned long flags; | |
1da177e4 | 239 | |
e18e2a00 DM |
240 | /* Round-robin distribution... */ |
241 | do_round_robin: | |
242 | spin_lock_irqsave(&irq_rover_lock, flags); | |
10951ee6 | 243 | |
e18e2a00 DM |
244 | while (!cpu_online(irq_rover)) { |
245 | if (++irq_rover >= NR_CPUS) | |
246 | irq_rover = 0; | |
247 | } | |
248 | cpuid = irq_rover; | |
249 | do { | |
250 | if (++irq_rover >= NR_CPUS) | |
251 | irq_rover = 0; | |
252 | } while (!cpu_online(irq_rover)); | |
1da177e4 | 253 | |
e18e2a00 DM |
254 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
255 | } else { | |
256 | cpumask_t tmp; | |
088dd1f8 | 257 | |
e18e2a00 | 258 | cpus_and(tmp, cpu_online_map, mask); |
088dd1f8 | 259 | |
e18e2a00 DM |
260 | if (cpus_empty(tmp)) |
261 | goto do_round_robin; | |
088dd1f8 | 262 | |
e18e2a00 | 263 | cpuid = first_cpu(tmp); |
1da177e4 | 264 | } |
088dd1f8 | 265 | |
e18e2a00 DM |
266 | return cpuid; |
267 | } | |
268 | #else | |
269 | static int irq_choose_cpu(unsigned int virt_irq) | |
270 | { | |
271 | return real_hard_smp_processor_id(); | |
1da177e4 | 272 | } |
e18e2a00 | 273 | #endif |
1da177e4 | 274 | |
e18e2a00 | 275 | static void sun4u_irq_enable(unsigned int virt_irq) |
e3999574 | 276 | { |
68c92186 | 277 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
e3999574 | 278 | |
e18e2a00 | 279 | if (likely(data)) { |
861fe906 | 280 | unsigned long cpuid, imap, val; |
e18e2a00 | 281 | unsigned int tid; |
e3999574 | 282 | |
e18e2a00 DM |
283 | cpuid = irq_choose_cpu(virt_irq); |
284 | imap = data->imap; | |
e3999574 | 285 | |
e18e2a00 | 286 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 287 | |
861fe906 DM |
288 | val = upa_readq(imap); |
289 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
290 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
291 | val |= tid | IMAP_VALID; | |
292 | upa_writeq(val, imap); | |
e3999574 | 293 | } |
e3999574 DM |
294 | } |
295 | ||
e18e2a00 | 296 | static void sun4u_irq_disable(unsigned int virt_irq) |
1da177e4 | 297 | { |
68c92186 | 298 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 299 | |
e18e2a00 DM |
300 | if (likely(data)) { |
301 | unsigned long imap = data->imap; | |
861fe906 | 302 | u32 tmp = upa_readq(imap); |
1da177e4 | 303 | |
e18e2a00 | 304 | tmp &= ~IMAP_VALID; |
861fe906 | 305 | upa_writeq(tmp, imap); |
088dd1f8 | 306 | } |
088dd1f8 DM |
307 | } |
308 | ||
e18e2a00 | 309 | static void sun4u_irq_end(unsigned int virt_irq) |
088dd1f8 | 310 | { |
68c92186 | 311 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
088dd1f8 | 312 | |
e18e2a00 | 313 | if (likely(data)) |
861fe906 | 314 | upa_writeq(ICLR_IDLE, data->iclr); |
088dd1f8 DM |
315 | } |
316 | ||
e18e2a00 | 317 | static void sun4v_irq_enable(unsigned int virt_irq) |
088dd1f8 | 318 | { |
e18e2a00 DM |
319 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
320 | unsigned int ino = bucket - &ivector_table[0]; | |
088dd1f8 | 321 | |
e18e2a00 DM |
322 | if (likely(bucket)) { |
323 | unsigned long cpuid; | |
324 | int err; | |
088dd1f8 | 325 | |
e18e2a00 | 326 | cpuid = irq_choose_cpu(virt_irq); |
088dd1f8 | 327 | |
e18e2a00 DM |
328 | err = sun4v_intr_settarget(ino, cpuid); |
329 | if (err != HV_EOK) | |
330 | printk("sun4v_intr_settarget(%x,%lu): err(%d)\n", | |
331 | ino, cpuid, err); | |
332 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); | |
333 | if (err != HV_EOK) | |
334 | printk("sun4v_intr_setenabled(%x): err(%d)\n", | |
335 | ino, err); | |
088dd1f8 | 336 | } |
088dd1f8 DM |
337 | } |
338 | ||
e18e2a00 | 339 | static void sun4v_irq_disable(unsigned int virt_irq) |
1da177e4 | 340 | { |
e18e2a00 DM |
341 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
342 | unsigned int ino = bucket - &ivector_table[0]; | |
1da177e4 | 343 | |
e18e2a00 DM |
344 | if (likely(bucket)) { |
345 | int err; | |
1da177e4 | 346 | |
e18e2a00 DM |
347 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
348 | if (err != HV_EOK) | |
349 | printk("sun4v_intr_setenabled(%x): " | |
350 | "err(%d)\n", ino, err); | |
1da177e4 | 351 | } |
e18e2a00 | 352 | } |
1da177e4 | 353 | |
35a17eb6 DM |
354 | #ifdef CONFIG_PCI_MSI |
355 | static void sun4v_msi_enable(unsigned int virt_irq) | |
356 | { | |
357 | sun4v_irq_enable(virt_irq); | |
358 | unmask_msi_irq(virt_irq); | |
359 | } | |
360 | ||
361 | static void sun4v_msi_disable(unsigned int virt_irq) | |
362 | { | |
363 | mask_msi_irq(virt_irq); | |
364 | sun4v_irq_disable(virt_irq); | |
365 | } | |
366 | #endif | |
367 | ||
e18e2a00 DM |
368 | static void sun4v_irq_end(unsigned int virt_irq) |
369 | { | |
370 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
371 | unsigned int ino = bucket - &ivector_table[0]; | |
1da177e4 | 372 | |
e18e2a00 DM |
373 | if (likely(bucket)) { |
374 | int err; | |
1da177e4 | 375 | |
e18e2a00 DM |
376 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
377 | if (err != HV_EOK) | |
378 | printk("sun4v_intr_setstate(%x): " | |
379 | "err(%d)\n", ino, err); | |
1da177e4 | 380 | } |
1da177e4 LT |
381 | } |
382 | ||
e18e2a00 | 383 | static void run_pre_handler(unsigned int virt_irq) |
1da177e4 | 384 | { |
e18e2a00 | 385 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
68c92186 | 386 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 387 | |
e18e2a00 DM |
388 | if (likely(data->pre_handler)) { |
389 | data->pre_handler(__irq_ino(__irq(bucket)), | |
390 | data->pre_handler_arg1, | |
391 | data->pre_handler_arg2); | |
1da177e4 | 392 | } |
088dd1f8 DM |
393 | } |
394 | ||
729e7d7e | 395 | static struct irq_chip sun4u_irq = { |
e18e2a00 DM |
396 | .typename = "sun4u", |
397 | .enable = sun4u_irq_enable, | |
398 | .disable = sun4u_irq_disable, | |
399 | .end = sun4u_irq_end, | |
400 | }; | |
8047e247 | 401 | |
729e7d7e | 402 | static struct irq_chip sun4u_irq_ack = { |
e18e2a00 DM |
403 | .typename = "sun4u+ack", |
404 | .enable = sun4u_irq_enable, | |
405 | .disable = sun4u_irq_disable, | |
406 | .ack = run_pre_handler, | |
407 | .end = sun4u_irq_end, | |
408 | }; | |
088dd1f8 | 409 | |
729e7d7e | 410 | static struct irq_chip sun4v_irq = { |
e18e2a00 DM |
411 | .typename = "sun4v", |
412 | .enable = sun4v_irq_enable, | |
413 | .disable = sun4v_irq_disable, | |
414 | .end = sun4v_irq_end, | |
415 | }; | |
1da177e4 | 416 | |
729e7d7e | 417 | static struct irq_chip sun4v_irq_ack = { |
e18e2a00 DM |
418 | .typename = "sun4v+ack", |
419 | .enable = sun4v_irq_enable, | |
420 | .disable = sun4v_irq_disable, | |
421 | .ack = run_pre_handler, | |
422 | .end = sun4v_irq_end, | |
423 | }; | |
1da177e4 | 424 | |
35a17eb6 DM |
425 | #ifdef CONFIG_PCI_MSI |
426 | static struct irq_chip sun4v_msi = { | |
427 | .typename = "sun4v+msi", | |
428 | .mask = mask_msi_irq, | |
429 | .unmask = unmask_msi_irq, | |
430 | .enable = sun4v_msi_enable, | |
431 | .disable = sun4v_msi_disable, | |
432 | .ack = run_pre_handler, | |
433 | .end = sun4v_irq_end, | |
434 | }; | |
435 | #endif | |
436 | ||
e18e2a00 DM |
437 | void irq_install_pre_handler(int virt_irq, |
438 | void (*func)(unsigned int, void *, void *), | |
439 | void *arg1, void *arg2) | |
440 | { | |
68c92186 DM |
441 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
442 | struct irq_chip *chip; | |
088dd1f8 | 443 | |
e18e2a00 DM |
444 | data->pre_handler = func; |
445 | data->pre_handler_arg1 = arg1; | |
446 | data->pre_handler_arg2 = arg2; | |
1da177e4 | 447 | |
68c92186 DM |
448 | chip = get_irq_chip(virt_irq); |
449 | if (chip == &sun4u_irq_ack || | |
35a17eb6 DM |
450 | chip == &sun4v_irq_ack |
451 | #ifdef CONFIG_PCI_MSI | |
452 | || chip == &sun4v_msi | |
453 | #endif | |
454 | ) | |
24ac26d4 DM |
455 | return; |
456 | ||
68c92186 DM |
457 | chip = (chip == &sun4u_irq ? |
458 | &sun4u_irq_ack : &sun4v_irq_ack); | |
459 | set_irq_chip(virt_irq, chip); | |
e18e2a00 | 460 | } |
1da177e4 | 461 | |
e18e2a00 DM |
462 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
463 | { | |
464 | struct ino_bucket *bucket; | |
465 | struct irq_handler_data *data; | |
e18e2a00 | 466 | int ino; |
1da177e4 | 467 | |
e18e2a00 | 468 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 469 | |
861fe906 | 470 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
e18e2a00 DM |
471 | bucket = &ivector_table[ino]; |
472 | if (!bucket->virt_irq) { | |
473 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
68c92186 | 474 | set_irq_chip(bucket->virt_irq, &sun4u_irq); |
fd0504c3 | 475 | } |
1da177e4 | 476 | |
68c92186 DM |
477 | data = get_irq_chip_data(bucket->virt_irq); |
478 | if (unlikely(data)) | |
e18e2a00 | 479 | goto out; |
fd0504c3 | 480 | |
e18e2a00 DM |
481 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
482 | if (unlikely(!data)) { | |
483 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
484 | prom_halt(); | |
1da177e4 | 485 | } |
68c92186 | 486 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 487 | |
e18e2a00 DM |
488 | data->imap = imap; |
489 | data->iclr = iclr; | |
1da177e4 | 490 | |
e18e2a00 DM |
491 | out: |
492 | return bucket->virt_irq; | |
493 | } | |
1da177e4 | 494 | |
e18e2a00 | 495 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
1da177e4 | 496 | { |
8047e247 | 497 | struct ino_bucket *bucket; |
e18e2a00 DM |
498 | struct irq_handler_data *data; |
499 | unsigned long sysino; | |
8047e247 | 500 | |
e18e2a00 | 501 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 502 | |
e18e2a00 DM |
503 | sysino = sun4v_devino_to_sysino(devhandle, devino); |
504 | bucket = &ivector_table[sysino]; | |
505 | if (!bucket->virt_irq) { | |
506 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
68c92186 | 507 | set_irq_chip(bucket->virt_irq, &sun4v_irq); |
1da177e4 | 508 | } |
1da177e4 | 509 | |
68c92186 DM |
510 | data = get_irq_chip_data(bucket->virt_irq); |
511 | if (unlikely(data)) | |
1da177e4 | 512 | goto out; |
1da177e4 | 513 | |
e18e2a00 DM |
514 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
515 | if (unlikely(!data)) { | |
516 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
517 | prom_halt(); | |
518 | } | |
68c92186 | 519 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 520 | |
e18e2a00 DM |
521 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
522 | * is done by hypervisor calls on sun4v platforms, not by direct | |
523 | * register accesses. | |
524 | */ | |
525 | data->imap = ~0UL; | |
526 | data->iclr = ~0UL; | |
1da177e4 | 527 | |
e18e2a00 DM |
528 | out: |
529 | return bucket->virt_irq; | |
530 | } | |
1da177e4 | 531 | |
35a17eb6 DM |
532 | #ifdef CONFIG_PCI_MSI |
533 | unsigned int sun4v_build_msi(u32 devhandle, unsigned int *virt_irq_p, | |
534 | unsigned int msi_start, unsigned int msi_end) | |
535 | { | |
536 | struct ino_bucket *bucket; | |
537 | struct irq_handler_data *data; | |
538 | unsigned long sysino; | |
539 | unsigned int devino; | |
540 | ||
541 | BUG_ON(tlb_type != hypervisor); | |
542 | ||
543 | /* Find a free devino in the given range. */ | |
544 | for (devino = msi_start; devino < msi_end; devino++) { | |
545 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
546 | bucket = &ivector_table[sysino]; | |
547 | if (!bucket->virt_irq) | |
548 | break; | |
549 | } | |
550 | if (devino >= msi_end) | |
551 | return 0; | |
552 | ||
553 | sysino = sun4v_devino_to_sysino(devhandle, devino); | |
554 | bucket = &ivector_table[sysino]; | |
555 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
556 | *virt_irq_p = bucket->virt_irq; | |
557 | set_irq_chip(bucket->virt_irq, &sun4v_msi); | |
558 | ||
559 | data = get_irq_chip_data(bucket->virt_irq); | |
560 | if (unlikely(data)) | |
561 | return devino; | |
562 | ||
563 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); | |
564 | if (unlikely(!data)) { | |
565 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
566 | prom_halt(); | |
567 | } | |
568 | set_irq_chip_data(bucket->virt_irq, data); | |
569 | ||
570 | data->imap = ~0UL; | |
571 | data->iclr = ~0UL; | |
572 | ||
573 | return devino; | |
574 | } | |
575 | ||
576 | void sun4v_destroy_msi(unsigned int virt_irq) | |
577 | { | |
578 | virt_irq_free(virt_irq); | |
579 | } | |
580 | #endif | |
581 | ||
e18e2a00 DM |
582 | void ack_bad_irq(unsigned int virt_irq) |
583 | { | |
584 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
585 | unsigned int ino = 0xdeadbeef; | |
ab66a50e | 586 | |
e18e2a00 DM |
587 | if (bucket) |
588 | ino = bucket - &ivector_table[0]; | |
6a76267f | 589 | |
e18e2a00 DM |
590 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
591 | ino, virt_irq); | |
1da177e4 LT |
592 | } |
593 | ||
1da177e4 LT |
594 | void handler_irq(int irq, struct pt_regs *regs) |
595 | { | |
e18e2a00 | 596 | struct ino_bucket *bucket; |
6d24c8dc | 597 | struct pt_regs *old_regs; |
1da177e4 | 598 | |
1da177e4 | 599 | clear_softint(1 << irq); |
1da177e4 | 600 | |
6d24c8dc | 601 | old_regs = set_irq_regs(regs); |
1da177e4 | 602 | irq_enter(); |
1da177e4 LT |
603 | |
604 | /* Sliiiick... */ | |
e18e2a00 DM |
605 | bucket = __bucket(xchg32(irq_work(smp_processor_id()), 0)); |
606 | while (bucket) { | |
607 | struct ino_bucket *next = __bucket(bucket->irq_chain); | |
1da177e4 | 608 | |
e18e2a00 | 609 | bucket->irq_chain = 0; |
6d24c8dc | 610 | __do_IRQ(bucket->virt_irq); |
fd0504c3 | 611 | |
e18e2a00 | 612 | bucket = next; |
1da177e4 | 613 | } |
e18e2a00 | 614 | |
1da177e4 | 615 | irq_exit(); |
6d24c8dc | 616 | set_irq_regs(old_regs); |
1da177e4 LT |
617 | } |
618 | ||
cdd5186f DM |
619 | struct sun5_timer { |
620 | u64 count0; | |
621 | u64 limit0; | |
622 | u64 count1; | |
623 | u64 limit1; | |
624 | }; | |
1da177e4 | 625 | |
cdd5186f | 626 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
627 | static u64 prom_limit0, prom_limit1; |
628 | ||
629 | static void map_prom_timers(void) | |
630 | { | |
25c7581b | 631 | struct device_node *dp; |
6a23acf3 | 632 | const unsigned int *addr; |
1da177e4 LT |
633 | |
634 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
635 | dp = of_find_node_by_path("/"); |
636 | dp = dp->child; | |
637 | while (dp) { | |
638 | if (!strcmp(dp->name, "counter-timer")) | |
639 | break; | |
640 | dp = dp->sibling; | |
641 | } | |
1da177e4 LT |
642 | |
643 | /* Assume if node is not present, PROM uses different tick mechanism | |
644 | * which we should not care about. | |
645 | */ | |
25c7581b | 646 | if (!dp) { |
1da177e4 LT |
647 | prom_timers = (struct sun5_timer *) 0; |
648 | return; | |
649 | } | |
650 | ||
651 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
652 | addr = of_get_property(dp, "address", NULL); |
653 | if (!addr) { | |
1da177e4 LT |
654 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
655 | prom_timers = (struct sun5_timer *) 0; | |
656 | return; | |
657 | } | |
658 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
659 | } | |
660 | ||
661 | static void kill_prom_timer(void) | |
662 | { | |
663 | if (!prom_timers) | |
664 | return; | |
665 | ||
666 | /* Save them away for later. */ | |
667 | prom_limit0 = prom_timers->limit0; | |
668 | prom_limit1 = prom_timers->limit1; | |
669 | ||
670 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
671 | * We turn both off here just to be paranoid. | |
672 | */ | |
673 | prom_timers->limit0 = 0; | |
674 | prom_timers->limit1 = 0; | |
675 | ||
676 | /* Wheee, eat the interrupt packet too... */ | |
677 | __asm__ __volatile__( | |
678 | " mov 0x40, %%g2\n" | |
679 | " ldxa [%%g0] %0, %%g1\n" | |
680 | " ldxa [%%g2] %1, %%g1\n" | |
681 | " stxa %%g0, [%%g0] %0\n" | |
682 | " membar #Sync\n" | |
683 | : /* no outputs */ | |
684 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
685 | : "g1", "g2"); | |
686 | } | |
687 | ||
1da177e4 LT |
688 | void init_irqwork_curcpu(void) |
689 | { | |
1da177e4 LT |
690 | int cpu = hard_smp_processor_id(); |
691 | ||
fd0504c3 | 692 | trap_block[cpu].irq_worklist = 0; |
1da177e4 LT |
693 | } |
694 | ||
5cbc3073 DM |
695 | /* Please be very careful with register_one_mondo() and |
696 | * sun4v_register_mondo_queues(). | |
697 | * | |
698 | * On SMP this gets invoked from the CPU trampoline before | |
699 | * the cpu has fully taken over the trap table from OBP, | |
700 | * and it's kernel stack + %g6 thread register state is | |
701 | * not fully cooked yet. | |
702 | * | |
703 | * Therefore you cannot make any OBP calls, not even prom_printf, | |
704 | * from these two routines. | |
705 | */ | |
706 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) | |
ac29c11d | 707 | { |
5cbc3073 | 708 | unsigned long num_entries = (qmask + 1) / 64; |
94f8762d DM |
709 | unsigned long status; |
710 | ||
711 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
712 | if (status != HV_EOK) { | |
713 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
714 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
715 | prom_halt(); |
716 | } | |
717 | } | |
718 | ||
b5a37e96 | 719 | static void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 720 | { |
b5a37e96 DM |
721 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
722 | ||
5cbc3073 DM |
723 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
724 | tb->cpu_mondo_qmask); | |
725 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, | |
726 | tb->dev_mondo_qmask); | |
727 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, | |
728 | tb->resum_qmask); | |
729 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, | |
730 | tb->nonresum_qmask); | |
b5a37e96 DM |
731 | } |
732 | ||
5cbc3073 | 733 | static void __cpuinit alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask, int use_bootmem) |
b5a37e96 | 734 | { |
5cbc3073 DM |
735 | unsigned long size = PAGE_ALIGN(qmask + 1); |
736 | unsigned long order = get_order(size); | |
737 | void *p = NULL; | |
b5a37e96 | 738 | |
5cbc3073 DM |
739 | if (use_bootmem) { |
740 | p = __alloc_bootmem_low(size, size, 0); | |
741 | } else { | |
742 | struct page *page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, order); | |
743 | if (page) | |
744 | p = page_address(page); | |
745 | } | |
b5a37e96 | 746 | |
5cbc3073 | 747 | if (!p) { |
b5a37e96 DM |
748 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); |
749 | prom_halt(); | |
750 | } | |
751 | ||
5cbc3073 | 752 | *pa_ptr = __pa(p); |
b5a37e96 DM |
753 | } |
754 | ||
5cbc3073 | 755 | static void __cpuinit alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask, int use_bootmem) |
b5a37e96 | 756 | { |
5cbc3073 DM |
757 | unsigned long size = PAGE_ALIGN(qmask + 1); |
758 | unsigned long order = get_order(size); | |
759 | void *p = NULL; | |
b5a37e96 | 760 | |
5cbc3073 DM |
761 | if (use_bootmem) { |
762 | p = __alloc_bootmem_low(size, size, 0); | |
763 | } else { | |
764 | struct page *page = alloc_pages(GFP_ATOMIC | __GFP_ZERO, order); | |
765 | if (page) | |
766 | p = page_address(page); | |
767 | } | |
5b0c0572 | 768 | |
5cbc3073 | 769 | if (!p) { |
5b0c0572 DM |
770 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); |
771 | prom_halt(); | |
772 | } | |
773 | ||
5cbc3073 | 774 | *pa_ptr = __pa(p); |
5b0c0572 DM |
775 | } |
776 | ||
b5a37e96 | 777 | static void __cpuinit init_cpu_send_mondo_info(struct trap_per_cpu *tb, int use_bootmem) |
1d2f1f90 DM |
778 | { |
779 | #ifdef CONFIG_SMP | |
b5a37e96 | 780 | void *page; |
1d2f1f90 DM |
781 | |
782 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
783 | ||
b5a37e96 DM |
784 | if (use_bootmem) |
785 | page = alloc_bootmem_low_pages(PAGE_SIZE); | |
786 | else | |
787 | page = (void *) get_zeroed_page(GFP_ATOMIC); | |
788 | ||
1d2f1f90 DM |
789 | if (!page) { |
790 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
791 | prom_halt(); | |
792 | } | |
793 | ||
794 | tb->cpu_mondo_block_pa = __pa(page); | |
795 | tb->cpu_list_pa = __pa(page + 64); | |
796 | #endif | |
797 | } | |
798 | ||
b5a37e96 | 799 | /* Allocate and register the mondo and error queues for this cpu. */ |
72aff53f | 800 | void __cpuinit sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load) |
ac29c11d | 801 | { |
ac29c11d DM |
802 | struct trap_per_cpu *tb = &trap_block[cpu]; |
803 | ||
72aff53f | 804 | if (alloc) { |
5cbc3073 DM |
805 | alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask, use_bootmem); |
806 | alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask, use_bootmem); | |
807 | alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask, use_bootmem); | |
808 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask, use_bootmem); | |
809 | alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask, use_bootmem); | |
810 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, tb->nonresum_qmask, use_bootmem); | |
1d2f1f90 | 811 | |
72aff53f DM |
812 | init_cpu_send_mondo_info(tb, use_bootmem); |
813 | } | |
1d2f1f90 | 814 | |
72aff53f DM |
815 | if (load) { |
816 | if (cpu != hard_smp_processor_id()) { | |
817 | prom_printf("SUN4V: init mondo on cpu %d not %d\n", | |
818 | cpu, hard_smp_processor_id()); | |
819 | prom_halt(); | |
820 | } | |
821 | sun4v_register_mondo_queues(cpu); | |
822 | } | |
ac29c11d DM |
823 | } |
824 | ||
e18e2a00 DM |
825 | static struct irqaction timer_irq_action = { |
826 | .name = "timer", | |
827 | }; | |
828 | ||
1da177e4 LT |
829 | /* Only invoked on boot processor. */ |
830 | void __init init_IRQ(void) | |
831 | { | |
832 | map_prom_timers(); | |
833 | kill_prom_timer(); | |
834 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
835 | ||
ac29c11d | 836 | if (tlb_type == hypervisor) |
72aff53f | 837 | sun4v_init_mondo_queues(1, hard_smp_processor_id(), 1, 1); |
ac29c11d | 838 | |
1da177e4 LT |
839 | /* We need to clear any IRQ's pending in the soft interrupt |
840 | * registers, a spurious one could be left around from the | |
841 | * PROM timer which we just disabled. | |
842 | */ | |
843 | clear_softint(get_softint()); | |
844 | ||
845 | /* Now that ivector table is initialized, it is safe | |
846 | * to receive IRQ vector traps. We will normally take | |
847 | * one or two right now, in case some device PROM used | |
848 | * to boot us wants to speak to us. We just ignore them. | |
849 | */ | |
850 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
851 | "or %%g1, %0, %%g1\n\t" | |
852 | "wrpr %%g1, 0x0, %%pstate" | |
853 | : /* No outputs */ | |
854 | : "i" (PSTATE_IE) | |
855 | : "g1"); | |
1da177e4 | 856 | |
e18e2a00 | 857 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 858 | } |