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4a907dec | 1 | /* irq.c: UltraSparc IRQ handling/init/registry. |
1da177e4 | 2 | * |
4a907dec | 3 | * Copyright (C) 1997, 2007 David S. Miller (davem@davemloft.net) |
1da177e4 LT |
4 | * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be) |
5 | * Copyright (C) 1998 Jakub Jelinek (jj@ultra.linux.cz) | |
6 | */ | |
7 | ||
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/sched.h> | |
10 | #include <linux/ptrace.h> | |
11 | #include <linux/errno.h> | |
12 | #include <linux/kernel_stat.h> | |
13 | #include <linux/signal.h> | |
14 | #include <linux/mm.h> | |
15 | #include <linux/interrupt.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/random.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/delay.h> | |
20 | #include <linux/proc_fs.h> | |
21 | #include <linux/seq_file.h> | |
b5a37e96 | 22 | #include <linux/bootmem.h> |
e18e2a00 | 23 | #include <linux/irq.h> |
1da177e4 LT |
24 | |
25 | #include <asm/ptrace.h> | |
26 | #include <asm/processor.h> | |
27 | #include <asm/atomic.h> | |
28 | #include <asm/system.h> | |
29 | #include <asm/irq.h> | |
2e457ef6 | 30 | #include <asm/io.h> |
1da177e4 LT |
31 | #include <asm/sbus.h> |
32 | #include <asm/iommu.h> | |
33 | #include <asm/upa.h> | |
34 | #include <asm/oplib.h> | |
25c7581b | 35 | #include <asm/prom.h> |
1da177e4 LT |
36 | #include <asm/timer.h> |
37 | #include <asm/smp.h> | |
38 | #include <asm/starfire.h> | |
39 | #include <asm/uaccess.h> | |
40 | #include <asm/cache.h> | |
41 | #include <asm/cpudata.h> | |
63b61452 | 42 | #include <asm/auxio.h> |
92704a1c | 43 | #include <asm/head.h> |
4a907dec | 44 | #include <asm/hypervisor.h> |
1da177e4 | 45 | |
1da177e4 LT |
46 | /* UPA nodes send interrupt packet to UltraSparc with first data reg |
47 | * value low 5 (7 on Starfire) bits holding the IRQ identifier being | |
48 | * delivered. We must translate this into a non-vector IRQ so we can | |
49 | * set the softint on this cpu. | |
50 | * | |
51 | * To make processing these packets efficient and race free we use | |
52 | * an array of irq buckets below. The interrupt vector handler in | |
53 | * entry.S feeds incoming packets into per-cpu pil-indexed lists. | |
54 | * The IVEC handler does not need to act atomically, the PIL dispatch | |
55 | * code uses CAS to get an atomic snapshot of the list and clear it | |
56 | * at the same time. | |
e18e2a00 DM |
57 | * |
58 | * If you make changes to ino_bucket, please update hand coded assembler | |
59 | * of the vectored interrupt trap handler(s) in entry.S and sun4v_ivec.S | |
1da177e4 | 60 | */ |
e18e2a00 | 61 | struct ino_bucket { |
a650d383 | 62 | /*0x00*/unsigned long irq_chain; |
1da177e4 | 63 | |
e18e2a00 | 64 | /* Virtual interrupt number assigned to this INO. */ |
a650d383 DM |
65 | /*0x08*/unsigned int virt_irq; |
66 | /*0x0c*/unsigned int __pad; | |
e18e2a00 DM |
67 | }; |
68 | ||
69 | #define NUM_IVECS (IMAP_INR + 1) | |
1da177e4 LT |
70 | struct ino_bucket ivector_table[NUM_IVECS] __attribute__ ((aligned (SMP_CACHE_BYTES))); |
71 | ||
e18e2a00 | 72 | #define __irq_ino(irq) \ |
a650d383 DM |
73 | (((struct ino_bucket *)(irq)) - &ivector_table[0]) |
74 | #define __bucket(irq) ((struct ino_bucket *)(irq)) | |
75 | #define __irq(bucket) ((unsigned long)(bucket)) | |
e18e2a00 | 76 | |
1da177e4 LT |
77 | /* This has to be in the main kernel image, it cannot be |
78 | * turned into per-cpu data. The reason is that the main | |
79 | * kernel image is locked into the TLB and this structure | |
80 | * is accessed from the vectored interrupt trap handler. If | |
81 | * access to this structure takes a TLB miss it could cause | |
82 | * the 5-level sparc v9 trap stack to overflow. | |
83 | */ | |
fd0504c3 | 84 | #define irq_work(__cpu) &(trap_block[(__cpu)].irq_worklist) |
1da177e4 | 85 | |
93b3238e | 86 | static struct { |
a650d383 | 87 | unsigned long irq; |
93b3238e DM |
88 | unsigned int dev_handle; |
89 | unsigned int dev_ino; | |
90 | } virt_to_real_irq_table[NR_IRQS]; | |
759f89e0 | 91 | static DEFINE_SPINLOCK(virt_irq_alloc_lock); |
8047e247 | 92 | |
a650d383 | 93 | unsigned char virt_irq_alloc(unsigned long real_irq) |
8047e247 | 94 | { |
759f89e0 | 95 | unsigned long flags; |
8047e247 DM |
96 | unsigned char ent; |
97 | ||
98 | BUILD_BUG_ON(NR_IRQS >= 256); | |
99 | ||
759f89e0 DM |
100 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
101 | ||
35a17eb6 | 102 | for (ent = 1; ent < NR_IRQS; ent++) { |
93b3238e | 103 | if (!virt_to_real_irq_table[ent].irq) |
35a17eb6 DM |
104 | break; |
105 | } | |
8047e247 DM |
106 | if (ent >= NR_IRQS) { |
107 | printk(KERN_ERR "IRQ: Out of virtual IRQs.\n"); | |
759f89e0 DM |
108 | ent = 0; |
109 | } else { | |
110 | virt_to_real_irq_table[ent].irq = real_irq; | |
8047e247 DM |
111 | } |
112 | ||
759f89e0 | 113 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 DM |
114 | |
115 | return ent; | |
116 | } | |
117 | ||
5746c99d | 118 | #ifdef CONFIG_PCI_MSI |
759f89e0 | 119 | void virt_irq_free(unsigned int virt_irq) |
8047e247 | 120 | { |
759f89e0 | 121 | unsigned long flags; |
8047e247 | 122 | |
35a17eb6 DM |
123 | if (virt_irq >= NR_IRQS) |
124 | return; | |
125 | ||
759f89e0 DM |
126 | spin_lock_irqsave(&virt_irq_alloc_lock, flags); |
127 | ||
93b3238e | 128 | virt_to_real_irq_table[virt_irq].irq = 0; |
35a17eb6 | 129 | |
759f89e0 | 130 | spin_unlock_irqrestore(&virt_irq_alloc_lock, flags); |
8047e247 | 131 | } |
5746c99d | 132 | #endif |
8047e247 | 133 | |
a650d383 | 134 | static unsigned long virt_to_real_irq(unsigned char virt_irq) |
8047e247 | 135 | { |
93b3238e | 136 | return virt_to_real_irq_table[virt_irq].irq; |
8047e247 DM |
137 | } |
138 | ||
1da177e4 | 139 | /* |
e18e2a00 | 140 | * /proc/interrupts printing: |
1da177e4 | 141 | */ |
1da177e4 LT |
142 | |
143 | int show_interrupts(struct seq_file *p, void *v) | |
144 | { | |
e18e2a00 DM |
145 | int i = *(loff_t *) v, j; |
146 | struct irqaction * action; | |
1da177e4 | 147 | unsigned long flags; |
1da177e4 | 148 | |
e18e2a00 DM |
149 | if (i == 0) { |
150 | seq_printf(p, " "); | |
151 | for_each_online_cpu(j) | |
152 | seq_printf(p, "CPU%d ",j); | |
153 | seq_putc(p, '\n'); | |
154 | } | |
155 | ||
156 | if (i < NR_IRQS) { | |
157 | spin_lock_irqsave(&irq_desc[i].lock, flags); | |
158 | action = irq_desc[i].action; | |
159 | if (!action) | |
160 | goto skip; | |
161 | seq_printf(p, "%3d: ",i); | |
1da177e4 LT |
162 | #ifndef CONFIG_SMP |
163 | seq_printf(p, "%10u ", kstat_irqs(i)); | |
164 | #else | |
e18e2a00 DM |
165 | for_each_online_cpu(j) |
166 | seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); | |
1da177e4 | 167 | #endif |
d1bef4ed | 168 | seq_printf(p, " %9s", irq_desc[i].chip->typename); |
e18e2a00 DM |
169 | seq_printf(p, " %s", action->name); |
170 | ||
171 | for (action=action->next; action; action = action->next) | |
37cdcd9e | 172 | seq_printf(p, ", %s", action->name); |
e18e2a00 | 173 | |
1da177e4 | 174 | seq_putc(p, '\n'); |
e18e2a00 DM |
175 | skip: |
176 | spin_unlock_irqrestore(&irq_desc[i].lock, flags); | |
1da177e4 | 177 | } |
1da177e4 LT |
178 | return 0; |
179 | } | |
180 | ||
ebd8c56c DM |
181 | static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid) |
182 | { | |
183 | unsigned int tid; | |
184 | ||
185 | if (this_is_starfire) { | |
186 | tid = starfire_translate(imap, cpuid); | |
187 | tid <<= IMAP_TID_SHIFT; | |
188 | tid &= IMAP_TID_UPA; | |
189 | } else { | |
190 | if (tlb_type == cheetah || tlb_type == cheetah_plus) { | |
191 | unsigned long ver; | |
192 | ||
193 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
194 | if ((ver >> 32UL) == __JALAPENO_ID || | |
195 | (ver >> 32UL) == __SERRANO_ID) { | |
196 | tid = cpuid << IMAP_TID_SHIFT; | |
197 | tid &= IMAP_TID_JBUS; | |
198 | } else { | |
199 | unsigned int a = cpuid & 0x1f; | |
200 | unsigned int n = (cpuid >> 5) & 0x1f; | |
201 | ||
202 | tid = ((a << IMAP_AID_SHIFT) | | |
203 | (n << IMAP_NID_SHIFT)); | |
204 | tid &= (IMAP_AID_SAFARI | | |
205 | IMAP_NID_SAFARI);; | |
206 | } | |
207 | } else { | |
208 | tid = cpuid << IMAP_TID_SHIFT; | |
209 | tid &= IMAP_TID_UPA; | |
210 | } | |
211 | } | |
212 | ||
213 | return tid; | |
214 | } | |
215 | ||
e18e2a00 DM |
216 | struct irq_handler_data { |
217 | unsigned long iclr; | |
218 | unsigned long imap; | |
8047e247 | 219 | |
e18e2a00 DM |
220 | void (*pre_handler)(unsigned int, void *, void *); |
221 | void *pre_handler_arg1; | |
222 | void *pre_handler_arg2; | |
223 | }; | |
1da177e4 | 224 | |
e18e2a00 | 225 | static inline struct ino_bucket *virt_irq_to_bucket(unsigned int virt_irq) |
1da177e4 | 226 | { |
a650d383 | 227 | unsigned long real_irq = virt_to_real_irq(virt_irq); |
e18e2a00 | 228 | struct ino_bucket *bucket = NULL; |
1da177e4 | 229 | |
e18e2a00 DM |
230 | if (likely(real_irq)) |
231 | bucket = __bucket(real_irq); | |
8047e247 | 232 | |
e18e2a00 | 233 | return bucket; |
1da177e4 LT |
234 | } |
235 | ||
e18e2a00 DM |
236 | #ifdef CONFIG_SMP |
237 | static int irq_choose_cpu(unsigned int virt_irq) | |
088dd1f8 | 238 | { |
a53da52f | 239 | cpumask_t mask = irq_desc[virt_irq].affinity; |
e18e2a00 | 240 | int cpuid; |
088dd1f8 | 241 | |
e18e2a00 DM |
242 | if (cpus_equal(mask, CPU_MASK_ALL)) { |
243 | static int irq_rover; | |
244 | static DEFINE_SPINLOCK(irq_rover_lock); | |
245 | unsigned long flags; | |
1da177e4 | 246 | |
e18e2a00 DM |
247 | /* Round-robin distribution... */ |
248 | do_round_robin: | |
249 | spin_lock_irqsave(&irq_rover_lock, flags); | |
10951ee6 | 250 | |
e18e2a00 DM |
251 | while (!cpu_online(irq_rover)) { |
252 | if (++irq_rover >= NR_CPUS) | |
253 | irq_rover = 0; | |
254 | } | |
255 | cpuid = irq_rover; | |
256 | do { | |
257 | if (++irq_rover >= NR_CPUS) | |
258 | irq_rover = 0; | |
259 | } while (!cpu_online(irq_rover)); | |
1da177e4 | 260 | |
e18e2a00 DM |
261 | spin_unlock_irqrestore(&irq_rover_lock, flags); |
262 | } else { | |
263 | cpumask_t tmp; | |
088dd1f8 | 264 | |
e18e2a00 | 265 | cpus_and(tmp, cpu_online_map, mask); |
088dd1f8 | 266 | |
e18e2a00 DM |
267 | if (cpus_empty(tmp)) |
268 | goto do_round_robin; | |
088dd1f8 | 269 | |
e18e2a00 | 270 | cpuid = first_cpu(tmp); |
1da177e4 | 271 | } |
088dd1f8 | 272 | |
e18e2a00 DM |
273 | return cpuid; |
274 | } | |
275 | #else | |
276 | static int irq_choose_cpu(unsigned int virt_irq) | |
277 | { | |
278 | return real_hard_smp_processor_id(); | |
1da177e4 | 279 | } |
e18e2a00 | 280 | #endif |
1da177e4 | 281 | |
e18e2a00 | 282 | static void sun4u_irq_enable(unsigned int virt_irq) |
e3999574 | 283 | { |
68c92186 | 284 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
e3999574 | 285 | |
e18e2a00 | 286 | if (likely(data)) { |
861fe906 | 287 | unsigned long cpuid, imap, val; |
e18e2a00 | 288 | unsigned int tid; |
e3999574 | 289 | |
e18e2a00 DM |
290 | cpuid = irq_choose_cpu(virt_irq); |
291 | imap = data->imap; | |
e3999574 | 292 | |
e18e2a00 | 293 | tid = sun4u_compute_tid(imap, cpuid); |
e3999574 | 294 | |
861fe906 DM |
295 | val = upa_readq(imap); |
296 | val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS | | |
297 | IMAP_AID_SAFARI | IMAP_NID_SAFARI); | |
298 | val |= tid | IMAP_VALID; | |
299 | upa_writeq(val, imap); | |
e3999574 | 300 | } |
e3999574 DM |
301 | } |
302 | ||
b53bcb67 DM |
303 | static void sun4u_set_affinity(unsigned int virt_irq, cpumask_t mask) |
304 | { | |
305 | sun4u_irq_enable(virt_irq); | |
306 | } | |
307 | ||
e18e2a00 | 308 | static void sun4u_irq_disable(unsigned int virt_irq) |
1da177e4 | 309 | { |
68c92186 | 310 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 311 | |
e18e2a00 DM |
312 | if (likely(data)) { |
313 | unsigned long imap = data->imap; | |
6e69d606 | 314 | unsigned long tmp = upa_readq(imap); |
1da177e4 | 315 | |
e18e2a00 | 316 | tmp &= ~IMAP_VALID; |
861fe906 | 317 | upa_writeq(tmp, imap); |
088dd1f8 | 318 | } |
088dd1f8 DM |
319 | } |
320 | ||
e18e2a00 | 321 | static void sun4u_irq_end(unsigned int virt_irq) |
088dd1f8 | 322 | { |
68c92186 | 323 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
5a606b72 DM |
324 | struct irq_desc *desc = irq_desc + virt_irq; |
325 | ||
326 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
327 | return; | |
088dd1f8 | 328 | |
e18e2a00 | 329 | if (likely(data)) |
861fe906 | 330 | upa_writeq(ICLR_IDLE, data->iclr); |
088dd1f8 DM |
331 | } |
332 | ||
e18e2a00 | 333 | static void sun4v_irq_enable(unsigned int virt_irq) |
088dd1f8 | 334 | { |
e18e2a00 DM |
335 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
336 | unsigned int ino = bucket - &ivector_table[0]; | |
088dd1f8 | 337 | |
e18e2a00 DM |
338 | if (likely(bucket)) { |
339 | unsigned long cpuid; | |
340 | int err; | |
088dd1f8 | 341 | |
e18e2a00 | 342 | cpuid = irq_choose_cpu(virt_irq); |
088dd1f8 | 343 | |
e18e2a00 DM |
344 | err = sun4v_intr_settarget(ino, cpuid); |
345 | if (err != HV_EOK) | |
e83fb17f DM |
346 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " |
347 | "err(%d)\n", ino, cpuid, err); | |
a357b8f4 DM |
348 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
349 | if (err != HV_EOK) | |
e83fb17f | 350 | printk(KERN_ERR "sun4v_intr_setstate(%x): " |
a357b8f4 | 351 | "err(%d)\n", ino, err); |
e18e2a00 DM |
352 | err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED); |
353 | if (err != HV_EOK) | |
e83fb17f | 354 | printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n", |
e18e2a00 | 355 | ino, err); |
088dd1f8 | 356 | } |
088dd1f8 DM |
357 | } |
358 | ||
b53bcb67 DM |
359 | static void sun4v_set_affinity(unsigned int virt_irq, cpumask_t mask) |
360 | { | |
361 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
362 | unsigned int ino = bucket - &ivector_table[0]; | |
363 | ||
364 | if (likely(bucket)) { | |
365 | unsigned long cpuid; | |
366 | int err; | |
367 | ||
368 | cpuid = irq_choose_cpu(virt_irq); | |
369 | ||
370 | err = sun4v_intr_settarget(ino, cpuid); | |
371 | if (err != HV_EOK) | |
e83fb17f DM |
372 | printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): " |
373 | "err(%d)\n", ino, cpuid, err); | |
b53bcb67 DM |
374 | } |
375 | } | |
376 | ||
e18e2a00 | 377 | static void sun4v_irq_disable(unsigned int virt_irq) |
1da177e4 | 378 | { |
e18e2a00 DM |
379 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
380 | unsigned int ino = bucket - &ivector_table[0]; | |
1da177e4 | 381 | |
e18e2a00 DM |
382 | if (likely(bucket)) { |
383 | int err; | |
1da177e4 | 384 | |
e18e2a00 DM |
385 | err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED); |
386 | if (err != HV_EOK) | |
e83fb17f | 387 | printk(KERN_ERR "sun4v_intr_setenabled(%x): " |
e18e2a00 | 388 | "err(%d)\n", ino, err); |
1da177e4 | 389 | } |
e18e2a00 | 390 | } |
1da177e4 | 391 | |
e18e2a00 DM |
392 | static void sun4v_irq_end(unsigned int virt_irq) |
393 | { | |
394 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
395 | unsigned int ino = bucket - &ivector_table[0]; | |
5a606b72 DM |
396 | struct irq_desc *desc = irq_desc + virt_irq; |
397 | ||
398 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
399 | return; | |
1da177e4 | 400 | |
e18e2a00 DM |
401 | if (likely(bucket)) { |
402 | int err; | |
1da177e4 | 403 | |
e18e2a00 DM |
404 | err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE); |
405 | if (err != HV_EOK) | |
e83fb17f | 406 | printk(KERN_ERR "sun4v_intr_setstate(%x): " |
e18e2a00 | 407 | "err(%d)\n", ino, err); |
1da177e4 | 408 | } |
1da177e4 LT |
409 | } |
410 | ||
4a907dec DM |
411 | static void sun4v_virq_enable(unsigned int virt_irq) |
412 | { | |
413 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
4a907dec DM |
414 | |
415 | if (likely(bucket)) { | |
416 | unsigned long cpuid, dev_handle, dev_ino; | |
417 | int err; | |
418 | ||
419 | cpuid = irq_choose_cpu(virt_irq); | |
420 | ||
93b3238e DM |
421 | dev_handle = virt_to_real_irq_table[virt_irq].dev_handle; |
422 | dev_ino = virt_to_real_irq_table[virt_irq].dev_ino; | |
4a907dec DM |
423 | |
424 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
425 | if (err != HV_EOK) | |
e83fb17f | 426 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " |
4a907dec DM |
427 | "err(%d)\n", |
428 | dev_handle, dev_ino, cpuid, err); | |
429 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
12450884 DM |
430 | HV_INTR_STATE_IDLE); |
431 | if (err != HV_EOK) | |
e83fb17f | 432 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
12450884 DM |
433 | "HV_INTR_STATE_IDLE): err(%d)\n", |
434 | dev_handle, dev_ino, err); | |
435 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, | |
4a907dec DM |
436 | HV_INTR_ENABLED); |
437 | if (err != HV_EOK) | |
e83fb17f | 438 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
4a907dec DM |
439 | "HV_INTR_ENABLED): err(%d)\n", |
440 | dev_handle, dev_ino, err); | |
441 | } | |
442 | } | |
443 | ||
b53bcb67 DM |
444 | static void sun4v_virt_set_affinity(unsigned int virt_irq, cpumask_t mask) |
445 | { | |
446 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
b53bcb67 DM |
447 | |
448 | if (likely(bucket)) { | |
449 | unsigned long cpuid, dev_handle, dev_ino; | |
450 | int err; | |
451 | ||
452 | cpuid = irq_choose_cpu(virt_irq); | |
453 | ||
93b3238e DM |
454 | dev_handle = virt_to_real_irq_table[virt_irq].dev_handle; |
455 | dev_ino = virt_to_real_irq_table[virt_irq].dev_ino; | |
b53bcb67 DM |
456 | |
457 | err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid); | |
458 | if (err != HV_EOK) | |
e83fb17f | 459 | printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): " |
b53bcb67 DM |
460 | "err(%d)\n", |
461 | dev_handle, dev_ino, cpuid, err); | |
462 | } | |
463 | } | |
464 | ||
4a907dec DM |
465 | static void sun4v_virq_disable(unsigned int virt_irq) |
466 | { | |
467 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
4a907dec DM |
468 | |
469 | if (likely(bucket)) { | |
470 | unsigned long dev_handle, dev_ino; | |
471 | int err; | |
472 | ||
93b3238e DM |
473 | dev_handle = virt_to_real_irq_table[virt_irq].dev_handle; |
474 | dev_ino = virt_to_real_irq_table[virt_irq].dev_ino; | |
4a907dec | 475 | |
12450884 | 476 | err = sun4v_vintr_set_valid(dev_handle, dev_ino, |
4a907dec DM |
477 | HV_INTR_DISABLED); |
478 | if (err != HV_EOK) | |
e83fb17f | 479 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
4a907dec DM |
480 | "HV_INTR_DISABLED): err(%d)\n", |
481 | dev_handle, dev_ino, err); | |
482 | } | |
483 | } | |
484 | ||
485 | static void sun4v_virq_end(unsigned int virt_irq) | |
486 | { | |
487 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
5a606b72 DM |
488 | struct irq_desc *desc = irq_desc + virt_irq; |
489 | ||
490 | if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))) | |
491 | return; | |
4a907dec DM |
492 | |
493 | if (likely(bucket)) { | |
494 | unsigned long dev_handle, dev_ino; | |
495 | int err; | |
496 | ||
93b3238e DM |
497 | dev_handle = virt_to_real_irq_table[virt_irq].dev_handle; |
498 | dev_ino = virt_to_real_irq_table[virt_irq].dev_ino; | |
4a907dec DM |
499 | |
500 | err = sun4v_vintr_set_state(dev_handle, dev_ino, | |
501 | HV_INTR_STATE_IDLE); | |
502 | if (err != HV_EOK) | |
e83fb17f | 503 | printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx," |
4a907dec DM |
504 | "HV_INTR_STATE_IDLE): err(%d)\n", |
505 | dev_handle, dev_ino, err); | |
506 | } | |
507 | } | |
508 | ||
e18e2a00 | 509 | static void run_pre_handler(unsigned int virt_irq) |
1da177e4 | 510 | { |
e18e2a00 | 511 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); |
68c92186 | 512 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
1da177e4 | 513 | |
e18e2a00 DM |
514 | if (likely(data->pre_handler)) { |
515 | data->pre_handler(__irq_ino(__irq(bucket)), | |
516 | data->pre_handler_arg1, | |
517 | data->pre_handler_arg2); | |
1da177e4 | 518 | } |
088dd1f8 DM |
519 | } |
520 | ||
729e7d7e | 521 | static struct irq_chip sun4u_irq = { |
e18e2a00 DM |
522 | .typename = "sun4u", |
523 | .enable = sun4u_irq_enable, | |
524 | .disable = sun4u_irq_disable, | |
525 | .end = sun4u_irq_end, | |
b53bcb67 | 526 | .set_affinity = sun4u_set_affinity, |
e18e2a00 | 527 | }; |
8047e247 | 528 | |
729e7d7e | 529 | static struct irq_chip sun4u_irq_ack = { |
e18e2a00 DM |
530 | .typename = "sun4u+ack", |
531 | .enable = sun4u_irq_enable, | |
532 | .disable = sun4u_irq_disable, | |
533 | .ack = run_pre_handler, | |
534 | .end = sun4u_irq_end, | |
b53bcb67 | 535 | .set_affinity = sun4u_set_affinity, |
e18e2a00 | 536 | }; |
088dd1f8 | 537 | |
729e7d7e | 538 | static struct irq_chip sun4v_irq = { |
e18e2a00 DM |
539 | .typename = "sun4v", |
540 | .enable = sun4v_irq_enable, | |
541 | .disable = sun4v_irq_disable, | |
542 | .end = sun4v_irq_end, | |
b53bcb67 | 543 | .set_affinity = sun4v_set_affinity, |
e18e2a00 | 544 | }; |
1da177e4 | 545 | |
4a907dec DM |
546 | static struct irq_chip sun4v_virq = { |
547 | .typename = "vsun4v", | |
548 | .enable = sun4v_virq_enable, | |
549 | .disable = sun4v_virq_disable, | |
550 | .end = sun4v_virq_end, | |
b53bcb67 | 551 | .set_affinity = sun4v_virt_set_affinity, |
4a907dec DM |
552 | }; |
553 | ||
e18e2a00 DM |
554 | void irq_install_pre_handler(int virt_irq, |
555 | void (*func)(unsigned int, void *, void *), | |
556 | void *arg1, void *arg2) | |
557 | { | |
68c92186 | 558 | struct irq_handler_data *data = get_irq_chip_data(virt_irq); |
759f89e0 DM |
559 | struct irq_chip *chip = get_irq_chip(virt_irq); |
560 | ||
561 | if (WARN_ON(chip == &sun4v_irq || chip == &sun4v_virq)) { | |
562 | printk(KERN_ERR "IRQ: Trying to install pre-handler on " | |
563 | "sun4v irq %u\n", virt_irq); | |
564 | return; | |
565 | } | |
088dd1f8 | 566 | |
e18e2a00 DM |
567 | data->pre_handler = func; |
568 | data->pre_handler_arg1 = arg1; | |
569 | data->pre_handler_arg2 = arg2; | |
1da177e4 | 570 | |
759f89e0 | 571 | if (chip == &sun4u_irq_ack) |
24ac26d4 DM |
572 | return; |
573 | ||
759f89e0 | 574 | set_irq_chip(virt_irq, &sun4u_irq_ack); |
e18e2a00 | 575 | } |
1da177e4 | 576 | |
e18e2a00 DM |
577 | unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap) |
578 | { | |
579 | struct ino_bucket *bucket; | |
580 | struct irq_handler_data *data; | |
e18e2a00 | 581 | int ino; |
1da177e4 | 582 | |
e18e2a00 | 583 | BUG_ON(tlb_type == hypervisor); |
088dd1f8 | 584 | |
861fe906 | 585 | ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup; |
e18e2a00 DM |
586 | bucket = &ivector_table[ino]; |
587 | if (!bucket->virt_irq) { | |
588 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
68c92186 | 589 | set_irq_chip(bucket->virt_irq, &sun4u_irq); |
fd0504c3 | 590 | } |
1da177e4 | 591 | |
68c92186 DM |
592 | data = get_irq_chip_data(bucket->virt_irq); |
593 | if (unlikely(data)) | |
e18e2a00 | 594 | goto out; |
fd0504c3 | 595 | |
e18e2a00 DM |
596 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
597 | if (unlikely(!data)) { | |
598 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
599 | prom_halt(); | |
1da177e4 | 600 | } |
68c92186 | 601 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 602 | |
e18e2a00 DM |
603 | data->imap = imap; |
604 | data->iclr = iclr; | |
1da177e4 | 605 | |
e18e2a00 DM |
606 | out: |
607 | return bucket->virt_irq; | |
608 | } | |
1da177e4 | 609 | |
4a907dec DM |
610 | static unsigned int sun4v_build_common(unsigned long sysino, |
611 | struct irq_chip *chip) | |
1da177e4 | 612 | { |
8047e247 | 613 | struct ino_bucket *bucket; |
e18e2a00 | 614 | struct irq_handler_data *data; |
8047e247 | 615 | |
e18e2a00 | 616 | BUG_ON(tlb_type != hypervisor); |
1da177e4 | 617 | |
e18e2a00 DM |
618 | bucket = &ivector_table[sysino]; |
619 | if (!bucket->virt_irq) { | |
620 | bucket->virt_irq = virt_irq_alloc(__irq(bucket)); | |
4a907dec | 621 | set_irq_chip(bucket->virt_irq, chip); |
1da177e4 | 622 | } |
1da177e4 | 623 | |
68c92186 DM |
624 | data = get_irq_chip_data(bucket->virt_irq); |
625 | if (unlikely(data)) | |
1da177e4 | 626 | goto out; |
1da177e4 | 627 | |
e18e2a00 DM |
628 | data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC); |
629 | if (unlikely(!data)) { | |
630 | prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n"); | |
631 | prom_halt(); | |
632 | } | |
68c92186 | 633 | set_irq_chip_data(bucket->virt_irq, data); |
1da177e4 | 634 | |
e18e2a00 DM |
635 | /* Catch accidental accesses to these things. IMAP/ICLR handling |
636 | * is done by hypervisor calls on sun4v platforms, not by direct | |
637 | * register accesses. | |
638 | */ | |
639 | data->imap = ~0UL; | |
640 | data->iclr = ~0UL; | |
1da177e4 | 641 | |
e18e2a00 DM |
642 | out: |
643 | return bucket->virt_irq; | |
644 | } | |
1da177e4 | 645 | |
4a907dec DM |
646 | unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino) |
647 | { | |
648 | unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino); | |
649 | ||
650 | return sun4v_build_common(sysino, &sun4v_irq); | |
651 | } | |
652 | ||
653 | unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino) | |
654 | { | |
655 | unsigned long sysino, hv_err; | |
93b3238e | 656 | unsigned int virq; |
4a907dec | 657 | |
5f7426c0 | 658 | BUG_ON(devhandle & devino); |
4a907dec DM |
659 | |
660 | sysino = devhandle | devino; | |
5f7426c0 | 661 | BUG_ON(sysino & ~(IMAP_IGN | IMAP_INO)); |
4a907dec DM |
662 | |
663 | hv_err = sun4v_vintr_set_cookie(devhandle, devino, sysino); | |
664 | if (hv_err) { | |
665 | prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] " | |
666 | "err=%lu\n", devhandle, devino, hv_err); | |
667 | prom_halt(); | |
668 | } | |
669 | ||
93b3238e DM |
670 | virq = sun4v_build_common(sysino, &sun4v_virq); |
671 | ||
672 | virt_to_real_irq_table[virq].dev_handle = devhandle; | |
673 | virt_to_real_irq_table[virq].dev_ino = devino; | |
674 | ||
675 | return virq; | |
4a907dec DM |
676 | } |
677 | ||
e18e2a00 DM |
678 | void ack_bad_irq(unsigned int virt_irq) |
679 | { | |
680 | struct ino_bucket *bucket = virt_irq_to_bucket(virt_irq); | |
681 | unsigned int ino = 0xdeadbeef; | |
ab66a50e | 682 | |
e18e2a00 DM |
683 | if (bucket) |
684 | ino = bucket - &ivector_table[0]; | |
6a76267f | 685 | |
e18e2a00 DM |
686 | printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n", |
687 | ino, virt_irq); | |
1da177e4 LT |
688 | } |
689 | ||
1da177e4 LT |
690 | void handler_irq(int irq, struct pt_regs *regs) |
691 | { | |
e18e2a00 | 692 | struct ino_bucket *bucket; |
6d24c8dc | 693 | struct pt_regs *old_regs; |
a650d383 | 694 | unsigned long pstate; |
1da177e4 | 695 | |
1da177e4 | 696 | clear_softint(1 << irq); |
1da177e4 | 697 | |
6d24c8dc | 698 | old_regs = set_irq_regs(regs); |
1da177e4 | 699 | irq_enter(); |
1da177e4 | 700 | |
a650d383 DM |
701 | /* Grab an atomic snapshot of the pending IVECs. */ |
702 | __asm__ __volatile__("rdpr %%pstate, %0\n\t" | |
703 | "wrpr %0, %3, %%pstate\n\t" | |
704 | "ldx [%2], %1\n\t" | |
705 | "stx %%g0, [%2]\n\t" | |
706 | "wrpr %0, 0x0, %%pstate\n\t" | |
707 | : "=&r" (pstate), "=&r" (bucket) | |
708 | : "r" (irq_work(smp_processor_id())), | |
709 | "i" (PSTATE_IE) | |
710 | : "memory"); | |
711 | ||
e18e2a00 DM |
712 | while (bucket) { |
713 | struct ino_bucket *next = __bucket(bucket->irq_chain); | |
1da177e4 | 714 | |
a650d383 | 715 | bucket->irq_chain = 0UL; |
6d24c8dc | 716 | __do_IRQ(bucket->virt_irq); |
fd0504c3 | 717 | |
e18e2a00 | 718 | bucket = next; |
1da177e4 | 719 | } |
e18e2a00 | 720 | |
1da177e4 | 721 | irq_exit(); |
6d24c8dc | 722 | set_irq_regs(old_regs); |
1da177e4 LT |
723 | } |
724 | ||
e0204409 DM |
725 | #ifdef CONFIG_HOTPLUG_CPU |
726 | void fixup_irqs(void) | |
727 | { | |
728 | unsigned int irq; | |
729 | ||
730 | for (irq = 0; irq < NR_IRQS; irq++) { | |
731 | unsigned long flags; | |
732 | ||
733 | spin_lock_irqsave(&irq_desc[irq].lock, flags); | |
734 | if (irq_desc[irq].action && | |
735 | !(irq_desc[irq].status & IRQ_PER_CPU)) { | |
736 | if (irq_desc[irq].chip->set_affinity) | |
737 | irq_desc[irq].chip->set_affinity(irq, | |
738 | irq_desc[irq].affinity); | |
739 | } | |
740 | spin_unlock_irqrestore(&irq_desc[irq].lock, flags); | |
741 | } | |
742 | } | |
743 | #endif | |
744 | ||
cdd5186f DM |
745 | struct sun5_timer { |
746 | u64 count0; | |
747 | u64 limit0; | |
748 | u64 count1; | |
749 | u64 limit1; | |
750 | }; | |
1da177e4 | 751 | |
cdd5186f | 752 | static struct sun5_timer *prom_timers; |
1da177e4 LT |
753 | static u64 prom_limit0, prom_limit1; |
754 | ||
755 | static void map_prom_timers(void) | |
756 | { | |
25c7581b | 757 | struct device_node *dp; |
6a23acf3 | 758 | const unsigned int *addr; |
1da177e4 LT |
759 | |
760 | /* PROM timer node hangs out in the top level of device siblings... */ | |
25c7581b DM |
761 | dp = of_find_node_by_path("/"); |
762 | dp = dp->child; | |
763 | while (dp) { | |
764 | if (!strcmp(dp->name, "counter-timer")) | |
765 | break; | |
766 | dp = dp->sibling; | |
767 | } | |
1da177e4 LT |
768 | |
769 | /* Assume if node is not present, PROM uses different tick mechanism | |
770 | * which we should not care about. | |
771 | */ | |
25c7581b | 772 | if (!dp) { |
1da177e4 LT |
773 | prom_timers = (struct sun5_timer *) 0; |
774 | return; | |
775 | } | |
776 | ||
777 | /* If PROM is really using this, it must be mapped by him. */ | |
25c7581b DM |
778 | addr = of_get_property(dp, "address", NULL); |
779 | if (!addr) { | |
1da177e4 LT |
780 | prom_printf("PROM does not have timer mapped, trying to continue.\n"); |
781 | prom_timers = (struct sun5_timer *) 0; | |
782 | return; | |
783 | } | |
784 | prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]); | |
785 | } | |
786 | ||
787 | static void kill_prom_timer(void) | |
788 | { | |
789 | if (!prom_timers) | |
790 | return; | |
791 | ||
792 | /* Save them away for later. */ | |
793 | prom_limit0 = prom_timers->limit0; | |
794 | prom_limit1 = prom_timers->limit1; | |
795 | ||
796 | /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14. | |
797 | * We turn both off here just to be paranoid. | |
798 | */ | |
799 | prom_timers->limit0 = 0; | |
800 | prom_timers->limit1 = 0; | |
801 | ||
802 | /* Wheee, eat the interrupt packet too... */ | |
803 | __asm__ __volatile__( | |
804 | " mov 0x40, %%g2\n" | |
805 | " ldxa [%%g0] %0, %%g1\n" | |
806 | " ldxa [%%g2] %1, %%g1\n" | |
807 | " stxa %%g0, [%%g0] %0\n" | |
808 | " membar #Sync\n" | |
809 | : /* no outputs */ | |
810 | : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R) | |
811 | : "g1", "g2"); | |
812 | } | |
813 | ||
1da177e4 LT |
814 | void init_irqwork_curcpu(void) |
815 | { | |
1da177e4 LT |
816 | int cpu = hard_smp_processor_id(); |
817 | ||
a650d383 | 818 | trap_block[cpu].irq_worklist = 0UL; |
1da177e4 LT |
819 | } |
820 | ||
5cbc3073 DM |
821 | /* Please be very careful with register_one_mondo() and |
822 | * sun4v_register_mondo_queues(). | |
823 | * | |
824 | * On SMP this gets invoked from the CPU trampoline before | |
825 | * the cpu has fully taken over the trap table from OBP, | |
826 | * and it's kernel stack + %g6 thread register state is | |
827 | * not fully cooked yet. | |
828 | * | |
829 | * Therefore you cannot make any OBP calls, not even prom_printf, | |
830 | * from these two routines. | |
831 | */ | |
832 | static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask) | |
ac29c11d | 833 | { |
5cbc3073 | 834 | unsigned long num_entries = (qmask + 1) / 64; |
94f8762d DM |
835 | unsigned long status; |
836 | ||
837 | status = sun4v_cpu_qconf(type, paddr, num_entries); | |
838 | if (status != HV_EOK) { | |
839 | prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, " | |
840 | "err %lu\n", type, paddr, num_entries, status); | |
ac29c11d DM |
841 | prom_halt(); |
842 | } | |
843 | } | |
844 | ||
b434e719 | 845 | void __cpuinit sun4v_register_mondo_queues(int this_cpu) |
5b0c0572 | 846 | { |
b5a37e96 DM |
847 | struct trap_per_cpu *tb = &trap_block[this_cpu]; |
848 | ||
5cbc3073 DM |
849 | register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO, |
850 | tb->cpu_mondo_qmask); | |
851 | register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO, | |
852 | tb->dev_mondo_qmask); | |
853 | register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR, | |
854 | tb->resum_qmask); | |
855 | register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR, | |
856 | tb->nonresum_qmask); | |
b5a37e96 DM |
857 | } |
858 | ||
b434e719 | 859 | static void __init alloc_one_mondo(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 860 | { |
5cbc3073 | 861 | unsigned long size = PAGE_ALIGN(qmask + 1); |
b434e719 | 862 | void *p = __alloc_bootmem_low(size, size, 0); |
5cbc3073 | 863 | if (!p) { |
b5a37e96 DM |
864 | prom_printf("SUN4V: Error, cannot allocate mondo queue.\n"); |
865 | prom_halt(); | |
866 | } | |
867 | ||
5cbc3073 | 868 | *pa_ptr = __pa(p); |
b5a37e96 DM |
869 | } |
870 | ||
b434e719 | 871 | static void __init alloc_one_kbuf(unsigned long *pa_ptr, unsigned long qmask) |
b5a37e96 | 872 | { |
5cbc3073 | 873 | unsigned long size = PAGE_ALIGN(qmask + 1); |
b434e719 | 874 | void *p = __alloc_bootmem_low(size, size, 0); |
5b0c0572 | 875 | |
5cbc3073 | 876 | if (!p) { |
5b0c0572 DM |
877 | prom_printf("SUN4V: Error, cannot allocate kbuf page.\n"); |
878 | prom_halt(); | |
879 | } | |
880 | ||
5cbc3073 | 881 | *pa_ptr = __pa(p); |
5b0c0572 DM |
882 | } |
883 | ||
b434e719 | 884 | static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb) |
1d2f1f90 DM |
885 | { |
886 | #ifdef CONFIG_SMP | |
b5a37e96 | 887 | void *page; |
1d2f1f90 DM |
888 | |
889 | BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64)); | |
890 | ||
b434e719 | 891 | page = alloc_bootmem_low_pages(PAGE_SIZE); |
1d2f1f90 DM |
892 | if (!page) { |
893 | prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n"); | |
894 | prom_halt(); | |
895 | } | |
896 | ||
897 | tb->cpu_mondo_block_pa = __pa(page); | |
898 | tb->cpu_list_pa = __pa(page + 64); | |
899 | #endif | |
900 | } | |
901 | ||
b434e719 DM |
902 | /* Allocate mondo and error queues for all possible cpus. */ |
903 | static void __init sun4v_init_mondo_queues(void) | |
ac29c11d | 904 | { |
b434e719 | 905 | int cpu; |
ac29c11d | 906 | |
b434e719 DM |
907 | for_each_possible_cpu(cpu) { |
908 | struct trap_per_cpu *tb = &trap_block[cpu]; | |
1d2f1f90 | 909 | |
b434e719 DM |
910 | alloc_one_mondo(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask); |
911 | alloc_one_mondo(&tb->dev_mondo_pa, tb->dev_mondo_qmask); | |
912 | alloc_one_mondo(&tb->resum_mondo_pa, tb->resum_qmask); | |
913 | alloc_one_kbuf(&tb->resum_kernel_buf_pa, tb->resum_qmask); | |
914 | alloc_one_mondo(&tb->nonresum_mondo_pa, tb->nonresum_qmask); | |
915 | alloc_one_kbuf(&tb->nonresum_kernel_buf_pa, | |
916 | tb->nonresum_qmask); | |
1d2f1f90 | 917 | |
b434e719 | 918 | init_cpu_send_mondo_info(tb); |
72aff53f | 919 | } |
b434e719 DM |
920 | |
921 | /* Load up the boot cpu's entries. */ | |
922 | sun4v_register_mondo_queues(hard_smp_processor_id()); | |
ac29c11d DM |
923 | } |
924 | ||
e18e2a00 DM |
925 | static struct irqaction timer_irq_action = { |
926 | .name = "timer", | |
927 | }; | |
928 | ||
1da177e4 LT |
929 | /* Only invoked on boot processor. */ |
930 | void __init init_IRQ(void) | |
931 | { | |
932 | map_prom_timers(); | |
933 | kill_prom_timer(); | |
934 | memset(&ivector_table[0], 0, sizeof(ivector_table)); | |
935 | ||
ac29c11d | 936 | if (tlb_type == hypervisor) |
b434e719 | 937 | sun4v_init_mondo_queues(); |
ac29c11d | 938 | |
1da177e4 LT |
939 | /* We need to clear any IRQ's pending in the soft interrupt |
940 | * registers, a spurious one could be left around from the | |
941 | * PROM timer which we just disabled. | |
942 | */ | |
943 | clear_softint(get_softint()); | |
944 | ||
945 | /* Now that ivector table is initialized, it is safe | |
946 | * to receive IRQ vector traps. We will normally take | |
947 | * one or two right now, in case some device PROM used | |
948 | * to boot us wants to speak to us. We just ignore them. | |
949 | */ | |
950 | __asm__ __volatile__("rdpr %%pstate, %%g1\n\t" | |
951 | "or %%g1, %0, %%g1\n\t" | |
952 | "wrpr %%g1, 0x0, %%pstate" | |
953 | : /* No outputs */ | |
954 | : "i" (PSTATE_IE) | |
955 | : "g1"); | |
1da177e4 | 956 | |
e18e2a00 | 957 | irq_desc[0].action = &timer_irq_action; |
1da177e4 | 958 | } |