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a2fb23af | 1 | /* pci.c: UltraSparc PCI controller support. |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com) | |
4 | * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be) | |
5 | * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz) | |
a2fb23af DM |
6 | * |
7 | * OF tree based PCI bus probing taken from the PowerPC port | |
8 | * with minor modifications, see there for credits. | |
1da177e4 LT |
9 | */ |
10 | ||
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/kernel.h> | |
13 | #include <linux/string.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/capability.h> | |
16 | #include <linux/errno.h> | |
35a17eb6 DM |
17 | #include <linux/msi.h> |
18 | #include <linux/irq.h> | |
1da177e4 LT |
19 | #include <linux/init.h> |
20 | ||
21 | #include <asm/uaccess.h> | |
22 | #include <asm/pbm.h> | |
23 | #include <asm/pgtable.h> | |
24 | #include <asm/irq.h> | |
25 | #include <asm/ebus.h> | |
26 | #include <asm/isa.h> | |
e87dc350 | 27 | #include <asm/prom.h> |
01f94c4a | 28 | #include <asm/apb.h> |
1da177e4 | 29 | |
1e8a8cc5 DM |
30 | #include "pci_impl.h" |
31 | ||
1da177e4 LT |
32 | unsigned long pci_memspace_mask = 0xffffffffUL; |
33 | ||
34 | #ifndef CONFIG_PCI | |
35 | /* A "nop" PCI implementation. */ | |
36 | asmlinkage int sys_pciconfig_read(unsigned long bus, unsigned long dfn, | |
37 | unsigned long off, unsigned long len, | |
38 | unsigned char *buf) | |
39 | { | |
40 | return 0; | |
41 | } | |
42 | asmlinkage int sys_pciconfig_write(unsigned long bus, unsigned long dfn, | |
43 | unsigned long off, unsigned long len, | |
44 | unsigned char *buf) | |
45 | { | |
46 | return 0; | |
47 | } | |
48 | #else | |
49 | ||
50 | /* List of all PCI controllers found in the system. */ | |
34768bc8 | 51 | struct pci_pbm_info *pci_pbm_root = NULL; |
1da177e4 LT |
52 | |
53 | /* Each PCI controller found gets a unique index. */ | |
54 | int pci_num_controllers = 0; | |
55 | ||
1da177e4 LT |
56 | volatile int pci_poke_in_progress; |
57 | volatile int pci_poke_cpu = -1; | |
58 | volatile int pci_poke_faulted; | |
59 | ||
60 | static DEFINE_SPINLOCK(pci_poke_lock); | |
61 | ||
62 | void pci_config_read8(u8 *addr, u8 *ret) | |
63 | { | |
64 | unsigned long flags; | |
65 | u8 byte; | |
66 | ||
67 | spin_lock_irqsave(&pci_poke_lock, flags); | |
68 | pci_poke_cpu = smp_processor_id(); | |
69 | pci_poke_in_progress = 1; | |
70 | pci_poke_faulted = 0; | |
71 | __asm__ __volatile__("membar #Sync\n\t" | |
72 | "lduba [%1] %2, %0\n\t" | |
73 | "membar #Sync" | |
74 | : "=r" (byte) | |
75 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
76 | : "memory"); | |
77 | pci_poke_in_progress = 0; | |
78 | pci_poke_cpu = -1; | |
79 | if (!pci_poke_faulted) | |
80 | *ret = byte; | |
81 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
82 | } | |
83 | ||
84 | void pci_config_read16(u16 *addr, u16 *ret) | |
85 | { | |
86 | unsigned long flags; | |
87 | u16 word; | |
88 | ||
89 | spin_lock_irqsave(&pci_poke_lock, flags); | |
90 | pci_poke_cpu = smp_processor_id(); | |
91 | pci_poke_in_progress = 1; | |
92 | pci_poke_faulted = 0; | |
93 | __asm__ __volatile__("membar #Sync\n\t" | |
94 | "lduha [%1] %2, %0\n\t" | |
95 | "membar #Sync" | |
96 | : "=r" (word) | |
97 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
98 | : "memory"); | |
99 | pci_poke_in_progress = 0; | |
100 | pci_poke_cpu = -1; | |
101 | if (!pci_poke_faulted) | |
102 | *ret = word; | |
103 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
104 | } | |
105 | ||
106 | void pci_config_read32(u32 *addr, u32 *ret) | |
107 | { | |
108 | unsigned long flags; | |
109 | u32 dword; | |
110 | ||
111 | spin_lock_irqsave(&pci_poke_lock, flags); | |
112 | pci_poke_cpu = smp_processor_id(); | |
113 | pci_poke_in_progress = 1; | |
114 | pci_poke_faulted = 0; | |
115 | __asm__ __volatile__("membar #Sync\n\t" | |
116 | "lduwa [%1] %2, %0\n\t" | |
117 | "membar #Sync" | |
118 | : "=r" (dword) | |
119 | : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
120 | : "memory"); | |
121 | pci_poke_in_progress = 0; | |
122 | pci_poke_cpu = -1; | |
123 | if (!pci_poke_faulted) | |
124 | *ret = dword; | |
125 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
126 | } | |
127 | ||
128 | void pci_config_write8(u8 *addr, u8 val) | |
129 | { | |
130 | unsigned long flags; | |
131 | ||
132 | spin_lock_irqsave(&pci_poke_lock, flags); | |
133 | pci_poke_cpu = smp_processor_id(); | |
134 | pci_poke_in_progress = 1; | |
135 | pci_poke_faulted = 0; | |
136 | __asm__ __volatile__("membar #Sync\n\t" | |
137 | "stba %0, [%1] %2\n\t" | |
138 | "membar #Sync" | |
139 | : /* no outputs */ | |
140 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
141 | : "memory"); | |
142 | pci_poke_in_progress = 0; | |
143 | pci_poke_cpu = -1; | |
144 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
145 | } | |
146 | ||
147 | void pci_config_write16(u16 *addr, u16 val) | |
148 | { | |
149 | unsigned long flags; | |
150 | ||
151 | spin_lock_irqsave(&pci_poke_lock, flags); | |
152 | pci_poke_cpu = smp_processor_id(); | |
153 | pci_poke_in_progress = 1; | |
154 | pci_poke_faulted = 0; | |
155 | __asm__ __volatile__("membar #Sync\n\t" | |
156 | "stha %0, [%1] %2\n\t" | |
157 | "membar #Sync" | |
158 | : /* no outputs */ | |
159 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
160 | : "memory"); | |
161 | pci_poke_in_progress = 0; | |
162 | pci_poke_cpu = -1; | |
163 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
164 | } | |
165 | ||
166 | void pci_config_write32(u32 *addr, u32 val) | |
167 | { | |
168 | unsigned long flags; | |
169 | ||
170 | spin_lock_irqsave(&pci_poke_lock, flags); | |
171 | pci_poke_cpu = smp_processor_id(); | |
172 | pci_poke_in_progress = 1; | |
173 | pci_poke_faulted = 0; | |
174 | __asm__ __volatile__("membar #Sync\n\t" | |
175 | "stwa %0, [%1] %2\n\t" | |
176 | "membar #Sync" | |
177 | : /* no outputs */ | |
178 | : "r" (val), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E_L) | |
179 | : "memory"); | |
180 | pci_poke_in_progress = 0; | |
181 | pci_poke_cpu = -1; | |
182 | spin_unlock_irqrestore(&pci_poke_lock, flags); | |
183 | } | |
184 | ||
185 | /* Probe for all PCI controllers in the system. */ | |
e87dc350 DM |
186 | extern void sabre_init(struct device_node *, const char *); |
187 | extern void psycho_init(struct device_node *, const char *); | |
188 | extern void schizo_init(struct device_node *, const char *); | |
189 | extern void schizo_plus_init(struct device_node *, const char *); | |
190 | extern void tomatillo_init(struct device_node *, const char *); | |
191 | extern void sun4v_pci_init(struct device_node *, const char *); | |
861fe906 | 192 | extern void fire_pci_init(struct device_node *, const char *); |
1da177e4 LT |
193 | |
194 | static struct { | |
195 | char *model_name; | |
e87dc350 | 196 | void (*init)(struct device_node *, const char *); |
1da177e4 LT |
197 | } pci_controller_table[] __initdata = { |
198 | { "SUNW,sabre", sabre_init }, | |
199 | { "pci108e,a000", sabre_init }, | |
200 | { "pci108e,a001", sabre_init }, | |
201 | { "SUNW,psycho", psycho_init }, | |
202 | { "pci108e,8000", psycho_init }, | |
203 | { "SUNW,schizo", schizo_init }, | |
204 | { "pci108e,8001", schizo_init }, | |
205 | { "SUNW,schizo+", schizo_plus_init }, | |
206 | { "pci108e,8002", schizo_plus_init }, | |
207 | { "SUNW,tomatillo", tomatillo_init }, | |
208 | { "pci108e,a801", tomatillo_init }, | |
8f6a93a1 | 209 | { "SUNW,sun4v-pci", sun4v_pci_init }, |
861fe906 | 210 | { "pciex108e,80f0", fire_pci_init }, |
1da177e4 LT |
211 | }; |
212 | #define PCI_NUM_CONTROLLER_TYPES (sizeof(pci_controller_table) / \ | |
213 | sizeof(pci_controller_table[0])) | |
214 | ||
e87dc350 | 215 | static int __init pci_controller_init(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
216 | { |
217 | int i; | |
218 | ||
219 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
220 | if (!strncmp(model_name, | |
221 | pci_controller_table[i].model_name, | |
222 | namelen)) { | |
e87dc350 | 223 | pci_controller_table[i].init(dp, model_name); |
1da177e4 LT |
224 | return 1; |
225 | } | |
226 | } | |
1da177e4 LT |
227 | |
228 | return 0; | |
229 | } | |
230 | ||
e87dc350 | 231 | static int __init pci_is_controller(const char *model_name, int namelen, struct device_node *dp) |
1da177e4 LT |
232 | { |
233 | int i; | |
234 | ||
235 | for (i = 0; i < PCI_NUM_CONTROLLER_TYPES; i++) { | |
236 | if (!strncmp(model_name, | |
237 | pci_controller_table[i].model_name, | |
238 | namelen)) { | |
239 | return 1; | |
240 | } | |
241 | } | |
242 | return 0; | |
243 | } | |
244 | ||
e87dc350 | 245 | static int __init pci_controller_scan(int (*handler)(const char *, int, struct device_node *)) |
1da177e4 | 246 | { |
e87dc350 | 247 | struct device_node *dp; |
1da177e4 LT |
248 | int count = 0; |
249 | ||
e87dc350 DM |
250 | for_each_node_by_name(dp, "pci") { |
251 | struct property *prop; | |
1da177e4 LT |
252 | int len; |
253 | ||
e87dc350 DM |
254 | prop = of_find_property(dp, "model", &len); |
255 | if (!prop) | |
256 | prop = of_find_property(dp, "compatible", &len); | |
257 | ||
258 | if (prop) { | |
259 | const char *model = prop->value; | |
1da177e4 LT |
260 | int item_len = 0; |
261 | ||
262 | /* Our value may be a multi-valued string in the | |
263 | * case of some compatible properties. For sanity, | |
e87dc350 DM |
264 | * only try the first one. |
265 | */ | |
266 | while (model[item_len] && len) { | |
1da177e4 LT |
267 | len--; |
268 | item_len++; | |
269 | } | |
270 | ||
e87dc350 | 271 | if (handler(model, item_len, dp)) |
1da177e4 LT |
272 | count++; |
273 | } | |
1da177e4 LT |
274 | } |
275 | ||
276 | return count; | |
277 | } | |
278 | ||
279 | ||
280 | /* Is there some PCI controller in the system? */ | |
281 | int __init pcic_present(void) | |
282 | { | |
283 | return pci_controller_scan(pci_is_controller); | |
284 | } | |
285 | ||
c6e87566 | 286 | const struct pci_iommu_ops *pci_iommu_ops; |
8f6a93a1 DM |
287 | EXPORT_SYMBOL(pci_iommu_ops); |
288 | ||
c6e87566 | 289 | extern const struct pci_iommu_ops pci_sun4u_iommu_ops, |
8f6a93a1 DM |
290 | pci_sun4v_iommu_ops; |
291 | ||
1da177e4 LT |
292 | /* Find each controller in the system, attach and initialize |
293 | * software state structure for each and link into the | |
34768bc8 | 294 | * pci_pbm_root. Setup the controller enough such |
1da177e4 LT |
295 | * that bus scanning can be done. |
296 | */ | |
297 | static void __init pci_controller_probe(void) | |
298 | { | |
8f6a93a1 DM |
299 | if (tlb_type == hypervisor) |
300 | pci_iommu_ops = &pci_sun4v_iommu_ops; | |
301 | else | |
302 | pci_iommu_ops = &pci_sun4u_iommu_ops; | |
303 | ||
1da177e4 LT |
304 | printk("PCI: Probing for controllers.\n"); |
305 | ||
306 | pci_controller_scan(pci_controller_init); | |
307 | } | |
308 | ||
a2fb23af DM |
309 | static unsigned long pci_parse_of_flags(u32 addr0) |
310 | { | |
311 | unsigned long flags = 0; | |
312 | ||
313 | if (addr0 & 0x02000000) { | |
314 | flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY; | |
315 | flags |= (addr0 >> 22) & PCI_BASE_ADDRESS_MEM_TYPE_64; | |
316 | flags |= (addr0 >> 28) & PCI_BASE_ADDRESS_MEM_TYPE_1M; | |
317 | if (addr0 & 0x40000000) | |
318 | flags |= IORESOURCE_PREFETCH | |
319 | | PCI_BASE_ADDRESS_MEM_PREFETCH; | |
320 | } else if (addr0 & 0x01000000) | |
321 | flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO; | |
322 | return flags; | |
323 | } | |
324 | ||
325 | /* The of_device layer has translated all of the assigned-address properties | |
326 | * into physical address resources, we only have to figure out the register | |
327 | * mapping. | |
328 | */ | |
329 | static void pci_parse_of_addrs(struct of_device *op, | |
330 | struct device_node *node, | |
331 | struct pci_dev *dev) | |
332 | { | |
333 | struct resource *op_res; | |
334 | const u32 *addrs; | |
335 | int proplen; | |
336 | ||
337 | addrs = of_get_property(node, "assigned-addresses", &proplen); | |
338 | if (!addrs) | |
339 | return; | |
340 | printk(" parse addresses (%d bytes) @ %p\n", proplen, addrs); | |
341 | op_res = &op->resource[0]; | |
342 | for (; proplen >= 20; proplen -= 20, addrs += 5, op_res++) { | |
343 | struct resource *res; | |
344 | unsigned long flags; | |
345 | int i; | |
346 | ||
347 | flags = pci_parse_of_flags(addrs[0]); | |
348 | if (!flags) | |
349 | continue; | |
350 | i = addrs[0] & 0xff; | |
351 | printk(" start: %lx, end: %lx, i: %x\n", | |
352 | op_res->start, op_res->end, i); | |
353 | ||
354 | if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) { | |
355 | res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2]; | |
356 | } else if (i == dev->rom_base_reg) { | |
357 | res = &dev->resource[PCI_ROM_RESOURCE]; | |
358 | flags |= IORESOURCE_READONLY | IORESOURCE_CACHEABLE; | |
359 | } else { | |
360 | printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i); | |
361 | continue; | |
362 | } | |
363 | res->start = op_res->start; | |
364 | res->end = op_res->end; | |
365 | res->flags = flags; | |
366 | res->name = pci_name(dev); | |
367 | } | |
368 | } | |
369 | ||
370 | struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm, | |
371 | struct device_node *node, | |
97b3cf05 DM |
372 | struct pci_bus *bus, int devfn, |
373 | int host_controller) | |
a2fb23af DM |
374 | { |
375 | struct dev_archdata *sd; | |
376 | struct pci_dev *dev; | |
377 | const char *type; | |
01f94c4a | 378 | u32 class; |
a2fb23af DM |
379 | |
380 | dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); | |
381 | if (!dev) | |
382 | return NULL; | |
383 | ||
384 | sd = &dev->dev.archdata; | |
385 | sd->iommu = pbm->iommu; | |
386 | sd->stc = &pbm->stc; | |
387 | sd->host_controller = pbm; | |
388 | sd->prom_node = node; | |
389 | sd->op = of_find_device_by_node(node); | |
390 | sd->msi_num = 0xffffffff; | |
391 | ||
392 | type = of_get_property(node, "device_type", NULL); | |
393 | if (type == NULL) | |
394 | type = ""; | |
395 | ||
28f57e77 DM |
396 | printk(" create device, devfn: %x, type: %s hostcontroller(%d)\n", |
397 | devfn, type, host_controller); | |
a2fb23af DM |
398 | |
399 | dev->bus = bus; | |
400 | dev->sysdata = node; | |
401 | dev->dev.parent = bus->bridge; | |
402 | dev->dev.bus = &pci_bus_type; | |
403 | dev->devfn = devfn; | |
404 | dev->multifunction = 0; /* maybe a lie? */ | |
405 | ||
97b3cf05 DM |
406 | if (host_controller) { |
407 | dev->vendor = 0x108e; | |
408 | dev->device = 0x8000; | |
409 | dev->subsystem_vendor = 0x0000; | |
410 | dev->subsystem_device = 0x0000; | |
411 | dev->cfg_size = 256; | |
28f57e77 DM |
412 | dev->class = PCI_CLASS_BRIDGE_HOST << 8; |
413 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
414 | 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 DM |
415 | } else { |
416 | dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff); | |
417 | dev->device = of_getintprop_default(node, "device-id", 0xffff); | |
418 | dev->subsystem_vendor = | |
419 | of_getintprop_default(node, "subsystem-vendor-id", 0); | |
420 | dev->subsystem_device = | |
421 | of_getintprop_default(node, "subsystem-id", 0); | |
422 | ||
423 | dev->cfg_size = pci_cfg_space_size(dev); | |
01f94c4a | 424 | |
97b3cf05 DM |
425 | /* We can't actually use the firmware value, we have |
426 | * to read what is in the register right now. One | |
427 | * reason is that in the case of IDE interfaces the | |
428 | * firmware can sample the value before the the IDE | |
429 | * interface is programmed into native mode. | |
430 | */ | |
431 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); | |
432 | dev->class = class >> 8; | |
28f57e77 DM |
433 | |
434 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus), | |
435 | dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn)); | |
97b3cf05 | 436 | } |
28f57e77 DM |
437 | printk(" class: 0x%x device name: %s\n", |
438 | dev->class, pci_name(dev)); | |
a2fb23af | 439 | |
861fe906 DM |
440 | /* I have seen IDE devices which will not respond to |
441 | * the bmdma simplex check reads if bus mastering is | |
442 | * disabled. | |
443 | */ | |
444 | if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) | |
445 | pci_set_master(dev); | |
446 | ||
a2fb23af DM |
447 | dev->current_state = 4; /* unknown power state */ |
448 | dev->error_state = pci_channel_io_normal; | |
449 | ||
97b3cf05 | 450 | if (host_controller) { |
a2fb23af DM |
451 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; |
452 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
97b3cf05 | 453 | dev->irq = PCI_IRQ_NONE; |
a2fb23af | 454 | } else { |
97b3cf05 DM |
455 | if (!strcmp(type, "pci") || !strcmp(type, "pciex")) { |
456 | /* a PCI-PCI bridge */ | |
457 | dev->hdr_type = PCI_HEADER_TYPE_BRIDGE; | |
458 | dev->rom_base_reg = PCI_ROM_ADDRESS1; | |
459 | } else if (!strcmp(type, "cardbus")) { | |
460 | dev->hdr_type = PCI_HEADER_TYPE_CARDBUS; | |
461 | } else { | |
462 | dev->hdr_type = PCI_HEADER_TYPE_NORMAL; | |
463 | dev->rom_base_reg = PCI_ROM_ADDRESS; | |
a2fb23af | 464 | |
97b3cf05 DM |
465 | dev->irq = sd->op->irqs[0]; |
466 | if (dev->irq == 0xffffffff) | |
467 | dev->irq = PCI_IRQ_NONE; | |
468 | } | |
a2fb23af | 469 | } |
a2fb23af DM |
470 | pci_parse_of_addrs(sd->op, node, dev); |
471 | ||
472 | printk(" adding to system ...\n"); | |
473 | ||
474 | pci_device_add(dev, bus); | |
475 | ||
476 | return dev; | |
477 | } | |
478 | ||
a6009dda | 479 | static void __devinit apb_calc_first_last(u8 map, u32 *first_p, u32 *last_p) |
01f94c4a DM |
480 | { |
481 | u32 idx, first, last; | |
482 | ||
483 | first = 8; | |
484 | last = 0; | |
485 | for (idx = 0; idx < 8; idx++) { | |
486 | if ((map & (1 << idx)) != 0) { | |
487 | if (first > idx) | |
488 | first = idx; | |
489 | if (last < idx) | |
490 | last = idx; | |
491 | } | |
492 | } | |
493 | ||
494 | *first_p = first; | |
495 | *last_p = last; | |
496 | } | |
497 | ||
0bae5f81 DM |
498 | static void __init pci_resource_adjust(struct resource *res, |
499 | struct resource *root) | |
500 | { | |
501 | res->start += root->start; | |
502 | res->end += root->start; | |
503 | } | |
504 | ||
01f94c4a DM |
505 | /* Cook up fake bus resources for SUNW,simba PCI bridges which lack |
506 | * a proper 'ranges' property. | |
507 | */ | |
a6009dda DM |
508 | static void __devinit apb_fake_ranges(struct pci_dev *dev, |
509 | struct pci_bus *bus, | |
510 | struct pci_pbm_info *pbm) | |
01f94c4a DM |
511 | { |
512 | struct resource *res; | |
513 | u32 first, last; | |
514 | u8 map; | |
515 | ||
516 | pci_read_config_byte(dev, APB_IO_ADDRESS_MAP, &map); | |
517 | apb_calc_first_last(map, &first, &last); | |
518 | res = bus->resource[0]; | |
519 | res->start = (first << 21); | |
520 | res->end = (last << 21) + ((1 << 21) - 1); | |
521 | res->flags = IORESOURCE_IO; | |
0bae5f81 | 522 | pci_resource_adjust(res, &pbm->io_space); |
01f94c4a DM |
523 | |
524 | pci_read_config_byte(dev, APB_MEM_ADDRESS_MAP, &map); | |
525 | apb_calc_first_last(map, &first, &last); | |
526 | res = bus->resource[1]; | |
527 | res->start = (first << 21); | |
528 | res->end = (last << 21) + ((1 << 21) - 1); | |
529 | res->flags = IORESOURCE_MEM; | |
0bae5f81 | 530 | pci_resource_adjust(res, &pbm->mem_space); |
01f94c4a DM |
531 | } |
532 | ||
a6009dda DM |
533 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
534 | struct device_node *node, | |
535 | struct pci_bus *bus); | |
a2fb23af DM |
536 | |
537 | #define GET_64BIT(prop, i) ((((u64) (prop)[(i)]) << 32) | (prop)[(i)+1]) | |
538 | ||
a6009dda DM |
539 | static void __devinit of_scan_pci_bridge(struct pci_pbm_info *pbm, |
540 | struct device_node *node, | |
541 | struct pci_dev *dev) | |
a2fb23af DM |
542 | { |
543 | struct pci_bus *bus; | |
544 | const u32 *busrange, *ranges; | |
01f94c4a | 545 | int len, i, simba; |
a2fb23af DM |
546 | struct resource *res; |
547 | unsigned int flags; | |
548 | u64 size; | |
549 | ||
550 | printk("of_scan_pci_bridge(%s)\n", node->full_name); | |
551 | ||
552 | /* parse bus-range property */ | |
553 | busrange = of_get_property(node, "bus-range", &len); | |
554 | if (busrange == NULL || len != 8) { | |
555 | printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %s\n", | |
556 | node->full_name); | |
557 | return; | |
558 | } | |
559 | ranges = of_get_property(node, "ranges", &len); | |
01f94c4a | 560 | simba = 0; |
a2fb23af | 561 | if (ranges == NULL) { |
a165b420 | 562 | const char *model = of_get_property(node, "model", NULL); |
01f94c4a DM |
563 | if (model && !strcmp(model, "SUNW,simba")) { |
564 | simba = 1; | |
565 | } else { | |
566 | printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %s\n", | |
567 | node->full_name); | |
568 | return; | |
569 | } | |
a2fb23af DM |
570 | } |
571 | ||
572 | bus = pci_add_new_bus(dev->bus, dev, busrange[0]); | |
573 | if (!bus) { | |
574 | printk(KERN_ERR "Failed to create pci bus for %s\n", | |
575 | node->full_name); | |
576 | return; | |
577 | } | |
578 | ||
579 | bus->primary = dev->bus->number; | |
580 | bus->subordinate = busrange[1]; | |
581 | bus->bridge_ctl = 0; | |
582 | ||
01f94c4a | 583 | /* parse ranges property, or cook one up by hand for Simba */ |
a2fb23af DM |
584 | /* PCI #address-cells == 3 and #size-cells == 2 always */ |
585 | res = &dev->resource[PCI_BRIDGE_RESOURCES]; | |
586 | for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) { | |
587 | res->flags = 0; | |
588 | bus->resource[i] = res; | |
589 | ++res; | |
590 | } | |
01f94c4a DM |
591 | if (simba) { |
592 | apb_fake_ranges(dev, bus, pbm); | |
593 | goto simba_cont; | |
594 | } | |
a2fb23af DM |
595 | i = 1; |
596 | for (; len >= 32; len -= 32, ranges += 8) { | |
597 | struct resource *root; | |
598 | ||
599 | flags = pci_parse_of_flags(ranges[0]); | |
600 | size = GET_64BIT(ranges, 6); | |
601 | if (flags == 0 || size == 0) | |
602 | continue; | |
603 | if (flags & IORESOURCE_IO) { | |
604 | res = bus->resource[0]; | |
605 | if (res->flags) { | |
606 | printk(KERN_ERR "PCI: ignoring extra I/O range" | |
607 | " for bridge %s\n", node->full_name); | |
608 | continue; | |
609 | } | |
610 | root = &pbm->io_space; | |
611 | } else { | |
612 | if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) { | |
613 | printk(KERN_ERR "PCI: too many memory ranges" | |
614 | " for bridge %s\n", node->full_name); | |
615 | continue; | |
616 | } | |
617 | res = bus->resource[i]; | |
618 | ++i; | |
619 | root = &pbm->mem_space; | |
620 | } | |
621 | ||
622 | res->start = GET_64BIT(ranges, 1); | |
623 | res->end = res->start + size - 1; | |
624 | res->flags = flags; | |
625 | ||
626 | /* Another way to implement this would be to add an of_device | |
627 | * layer routine that can calculate a resource for a given | |
628 | * range property value in a PCI device. | |
629 | */ | |
0bae5f81 | 630 | pci_resource_adjust(res, root); |
a2fb23af | 631 | } |
01f94c4a | 632 | simba_cont: |
a2fb23af DM |
633 | sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus), |
634 | bus->number); | |
635 | printk(" bus name: %s\n", bus->name); | |
636 | ||
637 | pci_of_scan_bus(pbm, node, bus); | |
638 | } | |
639 | ||
a6009dda DM |
640 | static void __devinit pci_of_scan_bus(struct pci_pbm_info *pbm, |
641 | struct device_node *node, | |
642 | struct pci_bus *bus) | |
a2fb23af DM |
643 | { |
644 | struct device_node *child; | |
645 | const u32 *reg; | |
646 | int reglen, devfn; | |
647 | struct pci_dev *dev; | |
648 | ||
649 | printk("PCI: scan_bus[%s] bus no %d\n", | |
650 | node->full_name, bus->number); | |
651 | ||
652 | child = NULL; | |
653 | while ((child = of_get_next_child(node, child)) != NULL) { | |
654 | printk(" * %s\n", child->full_name); | |
655 | reg = of_get_property(child, "reg", ®len); | |
656 | if (reg == NULL || reglen < 20) | |
657 | continue; | |
658 | devfn = (reg[0] >> 8) & 0xff; | |
659 | ||
660 | /* create a new pci_dev for this device */ | |
97b3cf05 | 661 | dev = of_create_pci_dev(pbm, child, bus, devfn, 0); |
a2fb23af DM |
662 | if (!dev) |
663 | continue; | |
664 | printk("PCI: dev header type: %x\n", dev->hdr_type); | |
665 | ||
666 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || | |
667 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) | |
668 | of_scan_pci_bridge(pbm, child, dev); | |
669 | } | |
670 | } | |
671 | ||
672 | static ssize_t | |
673 | show_pciobppath_attr(struct device * dev, struct device_attribute * attr, char * buf) | |
674 | { | |
675 | struct pci_dev *pdev; | |
676 | struct device_node *dp; | |
677 | ||
678 | pdev = to_pci_dev(dev); | |
679 | dp = pdev->dev.archdata.prom_node; | |
680 | ||
681 | return snprintf (buf, PAGE_SIZE, "%s\n", dp->full_name); | |
682 | } | |
683 | ||
684 | static DEVICE_ATTR(obppath, S_IRUSR | S_IRGRP | S_IROTH, show_pciobppath_attr, NULL); | |
685 | ||
686 | static void __devinit pci_bus_register_of_sysfs(struct pci_bus *bus) | |
687 | { | |
688 | struct pci_dev *dev; | |
a378fd0e | 689 | struct pci_bus *child_bus; |
a2fb23af DM |
690 | int err; |
691 | ||
692 | list_for_each_entry(dev, &bus->devices, bus_list) { | |
693 | /* we don't really care if we can create this file or | |
694 | * not, but we need to assign the result of the call | |
695 | * or the world will fall under alien invasion and | |
696 | * everybody will be frozen on a spaceship ready to be | |
697 | * eaten on alpha centauri by some green and jelly | |
698 | * humanoid. | |
699 | */ | |
700 | err = sysfs_create_file(&dev->dev.kobj, &dev_attr_obppath.attr); | |
701 | } | |
a378fd0e DM |
702 | list_for_each_entry(child_bus, &bus->children, node) |
703 | pci_bus_register_of_sysfs(child_bus); | |
a2fb23af DM |
704 | } |
705 | ||
97b3cf05 DM |
706 | int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev, |
707 | unsigned int devfn, | |
708 | int where, int size, | |
709 | u32 *value) | |
710 | { | |
711 | static u8 fake_pci_config[] = { | |
712 | 0x8e, 0x10, /* Vendor: 0x108e (Sun) */ | |
713 | 0x00, 0x80, /* Device: 0x8000 (PBM) */ | |
714 | 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */ | |
715 | 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */ | |
716 | 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */ | |
717 | 0x00, /* Cacheline: 0x00 */ | |
718 | 0x40, /* Latency: 0x40 */ | |
719 | 0x00, /* Header-Type: 0x00 normal */ | |
720 | }; | |
721 | ||
722 | *value = 0; | |
723 | if (where >= 0 && where < sizeof(fake_pci_config) && | |
724 | (where + size) >= 0 && | |
725 | (where + size) < sizeof(fake_pci_config) && | |
726 | size <= sizeof(u32)) { | |
727 | while (size--) { | |
728 | *value <<= 8; | |
729 | *value |= fake_pci_config[where + size]; | |
730 | } | |
731 | } | |
732 | ||
733 | return PCIBIOS_SUCCESSFUL; | |
734 | } | |
735 | ||
736 | int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev, | |
737 | unsigned int devfn, | |
738 | int where, int size, | |
739 | u32 value) | |
740 | { | |
741 | return PCIBIOS_SUCCESSFUL; | |
742 | } | |
743 | ||
a6009dda | 744 | struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm) |
a2fb23af | 745 | { |
a2fb23af | 746 | struct device_node *node = pbm->prom_node; |
97b3cf05 | 747 | struct pci_dev *host_pdev; |
a2fb23af DM |
748 | struct pci_bus *bus; |
749 | ||
750 | printk("PCI: Scanning PBM %s\n", node->full_name); | |
751 | ||
752 | /* XXX parent device? XXX */ | |
f1cd8de2 | 753 | bus = pci_create_bus(NULL, pbm->pci_first_busno, pbm->pci_ops, pbm); |
a2fb23af DM |
754 | if (!bus) { |
755 | printk(KERN_ERR "Failed to create bus for %s\n", | |
756 | node->full_name); | |
757 | return NULL; | |
758 | } | |
759 | bus->secondary = pbm->pci_first_busno; | |
760 | bus->subordinate = pbm->pci_last_busno; | |
761 | ||
762 | bus->resource[0] = &pbm->io_space; | |
763 | bus->resource[1] = &pbm->mem_space; | |
764 | ||
97b3cf05 DM |
765 | /* Create the dummy host bridge and link it in. */ |
766 | host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1); | |
767 | bus->self = host_pdev; | |
768 | ||
a2fb23af DM |
769 | pci_of_scan_bus(pbm, node, bus); |
770 | pci_bus_add_devices(bus); | |
771 | pci_bus_register_of_sysfs(bus); | |
772 | ||
773 | return bus; | |
774 | } | |
775 | ||
1da177e4 LT |
776 | static void __init pci_scan_each_controller_bus(void) |
777 | { | |
34768bc8 | 778 | struct pci_pbm_info *pbm; |
1da177e4 | 779 | |
34768bc8 DM |
780 | for (pbm = pci_pbm_root; pbm; pbm = pbm->next) |
781 | pbm->scan_bus(pbm); | |
1da177e4 LT |
782 | } |
783 | ||
1da177e4 LT |
784 | extern void power_init(void); |
785 | ||
786 | static int __init pcibios_init(void) | |
787 | { | |
788 | pci_controller_probe(); | |
34768bc8 | 789 | if (pci_pbm_root == NULL) |
1da177e4 LT |
790 | return 0; |
791 | ||
792 | pci_scan_each_controller_bus(); | |
793 | ||
1da177e4 LT |
794 | isa_init(); |
795 | ebus_init(); | |
1da177e4 LT |
796 | power_init(); |
797 | ||
798 | return 0; | |
799 | } | |
800 | ||
801 | subsys_initcall(pcibios_init); | |
802 | ||
f6b45da1 | 803 | void __devinit pcibios_fixup_bus(struct pci_bus *pbus) |
1da177e4 LT |
804 | { |
805 | struct pci_pbm_info *pbm = pbus->sysdata; | |
806 | ||
807 | /* Generic PCI bus probing sets these to point at | |
808 | * &io{port,mem}_resouce which is wrong for us. | |
809 | */ | |
810 | pbus->resource[0] = &pbm->io_space; | |
811 | pbus->resource[1] = &pbm->mem_space; | |
812 | } | |
813 | ||
085ae41f | 814 | struct resource *pcibios_select_root(struct pci_dev *pdev, struct resource *r) |
1da177e4 LT |
815 | { |
816 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
085ae41f | 817 | struct resource *root = NULL; |
1da177e4 | 818 | |
085ae41f | 819 | if (r->flags & IORESOURCE_IO) |
1da177e4 | 820 | root = &pbm->io_space; |
085ae41f | 821 | if (r->flags & IORESOURCE_MEM) |
1da177e4 LT |
822 | root = &pbm->mem_space; |
823 | ||
085ae41f | 824 | return root; |
1da177e4 LT |
825 | } |
826 | ||
827 | void pcibios_update_irq(struct pci_dev *pdev, int irq) | |
828 | { | |
829 | } | |
830 | ||
831 | void pcibios_align_resource(void *data, struct resource *res, | |
e31dd6e4 | 832 | resource_size_t size, resource_size_t align) |
1da177e4 LT |
833 | { |
834 | } | |
835 | ||
a2fb23af | 836 | int pcibios_enable_device(struct pci_dev *dev, int mask) |
1da177e4 | 837 | { |
a2fb23af DM |
838 | u16 cmd, oldcmd; |
839 | int i; | |
840 | ||
841 | pci_read_config_word(dev, PCI_COMMAND, &cmd); | |
842 | oldcmd = cmd; | |
843 | ||
844 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { | |
845 | struct resource *res = &dev->resource[i]; | |
846 | ||
847 | /* Only set up the requested stuff */ | |
848 | if (!(mask & (1<<i))) | |
849 | continue; | |
850 | ||
851 | if (res->flags & IORESOURCE_IO) | |
852 | cmd |= PCI_COMMAND_IO; | |
853 | if (res->flags & IORESOURCE_MEM) | |
854 | cmd |= PCI_COMMAND_MEMORY; | |
855 | } | |
856 | ||
857 | if (cmd != oldcmd) { | |
858 | printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n", | |
859 | pci_name(dev), cmd); | |
860 | /* Enable the appropriate bits in the PCI command register. */ | |
861 | pci_write_config_word(dev, PCI_COMMAND, cmd); | |
862 | } | |
1da177e4 LT |
863 | return 0; |
864 | } | |
865 | ||
866 | void pcibios_resource_to_bus(struct pci_dev *pdev, struct pci_bus_region *region, | |
867 | struct resource *res) | |
868 | { | |
869 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
870 | struct resource zero_res, *root; | |
871 | ||
872 | zero_res.start = 0; | |
873 | zero_res.end = 0; | |
874 | zero_res.flags = res->flags; | |
875 | ||
876 | if (res->flags & IORESOURCE_IO) | |
877 | root = &pbm->io_space; | |
878 | else | |
879 | root = &pbm->mem_space; | |
880 | ||
0bae5f81 | 881 | pci_resource_adjust(&zero_res, root); |
1da177e4 LT |
882 | |
883 | region->start = res->start - zero_res.start; | |
884 | region->end = res->end - zero_res.start; | |
885 | } | |
5fdfd42e | 886 | EXPORT_SYMBOL(pcibios_resource_to_bus); |
1da177e4 LT |
887 | |
888 | void pcibios_bus_to_resource(struct pci_dev *pdev, struct resource *res, | |
889 | struct pci_bus_region *region) | |
890 | { | |
891 | struct pci_pbm_info *pbm = pdev->bus->sysdata; | |
892 | struct resource *root; | |
893 | ||
894 | res->start = region->start; | |
895 | res->end = region->end; | |
896 | ||
897 | if (res->flags & IORESOURCE_IO) | |
898 | root = &pbm->io_space; | |
899 | else | |
900 | root = &pbm->mem_space; | |
901 | ||
0bae5f81 | 902 | pci_resource_adjust(res, root); |
1da177e4 | 903 | } |
41290c14 | 904 | EXPORT_SYMBOL(pcibios_bus_to_resource); |
1da177e4 | 905 | |
f6b45da1 | 906 | char * __devinit pcibios_setup(char *str) |
1da177e4 | 907 | { |
1da177e4 LT |
908 | return str; |
909 | } | |
910 | ||
911 | /* Platform support for /proc/bus/pci/X/Y mmap()s. */ | |
912 | ||
913 | /* If the user uses a host-bridge as the PCI device, he may use | |
914 | * this to perform a raw mmap() of the I/O or MEM space behind | |
915 | * that controller. | |
916 | * | |
917 | * This can be useful for execution of x86 PCI bios initialization code | |
918 | * on a PCI card, like the xfree86 int10 stuff does. | |
919 | */ | |
920 | static int __pci_mmap_make_offset_bus(struct pci_dev *pdev, struct vm_area_struct *vma, | |
921 | enum pci_mmap_state mmap_state) | |
922 | { | |
a2fb23af | 923 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
1da177e4 LT |
924 | struct pci_controller_info *p; |
925 | unsigned long space_size, user_offset, user_size; | |
926 | ||
1da177e4 | 927 | p = pbm->parent; |
3875c5c0 DM |
928 | if (mmap_state == pci_mmap_io) { |
929 | space_size = (pbm->io_space.end - | |
930 | pbm->io_space.start) + 1; | |
1da177e4 | 931 | } else { |
3875c5c0 DM |
932 | space_size = (pbm->mem_space.end - |
933 | pbm->mem_space.start) + 1; | |
1da177e4 LT |
934 | } |
935 | ||
936 | /* Make sure the request is in range. */ | |
937 | user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
938 | user_size = vma->vm_end - vma->vm_start; | |
939 | ||
940 | if (user_offset >= space_size || | |
941 | (user_offset + user_size) > space_size) | |
942 | return -EINVAL; | |
943 | ||
3875c5c0 DM |
944 | if (mmap_state == pci_mmap_io) { |
945 | vma->vm_pgoff = (pbm->io_space.start + | |
946 | user_offset) >> PAGE_SHIFT; | |
1da177e4 | 947 | } else { |
3875c5c0 DM |
948 | vma->vm_pgoff = (pbm->mem_space.start + |
949 | user_offset) >> PAGE_SHIFT; | |
1da177e4 LT |
950 | } |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
955 | /* Adjust vm_pgoff of VMA such that it is the physical page offset corresponding | |
956 | * to the 32-bit pci bus offset for DEV requested by the user. | |
957 | * | |
958 | * Basically, the user finds the base address for his device which he wishes | |
959 | * to mmap. They read the 32-bit value from the config space base register, | |
960 | * add whatever PAGE_SIZE multiple offset they wish, and feed this into the | |
961 | * offset parameter of mmap on /proc/bus/pci/XXX for that device. | |
962 | * | |
963 | * Returns negative error code on failure, zero on success. | |
964 | */ | |
965 | static int __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma, | |
966 | enum pci_mmap_state mmap_state) | |
967 | { | |
968 | unsigned long user_offset = vma->vm_pgoff << PAGE_SHIFT; | |
969 | unsigned long user32 = user_offset & pci_memspace_mask; | |
970 | unsigned long largest_base, this_base, addr32; | |
971 | int i; | |
972 | ||
973 | if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) | |
974 | return __pci_mmap_make_offset_bus(dev, vma, mmap_state); | |
975 | ||
976 | /* Figure out which base address this is for. */ | |
977 | largest_base = 0UL; | |
978 | for (i = 0; i <= PCI_ROM_RESOURCE; i++) { | |
979 | struct resource *rp = &dev->resource[i]; | |
980 | ||
981 | /* Active? */ | |
982 | if (!rp->flags) | |
983 | continue; | |
984 | ||
985 | /* Same type? */ | |
986 | if (i == PCI_ROM_RESOURCE) { | |
987 | if (mmap_state != pci_mmap_mem) | |
988 | continue; | |
989 | } else { | |
990 | if ((mmap_state == pci_mmap_io && | |
991 | (rp->flags & IORESOURCE_IO) == 0) || | |
992 | (mmap_state == pci_mmap_mem && | |
993 | (rp->flags & IORESOURCE_MEM) == 0)) | |
994 | continue; | |
995 | } | |
996 | ||
997 | this_base = rp->start; | |
998 | ||
999 | addr32 = (this_base & PAGE_MASK) & pci_memspace_mask; | |
1000 | ||
1001 | if (mmap_state == pci_mmap_io) | |
1002 | addr32 &= 0xffffff; | |
1003 | ||
1004 | if (addr32 <= user32 && this_base > largest_base) | |
1005 | largest_base = this_base; | |
1006 | } | |
1007 | ||
1008 | if (largest_base == 0UL) | |
1009 | return -EINVAL; | |
1010 | ||
1011 | /* Now construct the final physical address. */ | |
1012 | if (mmap_state == pci_mmap_io) | |
1013 | vma->vm_pgoff = (((largest_base & ~0xffffffUL) | user32) >> PAGE_SHIFT); | |
1014 | else | |
1015 | vma->vm_pgoff = (((largest_base & ~(pci_memspace_mask)) | user32) >> PAGE_SHIFT); | |
1016 | ||
1017 | return 0; | |
1018 | } | |
1019 | ||
1020 | /* Set vm_flags of VMA, as appropriate for this architecture, for a pci device | |
1021 | * mapping. | |
1022 | */ | |
1023 | static void __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma, | |
1024 | enum pci_mmap_state mmap_state) | |
1025 | { | |
1026 | vma->vm_flags |= (VM_IO | VM_RESERVED); | |
1027 | } | |
1028 | ||
1029 | /* Set vm_page_prot of VMA, as appropriate for this architecture, for a pci | |
1030 | * device mapping. | |
1031 | */ | |
1032 | static void __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma, | |
1033 | enum pci_mmap_state mmap_state) | |
1034 | { | |
a7a6cac2 | 1035 | /* Our io_remap_pfn_range takes care of this, do nothing. */ |
1da177e4 LT |
1036 | } |
1037 | ||
1038 | /* Perform the actual remap of the pages for a PCI device mapping, as appropriate | |
1039 | * for this architecture. The region in the process to map is described by vm_start | |
1040 | * and vm_end members of VMA, the base physical address is found in vm_pgoff. | |
1041 | * The pci device structure is provided so that architectures may make mapping | |
1042 | * decisions on a per-device or per-bus basis. | |
1043 | * | |
1044 | * Returns a negative error code on failure, zero on success. | |
1045 | */ | |
1046 | int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, | |
1047 | enum pci_mmap_state mmap_state, | |
1048 | int write_combine) | |
1049 | { | |
1050 | int ret; | |
1051 | ||
1052 | ret = __pci_mmap_make_offset(dev, vma, mmap_state); | |
1053 | if (ret < 0) | |
1054 | return ret; | |
1055 | ||
1056 | __pci_mmap_set_flags(dev, vma, mmap_state); | |
1057 | __pci_mmap_set_pgprot(dev, vma, mmap_state); | |
1058 | ||
14778d90 | 1059 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); |
1da177e4 LT |
1060 | ret = io_remap_pfn_range(vma, vma->vm_start, |
1061 | vma->vm_pgoff, | |
1062 | vma->vm_end - vma->vm_start, | |
1063 | vma->vm_page_prot); | |
1064 | if (ret) | |
1065 | return ret; | |
1066 | ||
1da177e4 LT |
1067 | return 0; |
1068 | } | |
1069 | ||
1070 | /* Return the domain nuber for this pci bus */ | |
1071 | ||
1072 | int pci_domain_nr(struct pci_bus *pbus) | |
1073 | { | |
1074 | struct pci_pbm_info *pbm = pbus->sysdata; | |
1075 | int ret; | |
1076 | ||
1077 | if (pbm == NULL || pbm->parent == NULL) { | |
1078 | ret = -ENXIO; | |
1079 | } else { | |
1080 | struct pci_controller_info *p = pbm->parent; | |
1081 | ||
1082 | ret = p->index; | |
3875c5c0 DM |
1083 | ret = ((ret << 1) + |
1084 | ((pbm == &pbm->parent->pbm_B) ? 1 : 0)); | |
1da177e4 LT |
1085 | } |
1086 | ||
1087 | return ret; | |
1088 | } | |
1089 | EXPORT_SYMBOL(pci_domain_nr); | |
1090 | ||
35a17eb6 DM |
1091 | #ifdef CONFIG_PCI_MSI |
1092 | int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) | |
1093 | { | |
a2fb23af | 1094 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 DM |
1095 | struct pci_controller_info *p = pbm->parent; |
1096 | int virt_irq, err; | |
1097 | ||
1098 | if (!pbm->msi_num || !p->setup_msi_irq) | |
1099 | return -EINVAL; | |
1100 | ||
1101 | err = p->setup_msi_irq(&virt_irq, pdev, desc); | |
7fe3730d | 1102 | if (err) |
35a17eb6 DM |
1103 | return err; |
1104 | ||
7fe3730d | 1105 | return 0; |
35a17eb6 DM |
1106 | } |
1107 | ||
1108 | void arch_teardown_msi_irq(unsigned int virt_irq) | |
1109 | { | |
abfd336c | 1110 | struct msi_desc *entry = get_irq_msi(virt_irq); |
35a17eb6 | 1111 | struct pci_dev *pdev = entry->dev; |
a2fb23af | 1112 | struct pci_pbm_info *pbm = pdev->dev.archdata.host_controller; |
35a17eb6 DM |
1113 | struct pci_controller_info *p = pbm->parent; |
1114 | ||
1115 | if (!pbm->msi_num || !p->setup_msi_irq) | |
1116 | return; | |
1117 | ||
1118 | return p->teardown_msi_irq(virt_irq, pdev); | |
1119 | } | |
1120 | #endif /* !(CONFIG_PCI_MSI) */ | |
1121 | ||
f6d0f9ea DM |
1122 | struct device_node *pci_device_to_OF_node(struct pci_dev *pdev) |
1123 | { | |
a2fb23af | 1124 | return pdev->dev.archdata.prom_node; |
f6d0f9ea DM |
1125 | } |
1126 | EXPORT_SYMBOL(pci_device_to_OF_node); | |
1127 | ||
1da177e4 | 1128 | #endif /* !(CONFIG_PCI) */ |