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[SPARC64]: Move index info pci_pbm_info.
[mirror_ubuntu-bionic-kernel.git] / arch / sparc64 / kernel / pci_psycho.c
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9fd8b647 1/* pci_psycho.c: PSYCHO/U2P specific PCI controller support.
1da177e4 2 *
9fd8b647 3 * Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
5 * Copyright (C) 1999 Jakub Jelinek (jakub@redhat.com)
6 */
7
8#include <linux/kernel.h>
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/init.h>
12#include <linux/slab.h>
13#include <linux/interrupt.h>
14
15#include <asm/pbm.h>
16#include <asm/iommu.h>
17#include <asm/irq.h>
18#include <asm/starfire.h>
e87dc350 19#include <asm/prom.h>
2b1e5978 20#include <asm/of_device.h>
1da177e4
LT		 21
22#include "pci_impl.h"
23#include "iommu_common.h"
24
25/* All PSYCHO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
28 */
29#define psycho_read(__reg) \
30({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36})
37#define psycho_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43
44/* Misc. PSYCHO PCI controller register offsets and definitions. */
45#define PSYCHO_CONTROL 0x0010UL
46#define PSYCHO_CONTROL_IMPL 0xf000000000000000UL /* Implementation of this PSYCHO*/
47#define PSYCHO_CONTROL_VER 0x0f00000000000000UL /* Version of this PSYCHO */
48#define PSYCHO_CONTROL_MID 0x00f8000000000000UL /* UPA Module ID of PSYCHO */
49#define PSYCHO_CONTROL_IGN 0x0007c00000000000UL /* Interrupt Group Number */
50#define PSYCHO_CONTROL_RESV 0x00003ffffffffff0UL /* Reserved */
51#define PSYCHO_CONTROL_APCKEN 0x0000000000000008UL /* Address Parity Check Enable */
52#define PSYCHO_CONTROL_APERR 0x0000000000000004UL /* Incoming System Addr Parerr */
53#define PSYCHO_CONTROL_IAP 0x0000000000000002UL /* Invert UPA Parity */
54#define PSYCHO_CONTROL_MODE 0x0000000000000001UL /* PSYCHO clock mode */
55#define PSYCHO_PCIA_CTRL 0x2000UL
56#define PSYCHO_PCIB_CTRL 0x4000UL
57#define PSYCHO_PCICTRL_RESV1 0xfffffff000000000UL /* Reserved */
58#define PSYCHO_PCICTRL_SBH_ERR 0x0000000800000000UL /* Streaming byte hole error */
59#define PSYCHO_PCICTRL_SERR 0x0000000400000000UL /* SERR signal asserted */
60#define PSYCHO_PCICTRL_SPEED 0x0000000200000000UL /* PCI speed (1 is U2P clock) */
61#define PSYCHO_PCICTRL_RESV2 0x00000001ffc00000UL /* Reserved */
62#define PSYCHO_PCICTRL_ARB_PARK 0x0000000000200000UL /* PCI arbitration parking */
63#define PSYCHO_PCICTRL_RESV3 0x00000000001ff800UL /* Reserved */
64#define PSYCHO_PCICTRL_SBH_INT 0x0000000000000400UL /* Streaming byte hole int enab */
65#define PSYCHO_PCICTRL_WEN 0x0000000000000200UL /* Power Mgmt Wake Enable */
66#define PSYCHO_PCICTRL_EEN 0x0000000000000100UL /* PCI Error Interrupt Enable */
67#define PSYCHO_PCICTRL_RESV4 0x00000000000000c0UL /* Reserved */
68#define PSYCHO_PCICTRL_AEN 0x000000000000003fUL /* PCI DVMA Arbitration Enable */
69
70/* U2P Programmer's Manual, page 13-55, configuration space
71 * address format:
72 *
73 * 32 24 23 16 15 11 10 8 7 2 1 0
74 * ---------------------------------------------------------
75 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
76 * ---------------------------------------------------------
77 */
78#define PSYCHO_CONFIG_BASE(PBM) \
79 ((PBM)->config_space | (1UL << 24))
80#define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \
81 (((unsigned long)(BUS) << 16) | \
82 ((unsigned long)(DEVFN) << 8) | \
83 ((unsigned long)(REG)))
84
85static void *psycho_pci_config_mkaddr(struct pci_pbm_info *pbm,
86 unsigned char bus,
87 unsigned int devfn,
88 int where)
89{
90 if (!pbm)
91 return NULL;
92 return (void *)
93 (PSYCHO_CONFIG_BASE(pbm) |
94 PSYCHO_CONFIG_ENCODE(bus, devfn, where));
95}
96
97static int psycho_out_of_range(struct pci_pbm_info *pbm,
98 unsigned char bus,
99 unsigned char devfn)
100{
101 return ((pbm->parent == 0) ||
102 ((pbm == &pbm->parent->pbm_B) &&
103 (bus == pbm->pci_first_busno) &&
104 PCI_SLOT(devfn) > 8) ||
105 ((pbm == &pbm->parent->pbm_A) &&
106 (bus == pbm->pci_first_busno) &&
107 PCI_SLOT(devfn) > 8));
108}
109
110/* PSYCHO PCI configuration space accessors. */
111
112static int psycho_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
113 int where, int size, u32 *value)
114{
115 struct pci_pbm_info *pbm = bus_dev->sysdata;
116 unsigned char bus = bus_dev->number;
117 u32 *addr;
118 u16 tmp16;
119 u8 tmp8;
120
97b3cf05
DM		 121 if (bus_dev == pbm->pci_bus && devfn == 0x00)
122 return pci_host_bridge_read_pci_cfg(bus_dev, devfn, where,
123 size, value);
124
1da177e4
LT		 125 switch (size) {
126 case 1:
127 *value = 0xff;
128 break;
129 case 2:
130 *value = 0xffff;
131 break;
132 case 4:
133 *value = 0xffffffff;
134 break;
135 }
136
137 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
138 if (!addr)
139 return PCIBIOS_SUCCESSFUL;
140
141 if (psycho_out_of_range(pbm, bus, devfn))
142 return PCIBIOS_SUCCESSFUL;
143 switch (size) {
144 case 1:
145 pci_config_read8((u8 *)addr, &tmp8);
146 *value = (u32) tmp8;
147 break;
148
149 case 2:
150 if (where & 0x01) {
151 printk("pci_read_config_word: misaligned reg [%x]\n",
152 where);
153 return PCIBIOS_SUCCESSFUL;
154 }
155 pci_config_read16((u16 *)addr, &tmp16);
156 *value = (u32) tmp16;
157 break;
158
159 case 4:
160 if (where & 0x03) {
161 printk("pci_read_config_dword: misaligned reg [%x]\n",
162 where);
163 return PCIBIOS_SUCCESSFUL;
164 }
165 pci_config_read32(addr, value);
166 break;
167 }
168 return PCIBIOS_SUCCESSFUL;
169}
170
171static int psycho_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
172 int where, int size, u32 value)
173{
174 struct pci_pbm_info *pbm = bus_dev->sysdata;
175 unsigned char bus = bus_dev->number;
176 u32 *addr;
177
97b3cf05
DM		 178 if (bus_dev == pbm->pci_bus && devfn == 0x00)
179 return pci_host_bridge_write_pci_cfg(bus_dev, devfn, where,
180 size, value);
1da177e4
LT		 181 addr = psycho_pci_config_mkaddr(pbm, bus, devfn, where);
182 if (!addr)
183 return PCIBIOS_SUCCESSFUL;
184
185 if (psycho_out_of_range(pbm, bus, devfn))
186 return PCIBIOS_SUCCESSFUL;
187
188 switch (size) {
189 case 1:
190 pci_config_write8((u8 *)addr, value);
191 break;
192
193 case 2:
194 if (where & 0x01) {
195 printk("pci_write_config_word: misaligned reg [%x]\n",
196 where);
197 return PCIBIOS_SUCCESSFUL;
198 }
199 pci_config_write16((u16 *)addr, value);
200 break;
201
202 case 4:
203 if (where & 0x03) {
204 printk("pci_write_config_dword: misaligned reg [%x]\n",
205 where);
206 return PCIBIOS_SUCCESSFUL;
207 }
208 pci_config_write32(addr, value);
209 }
210 return PCIBIOS_SUCCESSFUL;
211}
212
213static struct pci_ops psycho_ops = {
214 .read = psycho_read_pci_cfg,
215 .write = psycho_write_pci_cfg,
216};
217
1da177e4
LT		 218/* PSYCHO error handling support. */
219enum psycho_error_type {
220 UE_ERR, CE_ERR, PCI_ERR
221};
222
223/* Helper function of IOMMU error checking, which checks out
224 * the state of the streaming buffers. The IOMMU lock is
225 * held when this is called.
226 *
227 * For the PCI error case we know which PBM (and thus which
228 * streaming buffer) caused the error, but for the uncorrectable
229 * error case we do not. So we always check both streaming caches.
230 */
231#define PSYCHO_STRBUF_CONTROL_A 0x2800UL
232#define PSYCHO_STRBUF_CONTROL_B 0x4800UL
233#define PSYCHO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
234#define PSYCHO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
235#define PSYCHO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
236#define PSYCHO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
237#define PSYCHO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
238#define PSYCHO_STRBUF_FLUSH_A 0x2808UL
239#define PSYCHO_STRBUF_FLUSH_B 0x4808UL
240#define PSYCHO_STRBUF_FSYNC_A 0x2810UL
241#define PSYCHO_STRBUF_FSYNC_B 0x4810UL
242#define PSYCHO_STC_DATA_A 0xb000UL
243#define PSYCHO_STC_DATA_B 0xc000UL
244#define PSYCHO_STC_ERR_A 0xb400UL
245#define PSYCHO_STC_ERR_B 0xc400UL
246#define PSYCHO_STCERR_WRITE 0x0000000000000002UL /* Write Error */
247#define PSYCHO_STCERR_READ 0x0000000000000001UL /* Read Error */
248#define PSYCHO_STC_TAG_A 0xb800UL
249#define PSYCHO_STC_TAG_B 0xc800UL
250#define PSYCHO_STCTAG_PPN 0x0fffffff00000000UL /* Physical Page Number */
251#define PSYCHO_STCTAG_VPN 0x00000000ffffe000UL /* Virtual Page Number */
252#define PSYCHO_STCTAG_VALID 0x0000000000000002UL /* Valid */
253#define PSYCHO_STCTAG_WRITE 0x0000000000000001UL /* Writable */
254#define PSYCHO_STC_LINE_A 0xb900UL
255#define PSYCHO_STC_LINE_B 0xc900UL
256#define PSYCHO_STCLINE_LINDX 0x0000000001e00000UL /* LRU Index */
257#define PSYCHO_STCLINE_SPTR 0x00000000001f8000UL /* Dirty Data Start Pointer */
258#define PSYCHO_STCLINE_LADDR 0x0000000000007f00UL /* Line Address */
259#define PSYCHO_STCLINE_EPTR 0x00000000000000fcUL /* Dirty Data End Pointer */
260#define PSYCHO_STCLINE_VALID 0x0000000000000002UL /* Valid */
261#define PSYCHO_STCLINE_FOFN 0x0000000000000001UL /* Fetch Outstanding / Flush Necessary */
262
263static DEFINE_SPINLOCK(stc_buf_lock);
264static unsigned long stc_error_buf[128];
265static unsigned long stc_tag_buf[16];
266static unsigned long stc_line_buf[16];
267
34768bc8 268static void __psycho_check_one_stc(struct pci_pbm_info *pbm,
1da177e4
LT		 269 int is_pbm_a)
270{
16ce82d8 271 struct strbuf *strbuf = &pbm->stc;
34768bc8 272 unsigned long regbase = pbm->controller_regs;
1da177e4
LT		 273 unsigned long err_base, tag_base, line_base;
274 u64 control;
275 int i;
276
277 if (is_pbm_a) {
278 err_base = regbase + PSYCHO_STC_ERR_A;
279 tag_base = regbase + PSYCHO_STC_TAG_A;
280 line_base = regbase + PSYCHO_STC_LINE_A;
281 } else {
282 err_base = regbase + PSYCHO_STC_ERR_B;
283 tag_base = regbase + PSYCHO_STC_TAG_B;
284 line_base = regbase + PSYCHO_STC_LINE_B;
285 }
286
287 spin_lock(&stc_buf_lock);
288
289 /* This is __REALLY__ dangerous. When we put the
290 * streaming buffer into diagnostic mode to probe
291 * it's tags and error status, we _must_ clear all
292 * of the line tag valid bits before re-enabling
293 * the streaming buffer. If any dirty data lives
294 * in the STC when we do this, we will end up
295 * invalidating it before it has a chance to reach
296 * main memory.
297 */
298 control = psycho_read(strbuf->strbuf_control);
299 psycho_write(strbuf->strbuf_control,
300 (control | PSYCHO_STRBUF_CTRL_DENAB));
301 for (i = 0; i < 128; i++) {
302 unsigned long val;
303
304 val = psycho_read(err_base + (i * 8UL));
305 psycho_write(err_base + (i * 8UL), 0UL);
306 stc_error_buf[i] = val;
307 }
308 for (i = 0; i < 16; i++) {
309 stc_tag_buf[i] = psycho_read(tag_base + (i * 8UL));
310 stc_line_buf[i] = psycho_read(line_base + (i * 8UL));
311 psycho_write(tag_base + (i * 8UL), 0UL);
312 psycho_write(line_base + (i * 8UL), 0UL);
313 }
314
315 /* OK, state is logged, exit diagnostic mode. */
316 psycho_write(strbuf->strbuf_control, control);
317
318 for (i = 0; i < 16; i++) {
319 int j, saw_error, first, last;
320
321 saw_error = 0;
322 first = i * 8;
323 last = first + 8;
324 for (j = first; j < last; j++) {
325 unsigned long errval = stc_error_buf[j];
326 if (errval != 0) {
327 saw_error++;
6c108f12
DM		 328 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
329 pbm->name,
1da177e4
LT		 330 j,
331 (errval & PSYCHO_STCERR_WRITE) ? 1 : 0,
332 (errval & PSYCHO_STCERR_READ) ? 1 : 0);
333 }
334 }
335 if (saw_error != 0) {
336 unsigned long tagval = stc_tag_buf[i];
337 unsigned long lineval = stc_line_buf[i];
6c108f12
DM		 338 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)W(%d)]\n",
339 pbm->name,
1da177e4
LT		 340 i,
341 ((tagval & PSYCHO_STCTAG_PPN) >> 19UL),
342 (tagval & PSYCHO_STCTAG_VPN),
343 ((tagval & PSYCHO_STCTAG_VALID) ? 1 : 0),
344 ((tagval & PSYCHO_STCTAG_WRITE) ? 1 : 0));
6c108f12 345 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
1da177e4 346 "V(%d)FOFN(%d)]\n",
6c108f12 347 pbm->name,
1da177e4
LT		 348 i,
349 ((lineval & PSYCHO_STCLINE_LINDX) >> 21UL),
350 ((lineval & PSYCHO_STCLINE_SPTR) >> 15UL),
351 ((lineval & PSYCHO_STCLINE_LADDR) >> 8UL),
352 ((lineval & PSYCHO_STCLINE_EPTR) >> 2UL),
353 ((lineval & PSYCHO_STCLINE_VALID) ? 1 : 0),
354 ((lineval & PSYCHO_STCLINE_FOFN) ? 1 : 0));
355 }
356 }
357
358 spin_unlock(&stc_buf_lock);
359}
360
34768bc8 361static void __psycho_check_stc_error(struct pci_pbm_info *pbm,
1da177e4
LT		 362 unsigned long afsr,
363 unsigned long afar,
364 enum psycho_error_type type)
365{
34768bc8
DM		 366 __psycho_check_one_stc(pbm,
367 (pbm == &pbm->parent->pbm_A));
1da177e4
LT		 368}
369
370/* When an Uncorrectable Error or a PCI Error happens, we
371 * interrogate the IOMMU state to see if it is the cause.
372 */
373#define PSYCHO_IOMMU_CONTROL 0x0200UL
374#define PSYCHO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
375#define PSYCHO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
376#define PSYCHO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
377#define PSYCHO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
378#define PSYCHO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
379#define PSYCHO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
380#define PSYCHO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
381#define PSYCHO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
382#define PSYCHO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
383#define PSYCHO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
384#define PSYCHO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
385#define PSYCHO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
386#define PSYCHO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
387#define PSYCHO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
388#define PSYCHO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
389#define PSYCHO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
390#define PSYCHO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
391#define PSYCHO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
392#define PSYCHO_IOMMU_TSBBASE 0x0208UL
393#define PSYCHO_IOMMU_FLUSH 0x0210UL
394#define PSYCHO_IOMMU_TAG 0xa580UL
395#define PSYCHO_IOMMU_TAG_ERRSTS (0x3UL << 23UL)
396#define PSYCHO_IOMMU_TAG_ERR (0x1UL << 22UL)
397#define PSYCHO_IOMMU_TAG_WRITE (0x1UL << 21UL)
398#define PSYCHO_IOMMU_TAG_STREAM (0x1UL << 20UL)
399#define PSYCHO_IOMMU_TAG_SIZE (0x1UL << 19UL)
400#define PSYCHO_IOMMU_TAG_VPAGE 0x7ffffUL
401#define PSYCHO_IOMMU_DATA 0xa600UL
402#define PSYCHO_IOMMU_DATA_VALID (1UL << 30UL)
403#define PSYCHO_IOMMU_DATA_CACHE (1UL << 28UL)
404#define PSYCHO_IOMMU_DATA_PPAGE 0xfffffffUL
34768bc8 405static void psycho_check_iommu_error(struct pci_pbm_info *pbm,
1da177e4
LT		 406 unsigned long afsr,
407 unsigned long afar,
408 enum psycho_error_type type)
409{
34768bc8 410 struct iommu *iommu = pbm->iommu;
1da177e4
LT		 411 unsigned long iommu_tag[16];
412 unsigned long iommu_data[16];
413 unsigned long flags;
414 u64 control;
415 int i;
416
417 spin_lock_irqsave(&iommu->lock, flags);
418 control = psycho_read(iommu->iommu_control);
419 if (control & PSYCHO_IOMMU_CTRL_XLTEERR) {
420 char *type_string;
421
422 /* Clear the error encountered bit. */
423 control &= ~PSYCHO_IOMMU_CTRL_XLTEERR;
424 psycho_write(iommu->iommu_control, control);
425
426 switch((control & PSYCHO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
427 case 0:
428 type_string = "Protection Error";
429 break;
430 case 1:
431 type_string = "Invalid Error";
432 break;
433 case 2:
434 type_string = "TimeOut Error";
435 break;
436 case 3:
437 default:
438 type_string = "ECC Error";
439 break;
440 };
6c108f12
DM		 441 printk("%s: IOMMU Error, type[%s]\n",
442 pbm->name, type_string);
1da177e4
LT		 443
444 /* Put the IOMMU into diagnostic mode and probe
445 * it's TLB for entries with error status.
446 *
447 * It is very possible for another DVMA to occur
448 * while we do this probe, and corrupt the system
449 * further. But we are so screwed at this point
450 * that we are likely to crash hard anyways, so
451 * get as much diagnostic information to the
452 * console as we can.
453 */
454 psycho_write(iommu->iommu_control,
455 control | PSYCHO_IOMMU_CTRL_DENAB);
456 for (i = 0; i < 16; i++) {
34768bc8 457 unsigned long base = pbm->controller_regs;
1da177e4
LT		 458
459 iommu_tag[i] =
460 psycho_read(base + PSYCHO_IOMMU_TAG + (i * 8UL));
461 iommu_data[i] =
462 psycho_read(base + PSYCHO_IOMMU_DATA + (i * 8UL));
463
464 /* Now clear out the entry. */
465 psycho_write(base + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
466 psycho_write(base + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
467 }
468
469 /* Leave diagnostic mode. */
470 psycho_write(iommu->iommu_control, control);
471
472 for (i = 0; i < 16; i++) {
473 unsigned long tag, data;
474
475 tag = iommu_tag[i];
476 if (!(tag & PSYCHO_IOMMU_TAG_ERR))
477 continue;
478
479 data = iommu_data[i];
480 switch((tag & PSYCHO_IOMMU_TAG_ERRSTS) >> 23UL) {
481 case 0:
482 type_string = "Protection Error";
483 break;
484 case 1:
485 type_string = "Invalid Error";
486 break;
487 case 2:
488 type_string = "TimeOut Error";
489 break;
490 case 3:
491 default:
492 type_string = "ECC Error";
493 break;
494 };
6c108f12
DM		 495 printk("%s: IOMMU TAG(%d)[error(%s) wr(%d) str(%d) sz(%dK) vpg(%08lx)]\n",
496 pbm->name, i, type_string,
1da177e4
LT		 497 ((tag & PSYCHO_IOMMU_TAG_WRITE) ? 1 : 0),
498 ((tag & PSYCHO_IOMMU_TAG_STREAM) ? 1 : 0),
499 ((tag & PSYCHO_IOMMU_TAG_SIZE) ? 64 : 8),
500 (tag & PSYCHO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
6c108f12
DM		 501 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
502 pbm->name, i,
1da177e4
LT		 503 ((data & PSYCHO_IOMMU_DATA_VALID) ? 1 : 0),
504 ((data & PSYCHO_IOMMU_DATA_CACHE) ? 1 : 0),
505 (data & PSYCHO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
506 }
507 }
34768bc8 508 __psycho_check_stc_error(pbm, afsr, afar, type);
1da177e4
LT		 509 spin_unlock_irqrestore(&iommu->lock, flags);
510}
511
512/* Uncorrectable Errors. Cause of the error and the address are
513 * recorded in the UE_AFSR and UE_AFAR of PSYCHO. They are errors
514 * relating to UPA interface transactions.
515 */
516#define PSYCHO_UE_AFSR 0x0030UL
517#define PSYCHO_UEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
518#define PSYCHO_UEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
519#define PSYCHO_UEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
520#define PSYCHO_UEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
521#define PSYCHO_UEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
522#define PSYCHO_UEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
523#define PSYCHO_UEAFSR_RESV1 0x03ff000000000000UL /* Reserved */
524#define PSYCHO_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
525#define PSYCHO_UEAFSR_DOFF 0x00000000e0000000UL /* Doubleword Offset */
526#define PSYCHO_UEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
527#define PSYCHO_UEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
528#define PSYCHO_UEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
529#define PSYCHO_UE_AFAR 0x0038UL
530
6d24c8dc 531static irqreturn_t psycho_ue_intr(int irq, void *dev_id)
1da177e4 532{
34768bc8
DM		 533 struct pci_pbm_info *pbm = dev_id;
534 struct pci_controller_info *p = pbm->parent;
535 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_UE_AFSR;
536 unsigned long afar_reg = pbm->controller_regs + PSYCHO_UE_AFAR;
1da177e4
LT		 537 unsigned long afsr, afar, error_bits;
538 int reported;
539
540 /* Latch uncorrectable error status. */
541 afar = psycho_read(afar_reg);
542 afsr = psycho_read(afsr_reg);
543
544 /* Clear the primary/secondary error status bits. */
545 error_bits = afsr &
546 (PSYCHO_UEAFSR_PPIO | PSYCHO_UEAFSR_PDRD | PSYCHO_UEAFSR_PDWR |
547 PSYCHO_UEAFSR_SPIO | PSYCHO_UEAFSR_SDRD | PSYCHO_UEAFSR_SDWR);
548 if (!error_bits)
549 return IRQ_NONE;
550 psycho_write(afsr_reg, error_bits);
551
552 /* Log the error. */
6c108f12
DM		 553 printk("%s: Uncorrectable Error, primary error type[%s]\n",
554 pbm->name,
1da177e4
LT		 555 (((error_bits & PSYCHO_UEAFSR_PPIO) ?
556 "PIO" :
557 ((error_bits & PSYCHO_UEAFSR_PDRD) ?
558 "DMA Read" :
559 ((error_bits & PSYCHO_UEAFSR_PDWR) ?
560 "DMA Write" : "???")))));
6c108f12
DM		 561 printk("%s: bytemask[%04lx] dword_offset[%lx] UPA_MID[%02lx] was_block(%d)\n",
562 pbm->name,
1da177e4
LT		 563 (afsr & PSYCHO_UEAFSR_BMSK) >> 32UL,
564 (afsr & PSYCHO_UEAFSR_DOFF) >> 29UL,
565 (afsr & PSYCHO_UEAFSR_MID) >> 24UL,
566 ((afsr & PSYCHO_UEAFSR_BLK) ? 1 : 0));
6c108f12
DM		 567 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
568 printk("%s: UE Secondary errors [", pbm->name);
1da177e4
LT		 569 reported = 0;
570 if (afsr & PSYCHO_UEAFSR_SPIO) {
571 reported++;
572 printk("(PIO)");
573 }
574 if (afsr & PSYCHO_UEAFSR_SDRD) {
575 reported++;
576 printk("(DMA Read)");
577 }
578 if (afsr & PSYCHO_UEAFSR_SDWR) {
579 reported++;
580 printk("(DMA Write)");
581 }
582 if (!reported)
583 printk("(none)");
584 printk("]\n");
585
34768bc8
DM		 586 /* Interrogate both IOMMUs for error status. */
587 psycho_check_iommu_error(&p->pbm_A, afsr, afar, UE_ERR);
588 psycho_check_iommu_error(&p->pbm_B, afsr, afar, UE_ERR);
1da177e4
LT		 589
590 return IRQ_HANDLED;
591}
592
593/* Correctable Errors. */
594#define PSYCHO_CE_AFSR 0x0040UL
595#define PSYCHO_CEAFSR_PPIO 0x8000000000000000UL /* Primary PIO is cause */
596#define PSYCHO_CEAFSR_PDRD 0x4000000000000000UL /* Primary DVMA read is cause */
597#define PSYCHO_CEAFSR_PDWR 0x2000000000000000UL /* Primary DVMA write is cause */
598#define PSYCHO_CEAFSR_SPIO 0x1000000000000000UL /* Secondary PIO is cause */
599#define PSYCHO_CEAFSR_SDRD 0x0800000000000000UL /* Secondary DVMA read is cause */
600#define PSYCHO_CEAFSR_SDWR 0x0400000000000000UL /* Secondary DVMA write is cause*/
601#define PSYCHO_CEAFSR_RESV1 0x0300000000000000UL /* Reserved */
602#define PSYCHO_CEAFSR_ESYND 0x00ff000000000000UL /* Syndrome Bits */
603#define PSYCHO_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
604#define PSYCHO_CEAFSR_DOFF 0x00000000e0000000UL /* Double Offset */
605#define PSYCHO_CEAFSR_MID 0x000000001f000000UL /* UPA MID causing the fault */
606#define PSYCHO_CEAFSR_BLK 0x0000000000800000UL /* Trans was block operation */
607#define PSYCHO_CEAFSR_RESV2 0x00000000007fffffUL /* Reserved */
608#define PSYCHO_CE_AFAR 0x0040UL
609
6d24c8dc 610static irqreturn_t psycho_ce_intr(int irq, void *dev_id)
1da177e4 611{
34768bc8 612 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 613 unsigned long afsr_reg = pbm->controller_regs + PSYCHO_CE_AFSR;
614 unsigned long afar_reg = pbm->controller_regs + PSYCHO_CE_AFAR;
1da177e4
LT		 615 unsigned long afsr, afar, error_bits;
616 int reported;
617
618 /* Latch error status. */
619 afar = psycho_read(afar_reg);
620 afsr = psycho_read(afsr_reg);
621
622 /* Clear primary/secondary error status bits. */
623 error_bits = afsr &
624 (PSYCHO_CEAFSR_PPIO | PSYCHO_CEAFSR_PDRD | PSYCHO_CEAFSR_PDWR |
625 PSYCHO_CEAFSR_SPIO | PSYCHO_CEAFSR_SDRD | PSYCHO_CEAFSR_SDWR);
626 if (!error_bits)
627 return IRQ_NONE;
628 psycho_write(afsr_reg, error_bits);
629
630 /* Log the error. */
6c108f12
DM		 631 printk("%s: Correctable Error, primary error type[%s]\n",
632 pbm->name,
1da177e4
LT		 633 (((error_bits & PSYCHO_CEAFSR_PPIO) ?
634 "PIO" :
635 ((error_bits & PSYCHO_CEAFSR_PDRD) ?
636 "DMA Read" :
637 ((error_bits & PSYCHO_CEAFSR_PDWR) ?
638 "DMA Write" : "???")))));
639
640 /* XXX Use syndrome and afar to print out module string just like
641 * XXX UDB CE trap handler does... -DaveM
642 */
6c108f12 643 printk("%s: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
1da177e4 644 "UPA_MID[%02lx] was_block(%d)\n",
6c108f12 645 pbm->name,
1da177e4
LT		 646 (afsr & PSYCHO_CEAFSR_ESYND) >> 48UL,
647 (afsr & PSYCHO_CEAFSR_BMSK) >> 32UL,
648 (afsr & PSYCHO_CEAFSR_DOFF) >> 29UL,
649 (afsr & PSYCHO_CEAFSR_MID) >> 24UL,
650 ((afsr & PSYCHO_CEAFSR_BLK) ? 1 : 0));
6c108f12
DM		 651 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
652 printk("%s: CE Secondary errors [", pbm->name);
1da177e4
LT		 653 reported = 0;
654 if (afsr & PSYCHO_CEAFSR_SPIO) {
655 reported++;
656 printk("(PIO)");
657 }
658 if (afsr & PSYCHO_CEAFSR_SDRD) {
659 reported++;
660 printk("(DMA Read)");
661 }
662 if (afsr & PSYCHO_CEAFSR_SDWR) {
663 reported++;
664 printk("(DMA Write)");
665 }
666 if (!reported)
667 printk("(none)");
668 printk("]\n");
669
670 return IRQ_HANDLED;
671}
672
673/* PCI Errors. They are signalled by the PCI bus module since they
674 * are associated with a specific bus segment.
675 */
676#define PSYCHO_PCI_AFSR_A 0x2010UL
677#define PSYCHO_PCI_AFSR_B 0x4010UL
678#define PSYCHO_PCIAFSR_PMA 0x8000000000000000UL /* Primary Master Abort Error */
679#define PSYCHO_PCIAFSR_PTA 0x4000000000000000UL /* Primary Target Abort Error */
680#define PSYCHO_PCIAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
681#define PSYCHO_PCIAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
682#define PSYCHO_PCIAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort Error */
683#define PSYCHO_PCIAFSR_STA 0x0400000000000000UL /* Secondary Target Abort Error */
684#define PSYCHO_PCIAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
685#define PSYCHO_PCIAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
686#define PSYCHO_PCIAFSR_RESV1 0x00ff000000000000UL /* Reserved */
687#define PSYCHO_PCIAFSR_BMSK 0x0000ffff00000000UL /* Bytemask of failed transfer */
688#define PSYCHO_PCIAFSR_BLK 0x0000000080000000UL /* Trans was block operation */
689#define PSYCHO_PCIAFSR_RESV2 0x0000000040000000UL /* Reserved */
690#define PSYCHO_PCIAFSR_MID 0x000000003e000000UL /* MID causing the error */
691#define PSYCHO_PCIAFSR_RESV3 0x0000000001ffffffUL /* Reserved */
692#define PSYCHO_PCI_AFAR_A 0x2018UL
693#define PSYCHO_PCI_AFAR_B 0x4018UL
694
695static irqreturn_t psycho_pcierr_intr_other(struct pci_pbm_info *pbm, int is_pbm_a)
696{
697 unsigned long csr_reg, csr, csr_error_bits;
698 irqreturn_t ret = IRQ_NONE;
699 u16 stat;
700
701 if (is_pbm_a) {
702 csr_reg = pbm->controller_regs + PSYCHO_PCIA_CTRL;
703 } else {
704 csr_reg = pbm->controller_regs + PSYCHO_PCIB_CTRL;
705 }
706 csr = psycho_read(csr_reg);
707 csr_error_bits =
708 csr & (PSYCHO_PCICTRL_SBH_ERR | PSYCHO_PCICTRL_SERR);
709 if (csr_error_bits) {
710 /* Clear the errors. */
711 psycho_write(csr_reg, csr);
712
713 /* Log 'em. */
714 if (csr_error_bits & PSYCHO_PCICTRL_SBH_ERR)
715 printk("%s: PCI streaming byte hole error asserted.\n",
716 pbm->name);
717 if (csr_error_bits & PSYCHO_PCICTRL_SERR)
718 printk("%s: PCI SERR signal asserted.\n", pbm->name);
719 ret = IRQ_HANDLED;
720 }
721 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
722 if (stat & (PCI_STATUS_PARITY |
723 PCI_STATUS_SIG_TARGET_ABORT |
724 PCI_STATUS_REC_TARGET_ABORT |
725 PCI_STATUS_REC_MASTER_ABORT |
726 PCI_STATUS_SIG_SYSTEM_ERROR)) {
727 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
728 pbm->name, stat);
729 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
730 ret = IRQ_HANDLED;
731 }
732 return ret;
733}
734
6d24c8dc 735static irqreturn_t psycho_pcierr_intr(int irq, void *dev_id)
1da177e4
LT		 736{
737 struct pci_pbm_info *pbm = dev_id;
738 struct pci_controller_info *p = pbm->parent;
739 unsigned long afsr_reg, afar_reg;
740 unsigned long afsr, afar, error_bits;
741 int is_pbm_a, reported;
742
743 is_pbm_a = (pbm == &pbm->parent->pbm_A);
744 if (is_pbm_a) {
745 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_A;
746 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_A;
747 } else {
748 afsr_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFSR_B;
749 afar_reg = p->pbm_A.controller_regs + PSYCHO_PCI_AFAR_B;
750 }
751
752 /* Latch error status. */
753 afar = psycho_read(afar_reg);
754 afsr = psycho_read(afsr_reg);
755
756 /* Clear primary/secondary error status bits. */
757 error_bits = afsr &
758 (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_PTA |
759 PSYCHO_PCIAFSR_PRTRY | PSYCHO_PCIAFSR_PPERR |
760 PSYCHO_PCIAFSR_SMA | PSYCHO_PCIAFSR_STA |
761 PSYCHO_PCIAFSR_SRTRY | PSYCHO_PCIAFSR_SPERR);
762 if (!error_bits)
763 return psycho_pcierr_intr_other(pbm, is_pbm_a);
764 psycho_write(afsr_reg, error_bits);
765
766 /* Log the error. */
6c108f12
DM		 767 printk("%s: PCI Error, primary error type[%s]\n",
768 pbm->name,
1da177e4
LT		 769 (((error_bits & PSYCHO_PCIAFSR_PMA) ?
770 "Master Abort" :
771 ((error_bits & PSYCHO_PCIAFSR_PTA) ?
772 "Target Abort" :
773 ((error_bits & PSYCHO_PCIAFSR_PRTRY) ?
774 "Excessive Retries" :
775 ((error_bits & PSYCHO_PCIAFSR_PPERR) ?
776 "Parity Error" : "???"))))));
6c108f12
DM		 777 printk("%s: bytemask[%04lx] UPA_MID[%02lx] was_block(%d)\n",
778 pbm->name,
1da177e4
LT		 779 (afsr & PSYCHO_PCIAFSR_BMSK) >> 32UL,
780 (afsr & PSYCHO_PCIAFSR_MID) >> 25UL,
781 (afsr & PSYCHO_PCIAFSR_BLK) ? 1 : 0);
6c108f12
DM		 782 printk("%s: PCI AFAR [%016lx]\n", pbm->name, afar);
783 printk("%s: PCI Secondary errors [", pbm->name);
1da177e4
LT		 784 reported = 0;
785 if (afsr & PSYCHO_PCIAFSR_SMA) {
786 reported++;
787 printk("(Master Abort)");
788 }
789 if (afsr & PSYCHO_PCIAFSR_STA) {
790 reported++;
791 printk("(Target Abort)");
792 }
793 if (afsr & PSYCHO_PCIAFSR_SRTRY) {
794 reported++;
795 printk("(Excessive Retries)");
796 }
797 if (afsr & PSYCHO_PCIAFSR_SPERR) {
798 reported++;
799 printk("(Parity Error)");
800 }
801 if (!reported)
802 printk("(none)");
803 printk("]\n");
804
805 /* For the error types shown, scan PBM's PCI bus for devices
806 * which have logged that error type.
807 */
808
809 /* If we see a Target Abort, this could be the result of an
810 * IOMMU translation error of some sort. It is extremely
811 * useful to log this information as usually it indicates
812 * a bug in the IOMMU support code or a PCI device driver.
813 */
814 if (error_bits & (PSYCHO_PCIAFSR_PTA | PSYCHO_PCIAFSR_STA)) {
34768bc8 815 psycho_check_iommu_error(pbm, afsr, afar, PCI_ERR);
6c108f12 816 pci_scan_for_target_abort(pbm, pbm->pci_bus);
1da177e4
LT		 817 }
818 if (error_bits & (PSYCHO_PCIAFSR_PMA | PSYCHO_PCIAFSR_SMA))
6c108f12 819 pci_scan_for_master_abort(pbm, pbm->pci_bus);
1da177e4
LT		 820
821 /* For excessive retries, PSYCHO/PBM will abort the device
822 * and there is no way to specifically check for excessive
823 * retries in the config space status registers. So what
824 * we hope is that we'll catch it via the master/target
825 * abort events.
826 */
827
828 if (error_bits & (PSYCHO_PCIAFSR_PPERR | PSYCHO_PCIAFSR_SPERR))
6c108f12 829 pci_scan_for_parity_error(pbm, pbm->pci_bus);
1da177e4
LT		 830
831 return IRQ_HANDLED;
832}
833
834/* XXX What about PowerFail/PowerManagement??? -DaveM */
835#define PSYCHO_ECC_CTRL 0x0020
836#define PSYCHO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
837#define PSYCHO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
838#define PSYCHO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
34768bc8 839static void psycho_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 840{
2b1e5978 841 struct of_device *op = of_find_device_by_node(pbm->prom_node);
34768bc8 842 unsigned long base = pbm->controller_regs;
1da177e4
LT		 843 u64 tmp;
844
2b1e5978
DM		 845 if (!op)
846 return;
1da177e4 847
2b1e5978 848 /* Psycho interrupt property order is:
34768bc8 849 * 0: PCIERR INO for this PBM
2b1e5978
DM		 850 * 1: UE ERR
851 * 2: CE ERR
852 * 3: POWER FAIL
853 * 4: SPARE HARDWARE
34768bc8 854 * 5: POWER MANAGEMENT
2b1e5978 855 */
1da177e4 856
2b1e5978
DM		 857 if (op->num_irqs < 6)
858 return;
1da177e4 859
34768bc8
DM		 860 request_irq(op->irqs[1], psycho_ue_intr, 0,
861 "PSYCHO_UE", pbm);
862 request_irq(op->irqs[2], psycho_ce_intr, 0,
863 "PSYCHO_CE", pbm);
864 request_irq(op->irqs[0], psycho_pcierr_intr, 0,
865 "PSYCHO_PCIERR", pbm);
1da177e4
LT		 866
867 /* Enable UE and CE interrupts for controller. */
868 psycho_write(base + PSYCHO_ECC_CTRL,
869 (PSYCHO_ECCCTRL_EE |
870 PSYCHO_ECCCTRL_UE |
871 PSYCHO_ECCCTRL_CE));
872
873 /* Enable PCI Error interrupts and clear error
874 * bits for each PBM.
875 */
876 tmp = psycho_read(base + PSYCHO_PCIA_CTRL);
877 tmp |= (PSYCHO_PCICTRL_SERR |
878 PSYCHO_PCICTRL_SBH_ERR |
879 PSYCHO_PCICTRL_EEN);
880 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
881 psycho_write(base + PSYCHO_PCIA_CTRL, tmp);
882
883 tmp = psycho_read(base + PSYCHO_PCIB_CTRL);
884 tmp |= (PSYCHO_PCICTRL_SERR |
885 PSYCHO_PCICTRL_SBH_ERR |
886 PSYCHO_PCICTRL_EEN);
887 tmp &= ~(PSYCHO_PCICTRL_SBH_INT);
888 psycho_write(base + PSYCHO_PCIB_CTRL, tmp);
889}
890
891/* PSYCHO boot time probing and initialization. */
085ae41f 892static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 893{
894 u8 *addr;
895
896 /* Set cache-line size to 64 bytes, this is actually
897 * a nop but I do it for completeness.
898 */
899 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
900 0, PCI_CACHE_LINE_SIZE);
901 pci_config_write8(addr, 64 / sizeof(u32));
902
903 /* Set PBM latency timer to 64 PCI clocks. */
904 addr = psycho_pci_config_mkaddr(pbm, pbm->pci_first_busno,
905 0, PCI_LATENCY_TIMER);
906 pci_config_write8(addr, 64);
907}
908
34768bc8 909static void psycho_scan_bus(struct pci_pbm_info *pbm)
1da177e4 910{
34768bc8
DM		 911 pbm_config_busmastering(pbm);
912 pbm->is_66mhz_capable = 0;
a2fb23af 913 pbm->pci_bus = pci_scan_one_pbm(pbm);
1da177e4
LT		 914
915 /* After the PCI bus scan is complete, we can register
916 * the error interrupt handlers.
917 */
34768bc8 918 psycho_register_error_handlers(pbm);
1da177e4
LT		 919}
920
085ae41f 921static void psycho_iommu_init(struct pci_controller_info *p)
1da177e4 922{
16ce82d8 923 struct iommu *iommu = p->pbm_A.iommu;
51e85136 924 unsigned long i;
1da177e4
LT		 925 u64 control;
926
1da177e4
LT		 927 /* Register addresses. */
928 iommu->iommu_control = p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL;
929 iommu->iommu_tsbbase = p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE;
930 iommu->iommu_flush = p->pbm_A.controller_regs + PSYCHO_IOMMU_FLUSH;
931 /* PSYCHO's IOMMU lacks ctx flushing. */
932 iommu->iommu_ctxflush = 0;
933
934 /* We use the main control register of PSYCHO as the write
935 * completion register.
936 */
937 iommu->write_complete_reg = p->pbm_A.controller_regs + PSYCHO_CONTROL;
938
939 /*
940 * Invalidate TLB Entries.
941 */
942 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
943 control |= PSYCHO_IOMMU_CTRL_DENAB;
944 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
945 for(i = 0; i < 16; i++) {
946 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TAG + (i * 8UL), 0);
947 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_DATA + (i * 8UL), 0);
948 }
949
950 /* Leave diag mode enabled for full-flushing done
951 * in pci_iommu.c
952 */
51e85136 953 pci_iommu_table_init(iommu, IO_TSB_SIZE, 0xc0000000, 0xffffffff);
1da177e4 954
51e85136
DM		 955 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_TSBBASE,
956 __pa(iommu->page_table));
1da177e4
LT		 957
958 control = psycho_read(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL);
959 control &= ~(PSYCHO_IOMMU_CTRL_TSBSZ | PSYCHO_IOMMU_CTRL_TBWSZ);
960 control |= (PSYCHO_IOMMU_TSBSZ_128K | PSYCHO_IOMMU_CTRL_ENAB);
961 psycho_write(p->pbm_A.controller_regs + PSYCHO_IOMMU_CONTROL, control);
962
963 /* If necessary, hook us up for starfire IRQ translations. */
51e85136 964 if (this_is_starfire)
286bbe87 965 starfire_hookup(p->pbm_A.portid);
1da177e4
LT		 966}
967
968#define PSYCHO_IRQ_RETRY 0x1a00UL
969#define PSYCHO_PCIA_DIAG 0x2020UL
970#define PSYCHO_PCIB_DIAG 0x4020UL
971#define PSYCHO_PCIDIAG_RESV 0xffffffffffffff80UL /* Reserved */
972#define PSYCHO_PCIDIAG_DRETRY 0x0000000000000040UL /* Disable retry limit */
973#define PSYCHO_PCIDIAG_DISYNC 0x0000000000000020UL /* Disable DMA wr / irq sync */
974#define PSYCHO_PCIDIAG_DDWSYNC 0x0000000000000010UL /* Disable DMA wr / PIO rd sync */
975#define PSYCHO_PCIDIAG_IDDPAR 0x0000000000000008UL /* Invert DMA data parity */
976#define PSYCHO_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO data parity */
977#define PSYCHO_PCIDIAG_IPAPAR 0x0000000000000002UL /* Invert PIO address parity */
978#define PSYCHO_PCIDIAG_LPBACK 0x0000000000000001UL /* Enable loopback mode */
979
980static void psycho_controller_hwinit(struct pci_controller_info *p)
981{
982 u64 tmp;
983
864ae180 984 psycho_write(p->pbm_A.controller_regs + PSYCHO_IRQ_RETRY, 5);
1da177e4
LT		 985
986 /* Enable arbiter for all PCI slots. */
987 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL);
988 tmp |= PSYCHO_PCICTRL_AEN;
989 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_CTRL, tmp);
990
991 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL);
992 tmp |= PSYCHO_PCICTRL_AEN;
993 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_CTRL, tmp);
994
995 /* Disable DMA write / PIO read synchronization on
996 * both PCI bus segments.
997 * [ U2P Erratum 1243770, STP2223BGA data sheet ]
998 */
999 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG);
1000 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1001 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIA_DIAG, tmp);
1002
1003 tmp = psycho_read(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG);
1004 tmp |= PSYCHO_PCIDIAG_DDWSYNC;
1005 psycho_write(p->pbm_A.controller_regs + PSYCHO_PCIB_DIAG, tmp);
1006}
1007
1da177e4
LT		 1008static void psycho_pbm_strbuf_init(struct pci_controller_info *p,
1009 struct pci_pbm_info *pbm,
1010 int is_pbm_a)
1011{
1012 unsigned long base = pbm->controller_regs;
1013 u64 control;
1014
1015 if (is_pbm_a) {
1016 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_A;
1017 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_A;
1018 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_A;
1019 } else {
1020 pbm->stc.strbuf_control = base + PSYCHO_STRBUF_CONTROL_B;
1021 pbm->stc.strbuf_pflush = base + PSYCHO_STRBUF_FLUSH_B;
1022 pbm->stc.strbuf_fsync = base + PSYCHO_STRBUF_FSYNC_B;
1023 }
1024 /* PSYCHO's streaming buffer lacks ctx flushing. */
1025 pbm->stc.strbuf_ctxflush = 0;
1026 pbm->stc.strbuf_ctxmatch_base = 0;
1027
1028 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1029 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1030 + 63UL)
1031 & ~63UL);
1032 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1033 __pa(pbm->stc.strbuf_flushflag);
1034
1035 /* Enable the streaming buffer. We have to be careful
1036 * just in case OBP left it with LRU locking enabled.
1037 *
1038 * It is possible to control if PBM will be rerun on
1039 * line misses. Currently I just retain whatever setting
1040 * OBP left us with. All checks so far show it having
1041 * a value of zero.
1042 */
1043#undef PSYCHO_STRBUF_RERUN_ENABLE
1044#undef PSYCHO_STRBUF_RERUN_DISABLE
1045 control = psycho_read(pbm->stc.strbuf_control);
1046 control |= PSYCHO_STRBUF_CTRL_ENAB;
1047 control &= ~(PSYCHO_STRBUF_CTRL_LENAB | PSYCHO_STRBUF_CTRL_LPTR);
1048#ifdef PSYCHO_STRBUF_RERUN_ENABLE
1049 control &= ~(PSYCHO_STRBUF_CTRL_RRDIS);
1050#else
1051#ifdef PSYCHO_STRBUF_RERUN_DISABLE
1052 control |= PSYCHO_STRBUF_CTRL_RRDIS;
1053#endif
1054#endif
1055 psycho_write(pbm->stc.strbuf_control, control);
1056
1057 pbm->stc.strbuf_enabled = 1;
1058}
1059
1060#define PSYCHO_IOSPACE_A 0x002000000UL
1061#define PSYCHO_IOSPACE_B 0x002010000UL
1062#define PSYCHO_IOSPACE_SIZE 0x00000ffffUL
1063#define PSYCHO_MEMSPACE_A 0x100000000UL
1064#define PSYCHO_MEMSPACE_B 0x180000000UL
1065#define PSYCHO_MEMSPACE_SIZE 0x07fffffffUL
1066
1067static void psycho_pbm_init(struct pci_controller_info *p,
e87dc350 1068 struct device_node *dp, int is_pbm_a)
1da177e4 1069{
e87dc350 1070 struct property *prop;
1da177e4 1071 struct pci_pbm_info *pbm;
1da177e4 1072
0bba2dd8 1073 if (is_pbm_a)
1da177e4 1074 pbm = &p->pbm_A;
0bba2dd8 1075 else
1da177e4 1076 pbm = &p->pbm_B;
1da177e4 1077
34768bc8
DM		 1078 pbm->next = pci_pbm_root;
1079 pci_pbm_root = pbm;
1080
1081 pbm->scan_bus = psycho_scan_bus;
f1cd8de2 1082 pbm->pci_ops = &psycho_ops;
34768bc8 1083
6c108f12
DM		 1084 pbm->index = pci_num_pbms++;
1085
1da177e4 1086 pbm->chip_type = PBM_CHIP_TYPE_PSYCHO;
e87dc350
DM		 1087 pbm->chip_version = 0;
1088 prop = of_find_property(dp, "version#", NULL);
1089 if (prop)
1090 pbm->chip_version = *(int *) prop->value;
1091 pbm->chip_revision = 0;
1092 prop = of_find_property(dp, "module-revision#", NULL);
1093 if (prop)
1094 pbm->chip_revision = *(int *) prop->value;
1da177e4 1095
1da177e4 1096 pbm->parent = p;
e87dc350
DM		 1097 pbm->prom_node = dp;
1098 pbm->name = dp->full_name;
1099
1100 printk("%s: PSYCHO PCI Bus Module ver[%x:%x]\n",
1101 pbm->name,
1102 pbm->chip_version, pbm->chip_revision);
1103
0f3e2504
DM		 1104 pci_determine_mem_io_space(pbm);
1105
cfa0652c 1106 pci_get_pbm_props(pbm);
1da177e4
LT		 1107
1108 psycho_pbm_strbuf_init(p, pbm, is_pbm_a);
1109}
1110
1111#define PSYCHO_CONFIGSPACE 0x001000000UL
1112
e87dc350 1113void psycho_init(struct device_node *dp, char *model_name)
1da177e4 1114{
e87dc350 1115 struct linux_prom64_registers *pr_regs;
1da177e4 1116 struct pci_controller_info *p;
34768bc8 1117 struct pci_pbm_info *pbm;
16ce82d8 1118 struct iommu *iommu;
e87dc350 1119 struct property *prop;
1da177e4 1120 u32 upa_portid;
e87dc350 1121 int is_pbm_a;
1da177e4 1122
e87dc350
DM		 1123 upa_portid = 0xff;
1124 prop = of_find_property(dp, "upa-portid", NULL);
1125 if (prop)
1126 upa_portid = *(u32 *) prop->value;
1da177e4 1127
34768bc8
DM		 1128 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1129 struct pci_controller_info *p = pbm->parent;
1130
1da177e4 1131 if (p->pbm_A.portid == upa_portid) {
e87dc350
DM		 1132 is_pbm_a = (p->pbm_A.prom_node == NULL);
1133 psycho_pbm_init(p, dp, is_pbm_a);
1da177e4
LT		 1134 return;
1135 }
1136 }
1137
9132983a 1138 p = kzalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
1da177e4
LT		 1139 if (!p) {
1140 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1141 prom_halt();
1142 }
16ce82d8 1143 iommu = kzalloc(sizeof(struct iommu), GFP_ATOMIC);
1da177e4
LT		 1144 if (!iommu) {
1145 prom_printf("PSYCHO: Fatal memory allocation error.\n");
1146 prom_halt();
1147 }
1da177e4
LT		 1148 p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1149
1da177e4
LT		 1150 p->pbm_A.portid = upa_portid;
1151 p->pbm_B.portid = upa_portid;
1da177e4 1152
e87dc350
DM		 1153 prop = of_find_property(dp, "reg", NULL);
1154 pr_regs = prop->value;
1da177e4
LT		 1155
1156 p->pbm_A.controller_regs = pr_regs[2].phys_addr;
1157 p->pbm_B.controller_regs = pr_regs[2].phys_addr;
1da177e4
LT		 1158
1159 p->pbm_A.config_space = p->pbm_B.config_space =
1160 (pr_regs[2].phys_addr + PSYCHO_CONFIGSPACE);
1da177e4
LT		 1161
1162 /*
1163 * Psycho's PCI MEM space is mapped to a 2GB aligned area, so
1164 * we need to adjust our MEM space mask.
1165 */
1166 pci_memspace_mask = 0x7fffffffUL;
1167
1168 psycho_controller_hwinit(p);
1169
1170 psycho_iommu_init(p);
1171
1172 is_pbm_a = ((pr_regs[0].phys_addr & 0x6000) == 0x2000);
e87dc350 1173 psycho_pbm_init(p, dp, is_pbm_a);
1da177e4 1174}
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