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1da177e4 LT |
1 | /* $Id: pci_schizo.c,v 1.24 2002/01/23 11:27:32 davem Exp $ |
2 | * pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support. | |
3 | * | |
4 | * Copyright (C) 2001, 2002, 2003 David S. Miller (davem@redhat.com) | |
5 | */ | |
6 | ||
7 | #include <linux/kernel.h> | |
8 | #include <linux/types.h> | |
9 | #include <linux/pci.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/slab.h> | |
12 | #include <linux/interrupt.h> | |
13 | ||
14 | #include <asm/pbm.h> | |
15 | #include <asm/iommu.h> | |
16 | #include <asm/irq.h> | |
17 | #include <asm/upa.h> | |
bb6743f4 | 18 | #include <asm/pstate.h> |
1da177e4 LT |
19 | |
20 | #include "pci_impl.h" | |
21 | #include "iommu_common.h" | |
22 | ||
23 | /* All SCHIZO registers are 64-bits. The following accessor | |
24 | * routines are how they are accessed. The REG parameter | |
25 | * is a physical address. | |
26 | */ | |
27 | #define schizo_read(__reg) \ | |
28 | ({ u64 __ret; \ | |
29 | __asm__ __volatile__("ldxa [%1] %2, %0" \ | |
30 | : "=r" (__ret) \ | |
31 | : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \ | |
32 | : "memory"); \ | |
33 | __ret; \ | |
34 | }) | |
35 | #define schizo_write(__reg, __val) \ | |
36 | __asm__ __volatile__("stxa %0, [%1] %2" \ | |
37 | : /* no outputs */ \ | |
38 | : "r" (__val), "r" (__reg), \ | |
39 | "i" (ASI_PHYS_BYPASS_EC_E) \ | |
40 | : "memory") | |
41 | ||
42 | /* This is a convention that at least Excalibur and Merlin | |
43 | * follow. I suppose the SCHIZO used in Starcat and friends | |
44 | * will do similar. | |
45 | * | |
46 | * The only way I could see this changing is if the newlink | |
47 | * block requires more space in Schizo's address space than | |
48 | * they predicted, thus requiring an address space reorg when | |
49 | * the newer Schizo is taped out. | |
50 | */ | |
51 | ||
52 | /* Streaming buffer control register. */ | |
53 | #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */ | |
54 | #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */ | |
55 | #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */ | |
56 | #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */ | |
57 | #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */ | |
58 | ||
59 | /* IOMMU control register. */ | |
60 | #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */ | |
61 | #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */ | |
62 | #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */ | |
63 | #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */ | |
64 | #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */ | |
65 | #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */ | |
66 | #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */ | |
67 | #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */ | |
68 | #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */ | |
69 | #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */ | |
70 | #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */ | |
71 | #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */ | |
72 | #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */ | |
73 | #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */ | |
74 | #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */ | |
75 | #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */ | |
76 | #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */ | |
77 | #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */ | |
78 | ||
79 | /* Schizo config space address format is nearly identical to | |
80 | * that of PSYCHO: | |
81 | * | |
82 | * 32 24 23 16 15 11 10 8 7 2 1 0 | |
83 | * --------------------------------------------------------- | |
84 | * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 | | |
85 | * --------------------------------------------------------- | |
86 | */ | |
87 | #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space) | |
88 | #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ | |
89 | (((unsigned long)(BUS) << 16) | \ | |
90 | ((unsigned long)(DEVFN) << 8) | \ | |
91 | ((unsigned long)(REG))) | |
92 | ||
93 | static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm, | |
94 | unsigned char bus, | |
95 | unsigned int devfn, | |
96 | int where) | |
97 | { | |
98 | if (!pbm) | |
99 | return NULL; | |
100 | bus -= pbm->pci_first_busno; | |
101 | return (void *) | |
102 | (SCHIZO_CONFIG_BASE(pbm) | | |
103 | SCHIZO_CONFIG_ENCODE(bus, devfn, where)); | |
104 | } | |
105 | ||
106 | /* Just make sure the bus number is in range. */ | |
107 | static int schizo_out_of_range(struct pci_pbm_info *pbm, | |
108 | unsigned char bus, | |
109 | unsigned char devfn) | |
110 | { | |
111 | if (bus < pbm->pci_first_busno || | |
112 | bus > pbm->pci_last_busno) | |
113 | return 1; | |
114 | return 0; | |
115 | } | |
116 | ||
117 | /* SCHIZO PCI configuration space accessors. */ | |
118 | ||
119 | static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
120 | int where, int size, u32 *value) | |
121 | { | |
122 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
123 | unsigned char bus = bus_dev->number; | |
124 | u32 *addr; | |
125 | u16 tmp16; | |
126 | u8 tmp8; | |
127 | ||
128 | switch (size) { | |
129 | case 1: | |
130 | *value = 0xff; | |
131 | break; | |
132 | case 2: | |
133 | *value = 0xffff; | |
134 | break; | |
135 | case 4: | |
136 | *value = 0xffffffff; | |
137 | break; | |
138 | } | |
139 | ||
140 | addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where); | |
141 | if (!addr) | |
142 | return PCIBIOS_SUCCESSFUL; | |
143 | ||
144 | if (schizo_out_of_range(pbm, bus, devfn)) | |
145 | return PCIBIOS_SUCCESSFUL; | |
146 | switch (size) { | |
147 | case 1: | |
148 | pci_config_read8((u8 *)addr, &tmp8); | |
149 | *value = tmp8; | |
150 | break; | |
151 | ||
152 | case 2: | |
153 | if (where & 0x01) { | |
154 | printk("pci_read_config_word: misaligned reg [%x]\n", | |
155 | where); | |
156 | return PCIBIOS_SUCCESSFUL; | |
157 | } | |
158 | pci_config_read16((u16 *)addr, &tmp16); | |
159 | *value = tmp16; | |
160 | break; | |
161 | ||
162 | case 4: | |
163 | if (where & 0x03) { | |
164 | printk("pci_read_config_dword: misaligned reg [%x]\n", | |
165 | where); | |
166 | return PCIBIOS_SUCCESSFUL; | |
167 | } | |
168 | pci_config_read32(addr, value); | |
169 | break; | |
170 | } | |
171 | return PCIBIOS_SUCCESSFUL; | |
172 | } | |
173 | ||
174 | static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn, | |
175 | int where, int size, u32 value) | |
176 | { | |
177 | struct pci_pbm_info *pbm = bus_dev->sysdata; | |
178 | unsigned char bus = bus_dev->number; | |
179 | u32 *addr; | |
180 | ||
181 | addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where); | |
182 | if (!addr) | |
183 | return PCIBIOS_SUCCESSFUL; | |
184 | ||
185 | if (schizo_out_of_range(pbm, bus, devfn)) | |
186 | return PCIBIOS_SUCCESSFUL; | |
187 | ||
188 | switch (size) { | |
189 | case 1: | |
190 | pci_config_write8((u8 *)addr, value); | |
191 | break; | |
192 | ||
193 | case 2: | |
194 | if (where & 0x01) { | |
195 | printk("pci_write_config_word: misaligned reg [%x]\n", | |
196 | where); | |
197 | return PCIBIOS_SUCCESSFUL; | |
198 | } | |
199 | pci_config_write16((u16 *)addr, value); | |
200 | break; | |
201 | ||
202 | case 4: | |
203 | if (where & 0x03) { | |
204 | printk("pci_write_config_dword: misaligned reg [%x]\n", | |
205 | where); | |
206 | return PCIBIOS_SUCCESSFUL; | |
207 | } | |
208 | ||
209 | pci_config_write32(addr, value); | |
210 | } | |
211 | return PCIBIOS_SUCCESSFUL; | |
212 | } | |
213 | ||
214 | static struct pci_ops schizo_ops = { | |
215 | .read = schizo_read_pci_cfg, | |
216 | .write = schizo_write_pci_cfg, | |
217 | }; | |
218 | ||
219 | /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the | |
220 | * imap/iclr registers are per-PBM. | |
221 | */ | |
222 | #define SCHIZO_IMAP_BASE 0x1000UL | |
223 | #define SCHIZO_ICLR_BASE 0x1400UL | |
224 | ||
225 | static unsigned long schizo_imap_offset(unsigned long ino) | |
226 | { | |
227 | return SCHIZO_IMAP_BASE + (ino * 8UL); | |
228 | } | |
229 | ||
230 | static unsigned long schizo_iclr_offset(unsigned long ino) | |
231 | { | |
232 | return SCHIZO_ICLR_BASE + (ino * 8UL); | |
233 | } | |
234 | ||
235 | /* PCI SCHIZO INO number to Sparc PIL level. This table only matters for | |
236 | * INOs which will not have an associated PCI device struct, ie. onboard | |
237 | * EBUS devices and PCI controller internal error interrupts. | |
238 | */ | |
239 | static unsigned char schizo_pil_table[] = { | |
240 | /*0x00*/0, 0, 0, 0, /* PCI slot 0 Int A, B, C, D */ | |
241 | /*0x04*/0, 0, 0, 0, /* PCI slot 1 Int A, B, C, D */ | |
242 | /*0x08*/0, 0, 0, 0, /* PCI slot 2 Int A, B, C, D */ | |
243 | /*0x0c*/0, 0, 0, 0, /* PCI slot 3 Int A, B, C, D */ | |
244 | /*0x10*/0, 0, 0, 0, /* PCI slot 4 Int A, B, C, D */ | |
245 | /*0x14*/0, 0, 0, 0, /* PCI slot 5 Int A, B, C, D */ | |
246 | /*0x18*/4, /* SCSI */ | |
247 | /*0x19*/4, /* second SCSI */ | |
248 | /*0x1a*/0, /* UNKNOWN */ | |
249 | /*0x1b*/0, /* UNKNOWN */ | |
250 | /*0x1c*/8, /* Parallel */ | |
251 | /*0x1d*/5, /* Ethernet */ | |
252 | /*0x1e*/8, /* Firewire-1394 */ | |
253 | /*0x1f*/9, /* USB */ | |
254 | /*0x20*/13, /* Audio Record */ | |
255 | /*0x21*/14, /* Audio Playback */ | |
256 | /*0x22*/12, /* Serial */ | |
257 | /*0x23*/4, /* EBUS I2C */ | |
258 | /*0x24*/10, /* RTC Clock */ | |
259 | /*0x25*/11, /* Floppy */ | |
260 | /*0x26*/0, /* UNKNOWN */ | |
261 | /*0x27*/0, /* UNKNOWN */ | |
262 | /*0x28*/0, /* UNKNOWN */ | |
263 | /*0x29*/0, /* UNKNOWN */ | |
264 | /*0x2a*/10, /* UPA 1 */ | |
265 | /*0x2b*/10, /* UPA 2 */ | |
266 | /*0x2c*/0, /* UNKNOWN */ | |
267 | /*0x2d*/0, /* UNKNOWN */ | |
268 | /*0x2e*/0, /* UNKNOWN */ | |
269 | /*0x2f*/0, /* UNKNOWN */ | |
270 | /*0x30*/15, /* Uncorrectable ECC */ | |
271 | /*0x31*/15, /* Correctable ECC */ | |
272 | /*0x32*/15, /* PCI Bus A Error */ | |
273 | /*0x33*/15, /* PCI Bus B Error */ | |
274 | /*0x34*/15, /* Safari Bus Error */ | |
275 | /*0x35*/0, /* Reserved */ | |
276 | /*0x36*/0, /* Reserved */ | |
277 | /*0x37*/0, /* Reserved */ | |
278 | /*0x38*/0, /* Reserved for NewLink */ | |
279 | /*0x39*/0, /* Reserved for NewLink */ | |
280 | /*0x3a*/0, /* Reserved for NewLink */ | |
281 | /*0x3b*/0, /* Reserved for NewLink */ | |
282 | /*0x3c*/0, /* Reserved for NewLink */ | |
283 | /*0x3d*/0, /* Reserved for NewLink */ | |
284 | /*0x3e*/0, /* Reserved for NewLink */ | |
285 | /*0x3f*/0, /* Reserved for NewLink */ | |
286 | }; | |
287 | ||
085ae41f | 288 | static int schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino) |
1da177e4 LT |
289 | { |
290 | int ret; | |
291 | ||
292 | if (pdev && | |
293 | pdev->vendor == PCI_VENDOR_ID_SUN && | |
294 | pdev->device == PCI_DEVICE_ID_SUN_RIO_USB) | |
295 | return 9; | |
296 | ||
297 | ret = schizo_pil_table[ino]; | |
298 | if (ret == 0 && pdev == NULL) { | |
299 | ret = 4; | |
300 | } else if (ret == 0) { | |
301 | switch ((pdev->class >> 16) & 0xff) { | |
302 | case PCI_BASE_CLASS_STORAGE: | |
303 | ret = 4; | |
304 | break; | |
305 | ||
306 | case PCI_BASE_CLASS_NETWORK: | |
307 | ret = 6; | |
308 | break; | |
309 | ||
310 | case PCI_BASE_CLASS_DISPLAY: | |
311 | ret = 9; | |
312 | break; | |
313 | ||
314 | case PCI_BASE_CLASS_MULTIMEDIA: | |
315 | case PCI_BASE_CLASS_MEMORY: | |
316 | case PCI_BASE_CLASS_BRIDGE: | |
317 | case PCI_BASE_CLASS_SERIAL: | |
318 | ret = 10; | |
319 | break; | |
320 | ||
321 | default: | |
322 | ret = 4; | |
323 | break; | |
324 | }; | |
325 | } | |
326 | ||
327 | return ret; | |
328 | } | |
329 | ||
bb6743f4 DM |
330 | static void tomatillo_wsync_handler(struct ino_bucket *bucket, void *_arg1, void *_arg2) |
331 | { | |
332 | unsigned long sync_reg = (unsigned long) _arg2; | |
52f26deb | 333 | u64 mask = 1UL << (__irq_ino(__irq(bucket)) & IMAP_INO); |
bb6743f4 DM |
334 | u64 val; |
335 | int limit; | |
336 | ||
337 | schizo_write(sync_reg, mask); | |
338 | ||
339 | limit = 100000; | |
340 | val = 0; | |
341 | while (--limit) { | |
342 | val = schizo_read(sync_reg); | |
343 | if (!(val & mask)) | |
344 | break; | |
345 | } | |
346 | if (limit <= 0) { | |
347 | printk("tomatillo_wsync_handler: DMA won't sync [%lx:%lx]\n", | |
348 | val, mask); | |
349 | } | |
350 | ||
351 | if (_arg1) { | |
352 | static unsigned char cacheline[64] | |
353 | __attribute__ ((aligned (64))); | |
354 | ||
355 | __asm__ __volatile__("rd %%fprs, %0\n\t" | |
356 | "or %0, %4, %1\n\t" | |
357 | "wr %1, 0x0, %%fprs\n\t" | |
358 | "stda %%f0, [%5] %6\n\t" | |
359 | "wr %0, 0x0, %%fprs\n\t" | |
360 | "membar #Sync" | |
361 | : "=&r" (mask), "=&r" (val) | |
362 | : "0" (mask), "1" (val), | |
363 | "i" (FPRS_FEF), "r" (&cacheline[0]), | |
364 | "i" (ASI_BLK_COMMIT_P)); | |
365 | } | |
366 | } | |
367 | ||
1da177e4 LT |
368 | static unsigned int schizo_irq_build(struct pci_pbm_info *pbm, |
369 | struct pci_dev *pdev, | |
370 | unsigned int ino) | |
371 | { | |
372 | struct ino_bucket *bucket; | |
373 | unsigned long imap, iclr; | |
374 | unsigned long imap_off, iclr_off; | |
375 | int pil, ign_fixup; | |
376 | ||
377 | ino &= PCI_IRQ_INO; | |
378 | imap_off = schizo_imap_offset(ino); | |
379 | ||
380 | /* Now build the IRQ bucket. */ | |
381 | pil = schizo_ino_to_pil(pdev, ino); | |
382 | ||
383 | if (PIL_RESERVED(pil)) | |
384 | BUG(); | |
385 | ||
386 | imap = pbm->pbm_regs + imap_off; | |
387 | imap += 4; | |
388 | ||
389 | iclr_off = schizo_iclr_offset(ino); | |
390 | iclr = pbm->pbm_regs + iclr_off; | |
391 | iclr += 4; | |
392 | ||
393 | /* On Schizo, no inofixup occurs. This is because each | |
394 | * INO has it's own IMAP register. On Psycho and Sabre | |
395 | * there is only one IMAP register for each PCI slot even | |
396 | * though four different INOs can be generated by each | |
397 | * PCI slot. | |
398 | * | |
399 | * But, for JBUS variants (essentially, Tomatillo), we have | |
400 | * to fixup the lowest bit of the interrupt group number. | |
401 | */ | |
402 | ign_fixup = 0; | |
403 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { | |
404 | if (pbm->portid & 1) | |
405 | ign_fixup = (1 << 6); | |
406 | } | |
407 | ||
408 | bucket = __bucket(build_irq(pil, ign_fixup, iclr, imap)); | |
409 | bucket->flags |= IBF_PCI; | |
410 | ||
bb6743f4 DM |
411 | if (pdev && pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { |
412 | struct irq_desc *p = bucket->irq_info; | |
413 | ||
414 | p->pre_handler = tomatillo_wsync_handler; | |
415 | p->pre_handler_arg1 = ((pbm->chip_version <= 4) ? | |
416 | (void *) 1 : (void *) 0); | |
417 | p->pre_handler_arg2 = (void *) pbm->sync_reg; | |
418 | } | |
419 | ||
1da177e4 LT |
420 | return __irq(bucket); |
421 | } | |
422 | ||
423 | /* SCHIZO error handling support. */ | |
424 | enum schizo_error_type { | |
425 | UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR | |
426 | }; | |
427 | ||
428 | static DEFINE_SPINLOCK(stc_buf_lock); | |
429 | static unsigned long stc_error_buf[128]; | |
430 | static unsigned long stc_tag_buf[16]; | |
431 | static unsigned long stc_line_buf[16]; | |
432 | ||
433 | #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */ | |
434 | #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */ | |
435 | #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */ | |
436 | #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */ | |
437 | #define SCHIZO_SERR_INO 0x34 /* Safari interface error */ | |
438 | ||
439 | struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino) | |
440 | { | |
441 | ino &= IMAP_INO; | |
442 | if (p->pbm_A.ino_bitmap & (1UL << ino)) | |
443 | return &p->pbm_A; | |
444 | if (p->pbm_B.ino_bitmap & (1UL << ino)) | |
445 | return &p->pbm_B; | |
446 | ||
447 | printk("PCI%d: No ino_bitmap entry for ino[%x], bitmaps " | |
448 | "PBM_A[%016lx] PBM_B[%016lx]", | |
449 | p->index, ino, | |
450 | p->pbm_A.ino_bitmap, | |
451 | p->pbm_B.ino_bitmap); | |
452 | printk("PCI%d: Using PBM_A, report this problem immediately.\n", | |
453 | p->index); | |
454 | ||
455 | return &p->pbm_A; | |
456 | } | |
457 | ||
458 | static void schizo_clear_other_err_intr(struct pci_controller_info *p, int irq) | |
459 | { | |
460 | struct pci_pbm_info *pbm; | |
461 | struct ino_bucket *bucket; | |
462 | unsigned long iclr; | |
463 | ||
464 | /* Do not clear the interrupt for the other PCI bus. | |
465 | * | |
466 | * This "ACK both PBM IRQs" only needs to be performed | |
467 | * for chip-wide error interrupts. | |
468 | */ | |
469 | if ((irq & IMAP_INO) == SCHIZO_PCIERR_A_INO || | |
470 | (irq & IMAP_INO) == SCHIZO_PCIERR_B_INO) | |
471 | return; | |
472 | ||
473 | pbm = pbm_for_ino(p, irq); | |
474 | if (pbm == &p->pbm_A) | |
475 | pbm = &p->pbm_B; | |
476 | else | |
477 | pbm = &p->pbm_A; | |
478 | ||
479 | irq = schizo_irq_build(pbm, NULL, | |
480 | (pbm->portid << 6) | (irq & IMAP_INO)); | |
481 | bucket = __bucket(irq); | |
482 | iclr = bucket->iclr; | |
483 | ||
484 | upa_writel(ICLR_IDLE, iclr); | |
485 | } | |
486 | ||
487 | #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */ | |
488 | #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */ | |
489 | #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */ | |
490 | ||
491 | #define SCHIZO_STCERR_WRITE 0x2UL | |
492 | #define SCHIZO_STCERR_READ 0x1UL | |
493 | ||
494 | #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL | |
495 | #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL | |
496 | #define SCHIZO_STCTAG_VALID 0x8000000000000000UL | |
497 | #define SCHIZO_STCTAG_READ 0x4000000000000000UL | |
498 | ||
499 | #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL | |
500 | #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL | |
501 | #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL | |
502 | #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL | |
503 | #define SCHIZO_STCLINE_VALID 0x0000000000600000UL | |
504 | #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL | |
505 | ||
506 | static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm, | |
507 | enum schizo_error_type type) | |
508 | { | |
509 | struct pci_strbuf *strbuf = &pbm->stc; | |
510 | unsigned long regbase = pbm->pbm_regs; | |
511 | unsigned long err_base, tag_base, line_base; | |
512 | u64 control; | |
513 | int i; | |
514 | ||
515 | err_base = regbase + SCHIZO_STC_ERR; | |
516 | tag_base = regbase + SCHIZO_STC_TAG; | |
517 | line_base = regbase + SCHIZO_STC_LINE; | |
518 | ||
519 | spin_lock(&stc_buf_lock); | |
520 | ||
521 | /* This is __REALLY__ dangerous. When we put the | |
522 | * streaming buffer into diagnostic mode to probe | |
523 | * it's tags and error status, we _must_ clear all | |
524 | * of the line tag valid bits before re-enabling | |
525 | * the streaming buffer. If any dirty data lives | |
526 | * in the STC when we do this, we will end up | |
527 | * invalidating it before it has a chance to reach | |
528 | * main memory. | |
529 | */ | |
530 | control = schizo_read(strbuf->strbuf_control); | |
531 | schizo_write(strbuf->strbuf_control, | |
532 | (control | SCHIZO_STRBUF_CTRL_DENAB)); | |
533 | for (i = 0; i < 128; i++) { | |
534 | unsigned long val; | |
535 | ||
536 | val = schizo_read(err_base + (i * 8UL)); | |
537 | schizo_write(err_base + (i * 8UL), 0UL); | |
538 | stc_error_buf[i] = val; | |
539 | } | |
540 | for (i = 0; i < 16; i++) { | |
541 | stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL)); | |
542 | stc_line_buf[i] = schizo_read(line_base + (i * 8UL)); | |
543 | schizo_write(tag_base + (i * 8UL), 0UL); | |
544 | schizo_write(line_base + (i * 8UL), 0UL); | |
545 | } | |
546 | ||
547 | /* OK, state is logged, exit diagnostic mode. */ | |
548 | schizo_write(strbuf->strbuf_control, control); | |
549 | ||
550 | for (i = 0; i < 16; i++) { | |
551 | int j, saw_error, first, last; | |
552 | ||
553 | saw_error = 0; | |
554 | first = i * 8; | |
555 | last = first + 8; | |
556 | for (j = first; j < last; j++) { | |
557 | unsigned long errval = stc_error_buf[j]; | |
558 | if (errval != 0) { | |
559 | saw_error++; | |
560 | printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n", | |
561 | pbm->name, | |
562 | j, | |
563 | (errval & SCHIZO_STCERR_WRITE) ? 1 : 0, | |
564 | (errval & SCHIZO_STCERR_READ) ? 1 : 0); | |
565 | } | |
566 | } | |
567 | if (saw_error != 0) { | |
568 | unsigned long tagval = stc_tag_buf[i]; | |
569 | unsigned long lineval = stc_line_buf[i]; | |
570 | printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n", | |
571 | pbm->name, | |
572 | i, | |
573 | ((tagval & SCHIZO_STCTAG_PPN) >> 19UL), | |
574 | (tagval & SCHIZO_STCTAG_VPN), | |
575 | ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0), | |
576 | ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0)); | |
577 | ||
578 | /* XXX Should spit out per-bank error information... -DaveM */ | |
579 | printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)" | |
580 | "V(%d)FOFN(%d)]\n", | |
581 | pbm->name, | |
582 | i, | |
583 | ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL), | |
584 | ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL), | |
585 | ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL), | |
586 | ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL), | |
587 | ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0), | |
588 | ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0)); | |
589 | } | |
590 | } | |
591 | ||
592 | spin_unlock(&stc_buf_lock); | |
593 | } | |
594 | ||
595 | /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous | |
596 | * controller level errors. | |
597 | */ | |
598 | ||
599 | #define SCHIZO_IOMMU_TAG 0xa580UL | |
600 | #define SCHIZO_IOMMU_DATA 0xa600UL | |
601 | ||
602 | #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL | |
603 | #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL | |
604 | #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL | |
605 | #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL | |
606 | #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL | |
607 | #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL | |
608 | #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL | |
609 | ||
610 | #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL | |
611 | #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL | |
612 | #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL | |
613 | ||
614 | static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm, | |
615 | enum schizo_error_type type) | |
616 | { | |
617 | struct pci_iommu *iommu = pbm->iommu; | |
618 | unsigned long iommu_tag[16]; | |
619 | unsigned long iommu_data[16]; | |
620 | unsigned long flags; | |
621 | u64 control; | |
622 | int i; | |
623 | ||
624 | spin_lock_irqsave(&iommu->lock, flags); | |
625 | control = schizo_read(iommu->iommu_control); | |
626 | if (control & SCHIZO_IOMMU_CTRL_XLTEERR) { | |
627 | unsigned long base; | |
628 | char *type_string; | |
629 | ||
630 | /* Clear the error encountered bit. */ | |
631 | control &= ~SCHIZO_IOMMU_CTRL_XLTEERR; | |
632 | schizo_write(iommu->iommu_control, control); | |
633 | ||
634 | switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) { | |
635 | case 0: | |
636 | type_string = "Protection Error"; | |
637 | break; | |
638 | case 1: | |
639 | type_string = "Invalid Error"; | |
640 | break; | |
641 | case 2: | |
642 | type_string = "TimeOut Error"; | |
643 | break; | |
644 | case 3: | |
645 | default: | |
646 | type_string = "ECC Error"; | |
647 | break; | |
648 | }; | |
649 | printk("%s: IOMMU Error, type[%s]\n", | |
650 | pbm->name, type_string); | |
651 | ||
652 | /* Put the IOMMU into diagnostic mode and probe | |
653 | * it's TLB for entries with error status. | |
654 | * | |
655 | * It is very possible for another DVMA to occur | |
656 | * while we do this probe, and corrupt the system | |
657 | * further. But we are so screwed at this point | |
658 | * that we are likely to crash hard anyways, so | |
659 | * get as much diagnostic information to the | |
660 | * console as we can. | |
661 | */ | |
662 | schizo_write(iommu->iommu_control, | |
663 | control | SCHIZO_IOMMU_CTRL_DENAB); | |
664 | ||
665 | base = pbm->pbm_regs; | |
666 | ||
667 | for (i = 0; i < 16; i++) { | |
668 | iommu_tag[i] = | |
669 | schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL)); | |
670 | iommu_data[i] = | |
671 | schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL)); | |
672 | ||
673 | /* Now clear out the entry. */ | |
674 | schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0); | |
675 | schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0); | |
676 | } | |
677 | ||
678 | /* Leave diagnostic mode. */ | |
679 | schizo_write(iommu->iommu_control, control); | |
680 | ||
681 | for (i = 0; i < 16; i++) { | |
682 | unsigned long tag, data; | |
683 | ||
684 | tag = iommu_tag[i]; | |
685 | if (!(tag & SCHIZO_IOMMU_TAG_ERR)) | |
686 | continue; | |
687 | ||
688 | data = iommu_data[i]; | |
689 | switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) { | |
690 | case 0: | |
691 | type_string = "Protection Error"; | |
692 | break; | |
693 | case 1: | |
694 | type_string = "Invalid Error"; | |
695 | break; | |
696 | case 2: | |
697 | type_string = "TimeOut Error"; | |
698 | break; | |
699 | case 3: | |
700 | default: | |
701 | type_string = "ECC Error"; | |
702 | break; | |
703 | }; | |
704 | printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) " | |
705 | "sz(%dK) vpg(%08lx)]\n", | |
706 | pbm->name, i, type_string, | |
707 | (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL), | |
708 | ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0), | |
709 | ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0), | |
710 | ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8), | |
711 | (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT); | |
712 | printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n", | |
713 | pbm->name, i, | |
714 | ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0), | |
715 | ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0), | |
716 | (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT); | |
717 | } | |
718 | } | |
719 | if (pbm->stc.strbuf_enabled) | |
720 | __schizo_check_stc_error_pbm(pbm, type); | |
721 | spin_unlock_irqrestore(&iommu->lock, flags); | |
722 | } | |
723 | ||
724 | static void schizo_check_iommu_error(struct pci_controller_info *p, | |
725 | enum schizo_error_type type) | |
726 | { | |
727 | schizo_check_iommu_error_pbm(&p->pbm_A, type); | |
728 | schizo_check_iommu_error_pbm(&p->pbm_B, type); | |
729 | } | |
730 | ||
731 | /* Uncorrectable ECC error status gathering. */ | |
732 | #define SCHIZO_UE_AFSR 0x10030UL | |
733 | #define SCHIZO_UE_AFAR 0x10038UL | |
734 | ||
735 | #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */ | |
736 | #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */ | |
737 | #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */ | |
738 | #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */ | |
739 | #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */ | |
740 | #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */ | |
741 | #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */ | |
742 | #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */ | |
743 | #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */ | |
744 | #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */ | |
745 | #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */ | |
746 | #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */ | |
747 | #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */ | |
748 | #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */ | |
749 | ||
750 | static irqreturn_t schizo_ue_intr(int irq, void *dev_id, struct pt_regs *regs) | |
751 | { | |
752 | struct pci_controller_info *p = dev_id; | |
753 | unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFSR; | |
754 | unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFAR; | |
755 | unsigned long afsr, afar, error_bits; | |
756 | int reported, limit; | |
757 | ||
758 | /* Latch uncorrectable error status. */ | |
759 | afar = schizo_read(afar_reg); | |
760 | ||
761 | /* If either of the error pending bits are set in the | |
762 | * AFSR, the error status is being actively updated by | |
763 | * the hardware and we must re-read to get a clean value. | |
764 | */ | |
765 | limit = 1000; | |
766 | do { | |
767 | afsr = schizo_read(afsr_reg); | |
768 | } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); | |
769 | ||
770 | /* Clear the primary/secondary error status bits. */ | |
771 | error_bits = afsr & | |
772 | (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR | | |
773 | SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA); | |
774 | if (!error_bits) | |
775 | return IRQ_NONE; | |
776 | schizo_write(afsr_reg, error_bits); | |
777 | ||
778 | /* Log the error. */ | |
779 | printk("PCI%d: Uncorrectable Error, primary error type[%s]\n", | |
780 | p->index, | |
781 | (((error_bits & SCHIZO_UEAFSR_PPIO) ? | |
782 | "PIO" : | |
783 | ((error_bits & SCHIZO_UEAFSR_PDRD) ? | |
784 | "DMA Read" : | |
785 | ((error_bits & SCHIZO_UEAFSR_PDWR) ? | |
786 | "DMA Write" : "???"))))); | |
787 | printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", | |
788 | p->index, | |
789 | (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, | |
790 | (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, | |
791 | (afsr & SCHIZO_UEAFSR_AID) >> 24UL); | |
792 | printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", | |
793 | p->index, | |
794 | (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, | |
795 | (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, | |
796 | (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, | |
797 | (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, | |
798 | (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); | |
799 | printk("PCI%d: UE AFAR [%016lx]\n", p->index, afar); | |
800 | printk("PCI%d: UE Secondary errors [", p->index); | |
801 | reported = 0; | |
802 | if (afsr & SCHIZO_UEAFSR_SPIO) { | |
803 | reported++; | |
804 | printk("(PIO)"); | |
805 | } | |
806 | if (afsr & SCHIZO_UEAFSR_SDMA) { | |
807 | reported++; | |
808 | printk("(DMA)"); | |
809 | } | |
810 | if (!reported) | |
811 | printk("(none)"); | |
812 | printk("]\n"); | |
813 | ||
814 | /* Interrogate IOMMU for error status. */ | |
815 | schizo_check_iommu_error(p, UE_ERR); | |
816 | ||
817 | schizo_clear_other_err_intr(p, irq); | |
818 | ||
819 | return IRQ_HANDLED; | |
820 | } | |
821 | ||
822 | #define SCHIZO_CE_AFSR 0x10040UL | |
823 | #define SCHIZO_CE_AFAR 0x10048UL | |
824 | ||
825 | #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL | |
826 | #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL | |
827 | #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL | |
828 | #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL | |
829 | #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL | |
830 | #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL | |
831 | #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL | |
832 | #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL | |
833 | #define SCHIZO_CEAFSR_AID 0x000000001f000000UL | |
834 | #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL | |
835 | #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL | |
836 | #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL | |
837 | #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL | |
838 | #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL | |
839 | ||
840 | static irqreturn_t schizo_ce_intr(int irq, void *dev_id, struct pt_regs *regs) | |
841 | { | |
842 | struct pci_controller_info *p = dev_id; | |
843 | unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFSR; | |
844 | unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFAR; | |
845 | unsigned long afsr, afar, error_bits; | |
846 | int reported, limit; | |
847 | ||
848 | /* Latch error status. */ | |
849 | afar = schizo_read(afar_reg); | |
850 | ||
851 | /* If either of the error pending bits are set in the | |
852 | * AFSR, the error status is being actively updated by | |
853 | * the hardware and we must re-read to get a clean value. | |
854 | */ | |
855 | limit = 1000; | |
856 | do { | |
857 | afsr = schizo_read(afsr_reg); | |
858 | } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit); | |
859 | ||
860 | /* Clear primary/secondary error status bits. */ | |
861 | error_bits = afsr & | |
862 | (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR | | |
863 | SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA); | |
864 | if (!error_bits) | |
865 | return IRQ_NONE; | |
866 | schizo_write(afsr_reg, error_bits); | |
867 | ||
868 | /* Log the error. */ | |
869 | printk("PCI%d: Correctable Error, primary error type[%s]\n", | |
870 | p->index, | |
871 | (((error_bits & SCHIZO_CEAFSR_PPIO) ? | |
872 | "PIO" : | |
873 | ((error_bits & SCHIZO_CEAFSR_PDRD) ? | |
874 | "DMA Read" : | |
875 | ((error_bits & SCHIZO_CEAFSR_PDWR) ? | |
876 | "DMA Write" : "???"))))); | |
877 | ||
878 | /* XXX Use syndrome and afar to print out module string just like | |
879 | * XXX UDB CE trap handler does... -DaveM | |
880 | */ | |
881 | printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n", | |
882 | p->index, | |
883 | (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL, | |
884 | (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL, | |
885 | (afsr & SCHIZO_UEAFSR_AID) >> 24UL); | |
886 | printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n", | |
887 | p->index, | |
888 | (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0, | |
889 | (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0, | |
890 | (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL, | |
891 | (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL, | |
892 | (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL); | |
893 | printk("PCI%d: CE AFAR [%016lx]\n", p->index, afar); | |
894 | printk("PCI%d: CE Secondary errors [", p->index); | |
895 | reported = 0; | |
896 | if (afsr & SCHIZO_CEAFSR_SPIO) { | |
897 | reported++; | |
898 | printk("(PIO)"); | |
899 | } | |
900 | if (afsr & SCHIZO_CEAFSR_SDMA) { | |
901 | reported++; | |
902 | printk("(DMA)"); | |
903 | } | |
904 | if (!reported) | |
905 | printk("(none)"); | |
906 | printk("]\n"); | |
907 | ||
908 | schizo_clear_other_err_intr(p, irq); | |
909 | ||
910 | return IRQ_HANDLED; | |
911 | } | |
912 | ||
913 | #define SCHIZO_PCI_AFSR 0x2010UL | |
914 | #define SCHIZO_PCI_AFAR 0x2018UL | |
915 | ||
916 | #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */ | |
917 | #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */ | |
918 | #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */ | |
919 | #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */ | |
920 | #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */ | |
921 | #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */ | |
922 | #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */ | |
923 | #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */ | |
924 | #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */ | |
925 | #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */ | |
926 | #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */ | |
927 | #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */ | |
928 | #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */ | |
929 | #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */ | |
930 | #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */ | |
931 | #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */ | |
932 | #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */ | |
933 | ||
934 | #define SCHIZO_PCI_CTRL (0x2000UL) | |
935 | #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */ | |
9fba62a5 | 936 | #define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */ |
1da177e4 LT |
937 | #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */ |
938 | #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */ | |
939 | #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */ | |
940 | #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */ | |
941 | #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */ | |
942 | #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */ | |
943 | #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */ | |
944 | #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */ | |
945 | #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */ | |
946 | #define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */ | |
947 | #define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */ | |
948 | #define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */ | |
949 | #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */ | |
950 | #define SCHIZO_PCICTRL_PTO_SHIFT 24UL | |
951 | #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */ | |
952 | #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */ | |
953 | #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */ | |
954 | #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */ | |
955 | #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */ | |
956 | #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */ | |
957 | #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */ | |
958 | #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */ | |
959 | #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */ | |
960 | #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */ | |
961 | #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */ | |
962 | ||
963 | static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm) | |
964 | { | |
965 | unsigned long csr_reg, csr, csr_error_bits; | |
966 | irqreturn_t ret = IRQ_NONE; | |
967 | u16 stat; | |
968 | ||
969 | csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL; | |
970 | csr = schizo_read(csr_reg); | |
971 | csr_error_bits = | |
972 | csr & (SCHIZO_PCICTRL_BUS_UNUS | | |
973 | SCHIZO_PCICTRL_TTO_ERR | | |
974 | SCHIZO_PCICTRL_RTRY_ERR | | |
975 | SCHIZO_PCICTRL_DTO_ERR | | |
976 | SCHIZO_PCICTRL_SBH_ERR | | |
977 | SCHIZO_PCICTRL_SERR); | |
978 | if (csr_error_bits) { | |
979 | /* Clear the errors. */ | |
980 | schizo_write(csr_reg, csr); | |
981 | ||
982 | /* Log 'em. */ | |
983 | if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS) | |
984 | printk("%s: Bus unusable error asserted.\n", | |
985 | pbm->name); | |
986 | if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR) | |
987 | printk("%s: PCI TRDY# timeout error asserted.\n", | |
988 | pbm->name); | |
989 | if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR) | |
990 | printk("%s: PCI excessive retry error asserted.\n", | |
991 | pbm->name); | |
992 | if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR) | |
993 | printk("%s: PCI discard timeout error asserted.\n", | |
994 | pbm->name); | |
995 | if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR) | |
996 | printk("%s: PCI streaming byte hole error asserted.\n", | |
997 | pbm->name); | |
998 | if (csr_error_bits & SCHIZO_PCICTRL_SERR) | |
999 | printk("%s: PCI SERR signal asserted.\n", | |
1000 | pbm->name); | |
1001 | ret = IRQ_HANDLED; | |
1002 | } | |
1003 | pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat); | |
1004 | if (stat & (PCI_STATUS_PARITY | | |
1005 | PCI_STATUS_SIG_TARGET_ABORT | | |
1006 | PCI_STATUS_REC_TARGET_ABORT | | |
1007 | PCI_STATUS_REC_MASTER_ABORT | | |
1008 | PCI_STATUS_SIG_SYSTEM_ERROR)) { | |
1009 | printk("%s: PCI bus error, PCI_STATUS[%04x]\n", | |
1010 | pbm->name, stat); | |
1011 | pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff); | |
1012 | ret = IRQ_HANDLED; | |
1013 | } | |
1014 | return ret; | |
1015 | } | |
1016 | ||
1017 | static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs) | |
1018 | { | |
1019 | struct pci_pbm_info *pbm = dev_id; | |
1020 | struct pci_controller_info *p = pbm->parent; | |
1021 | unsigned long afsr_reg, afar_reg, base; | |
1022 | unsigned long afsr, afar, error_bits; | |
1023 | int reported; | |
1024 | ||
1025 | base = pbm->pbm_regs; | |
1026 | ||
1027 | afsr_reg = base + SCHIZO_PCI_AFSR; | |
1028 | afar_reg = base + SCHIZO_PCI_AFAR; | |
1029 | ||
1030 | /* Latch error status. */ | |
1031 | afar = schizo_read(afar_reg); | |
1032 | afsr = schizo_read(afsr_reg); | |
1033 | ||
1034 | /* Clear primary/secondary error status bits. */ | |
1035 | error_bits = afsr & | |
1036 | (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | | |
1037 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | | |
1038 | SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | | |
1039 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | | |
1040 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | | |
1041 | SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS); | |
1042 | if (!error_bits) | |
1043 | return schizo_pcierr_intr_other(pbm); | |
1044 | schizo_write(afsr_reg, error_bits); | |
1045 | ||
1046 | /* Log the error. */ | |
1047 | printk("%s: PCI Error, primary error type[%s]\n", | |
1048 | pbm->name, | |
1049 | (((error_bits & SCHIZO_PCIAFSR_PMA) ? | |
1050 | "Master Abort" : | |
1051 | ((error_bits & SCHIZO_PCIAFSR_PTA) ? | |
1052 | "Target Abort" : | |
1053 | ((error_bits & SCHIZO_PCIAFSR_PRTRY) ? | |
1054 | "Excessive Retries" : | |
1055 | ((error_bits & SCHIZO_PCIAFSR_PPERR) ? | |
1056 | "Parity Error" : | |
1057 | ((error_bits & SCHIZO_PCIAFSR_PTTO) ? | |
1058 | "Timeout" : | |
1059 | ((error_bits & SCHIZO_PCIAFSR_PUNUS) ? | |
1060 | "Bus Unusable" : "???")))))))); | |
1061 | printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n", | |
1062 | pbm->name, | |
1063 | (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL, | |
1064 | (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0, | |
1065 | ((afsr & SCHIZO_PCIAFSR_CFG) ? | |
1066 | "Config" : | |
1067 | ((afsr & SCHIZO_PCIAFSR_MEM) ? | |
1068 | "Memory" : | |
1069 | ((afsr & SCHIZO_PCIAFSR_IO) ? | |
1070 | "I/O" : "???")))); | |
1071 | printk("%s: PCI AFAR [%016lx]\n", | |
1072 | pbm->name, afar); | |
1073 | printk("%s: PCI Secondary errors [", | |
1074 | pbm->name); | |
1075 | reported = 0; | |
1076 | if (afsr & SCHIZO_PCIAFSR_SMA) { | |
1077 | reported++; | |
1078 | printk("(Master Abort)"); | |
1079 | } | |
1080 | if (afsr & SCHIZO_PCIAFSR_STA) { | |
1081 | reported++; | |
1082 | printk("(Target Abort)"); | |
1083 | } | |
1084 | if (afsr & SCHIZO_PCIAFSR_SRTRY) { | |
1085 | reported++; | |
1086 | printk("(Excessive Retries)"); | |
1087 | } | |
1088 | if (afsr & SCHIZO_PCIAFSR_SPERR) { | |
1089 | reported++; | |
1090 | printk("(Parity Error)"); | |
1091 | } | |
1092 | if (afsr & SCHIZO_PCIAFSR_STTO) { | |
1093 | reported++; | |
1094 | printk("(Timeout)"); | |
1095 | } | |
1096 | if (afsr & SCHIZO_PCIAFSR_SUNUS) { | |
1097 | reported++; | |
1098 | printk("(Bus Unusable)"); | |
1099 | } | |
1100 | if (!reported) | |
1101 | printk("(none)"); | |
1102 | printk("]\n"); | |
1103 | ||
1104 | /* For the error types shown, scan PBM's PCI bus for devices | |
1105 | * which have logged that error type. | |
1106 | */ | |
1107 | ||
1108 | /* If we see a Target Abort, this could be the result of an | |
1109 | * IOMMU translation error of some sort. It is extremely | |
1110 | * useful to log this information as usually it indicates | |
1111 | * a bug in the IOMMU support code or a PCI device driver. | |
1112 | */ | |
1113 | if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) { | |
1114 | schizo_check_iommu_error(p, PCI_ERR); | |
1115 | pci_scan_for_target_abort(p, pbm, pbm->pci_bus); | |
1116 | } | |
1117 | if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA)) | |
1118 | pci_scan_for_master_abort(p, pbm, pbm->pci_bus); | |
1119 | ||
1120 | /* For excessive retries, PSYCHO/PBM will abort the device | |
1121 | * and there is no way to specifically check for excessive | |
1122 | * retries in the config space status registers. So what | |
1123 | * we hope is that we'll catch it via the master/target | |
1124 | * abort events. | |
1125 | */ | |
1126 | ||
1127 | if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR)) | |
1128 | pci_scan_for_parity_error(p, pbm, pbm->pci_bus); | |
1129 | ||
1130 | schizo_clear_other_err_intr(p, irq); | |
1131 | ||
1132 | return IRQ_HANDLED; | |
1133 | } | |
1134 | ||
1135 | #define SCHIZO_SAFARI_ERRLOG 0x10018UL | |
1136 | ||
1137 | #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL | |
1138 | ||
1139 | #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */ | |
1140 | #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */ | |
1141 | #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */ | |
1142 | #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */ | |
1143 | #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */ | |
1144 | #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */ | |
1145 | #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */ | |
1146 | #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */ | |
1147 | #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */ | |
1148 | #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */ | |
1149 | #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */ | |
1150 | #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */ | |
1151 | #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */ | |
1152 | #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */ | |
1153 | #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */ | |
1154 | #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */ | |
1155 | #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */ | |
1156 | #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */ | |
1157 | #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */ | |
1158 | #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */ | |
1159 | #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */ | |
1160 | #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */ | |
1161 | #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */ | |
1162 | #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */ | |
1163 | #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */ | |
1164 | #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */ | |
1165 | #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */ | |
1166 | #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */ | |
1167 | #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */ | |
1168 | #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */ | |
1169 | #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */ | |
1170 | ||
1171 | /* We only expect UNMAP errors here. The rest of the Safari errors | |
1172 | * are marked fatal and thus cause a system reset. | |
1173 | */ | |
1174 | static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *regs) | |
1175 | { | |
1176 | struct pci_controller_info *p = dev_id; | |
1177 | u64 errlog; | |
1178 | ||
1179 | errlog = schizo_read(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG); | |
1180 | schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG, | |
1181 | errlog & ~(SAFARI_ERRLOG_ERROUT)); | |
1182 | ||
1183 | if (!(errlog & BUS_ERROR_UNMAP)) { | |
1184 | printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n", | |
1185 | p->index, errlog); | |
1186 | ||
1187 | schizo_clear_other_err_intr(p, irq); | |
1188 | return IRQ_HANDLED; | |
1189 | } | |
1190 | ||
1191 | printk("PCI%d: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n", | |
1192 | p->index); | |
1193 | schizo_check_iommu_error(p, SAFARI_ERR); | |
1194 | ||
1195 | schizo_clear_other_err_intr(p, irq); | |
1196 | return IRQ_HANDLED; | |
1197 | } | |
1198 | ||
1199 | /* Nearly identical to PSYCHO equivalents... */ | |
1200 | #define SCHIZO_ECC_CTRL 0x10020UL | |
1201 | #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */ | |
1202 | #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */ | |
1203 | #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */ | |
1204 | ||
1205 | #define SCHIZO_SAFARI_ERRCTRL 0x10008UL | |
1206 | #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL | |
1207 | #define SCHIZO_SAFARI_IRQCTRL 0x10010UL | |
1208 | #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL | |
1209 | ||
1210 | /* How the Tomatillo IRQs are routed around is pure guesswork here. | |
1211 | * | |
1212 | * All the Tomatillo devices I see in prtconf dumps seem to have only | |
1213 | * a single PCI bus unit attached to it. It would seem they are seperate | |
1214 | * devices because their PortID (ie. JBUS ID) values are all different | |
1215 | * and thus the registers are mapped to totally different locations. | |
1216 | * | |
1217 | * However, two Tomatillo's look "similar" in that the only difference | |
1218 | * in their PortID is the lowest bit. | |
1219 | * | |
1220 | * So if we were to ignore this lower bit, it certainly looks like two | |
1221 | * PCI bus units of the same Tomatillo. I still have not really | |
1222 | * figured this out... | |
1223 | */ | |
085ae41f | 1224 | static void tomatillo_register_error_handlers(struct pci_controller_info *p) |
1da177e4 LT |
1225 | { |
1226 | struct pci_pbm_info *pbm; | |
1227 | unsigned int irq; | |
1228 | struct ino_bucket *bucket; | |
1229 | u64 tmp, err_mask, err_no_mask; | |
1230 | ||
1231 | /* Build IRQs and register handlers. */ | |
1232 | pbm = pbm_for_ino(p, SCHIZO_UE_INO); | |
1233 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO); | |
1234 | if (request_irq(irq, schizo_ue_intr, | |
1235 | SA_SHIRQ, "TOMATILLO UE", p) < 0) { | |
1236 | prom_printf("%s: Cannot register UE interrupt.\n", | |
1237 | pbm->name); | |
1238 | prom_halt(); | |
1239 | } | |
1240 | bucket = __bucket(irq); | |
1241 | tmp = upa_readl(bucket->imap); | |
1242 | upa_writel(tmp, (pbm->pbm_regs + | |
1243 | schizo_imap_offset(SCHIZO_UE_INO) + 4)); | |
1244 | ||
1245 | pbm = pbm_for_ino(p, SCHIZO_CE_INO); | |
1246 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO); | |
1247 | if (request_irq(irq, schizo_ce_intr, | |
1248 | SA_SHIRQ, "TOMATILLO CE", p) < 0) { | |
1249 | prom_printf("%s: Cannot register CE interrupt.\n", | |
1250 | pbm->name); | |
1251 | prom_halt(); | |
1252 | } | |
1253 | bucket = __bucket(irq); | |
1254 | tmp = upa_readl(bucket->imap); | |
1255 | upa_writel(tmp, (pbm->pbm_regs + | |
1256 | schizo_imap_offset(SCHIZO_CE_INO) + 4)); | |
1257 | ||
1258 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO); | |
1259 | irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) | | |
1260 | SCHIZO_PCIERR_A_INO)); | |
1261 | if (request_irq(irq, schizo_pcierr_intr, | |
1262 | SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) { | |
1263 | prom_printf("%s: Cannot register PBM A PciERR interrupt.\n", | |
1264 | pbm->name); | |
1265 | prom_halt(); | |
1266 | } | |
1267 | bucket = __bucket(irq); | |
1268 | tmp = upa_readl(bucket->imap); | |
1269 | upa_writel(tmp, (pbm->pbm_regs + | |
1270 | schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4)); | |
1271 | ||
1272 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO); | |
1273 | irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) | | |
1274 | SCHIZO_PCIERR_B_INO)); | |
1275 | if (request_irq(irq, schizo_pcierr_intr, | |
1276 | SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) { | |
1277 | prom_printf("%s: Cannot register PBM B PciERR interrupt.\n", | |
1278 | pbm->name); | |
1279 | prom_halt(); | |
1280 | } | |
1281 | bucket = __bucket(irq); | |
1282 | tmp = upa_readl(bucket->imap); | |
1283 | upa_writel(tmp, (pbm->pbm_regs + | |
1284 | schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4)); | |
1285 | ||
1286 | pbm = pbm_for_ino(p, SCHIZO_SERR_INO); | |
1287 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO); | |
1288 | if (request_irq(irq, schizo_safarierr_intr, | |
1289 | SA_SHIRQ, "TOMATILLO SERR", p) < 0) { | |
1290 | prom_printf("%s: Cannot register SafariERR interrupt.\n", | |
1291 | pbm->name); | |
1292 | prom_halt(); | |
1293 | } | |
1294 | bucket = __bucket(irq); | |
1295 | tmp = upa_readl(bucket->imap); | |
1296 | upa_writel(tmp, (pbm->pbm_regs + | |
1297 | schizo_imap_offset(SCHIZO_SERR_INO) + 4)); | |
1298 | ||
1299 | /* Enable UE and CE interrupts for controller. */ | |
1300 | schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, | |
1301 | (SCHIZO_ECCCTRL_EE | | |
1302 | SCHIZO_ECCCTRL_UE | | |
1303 | SCHIZO_ECCCTRL_CE)); | |
1304 | ||
1305 | schizo_write(p->pbm_B.controller_regs + SCHIZO_ECC_CTRL, | |
1306 | (SCHIZO_ECCCTRL_EE | | |
1307 | SCHIZO_ECCCTRL_UE | | |
1308 | SCHIZO_ECCCTRL_CE)); | |
1309 | ||
1310 | /* Enable PCI Error interrupts and clear error | |
1311 | * bits. | |
1312 | */ | |
1313 | err_mask = (SCHIZO_PCICTRL_BUS_UNUS | | |
1314 | SCHIZO_PCICTRL_TTO_ERR | | |
1315 | SCHIZO_PCICTRL_RTRY_ERR | | |
1316 | SCHIZO_PCICTRL_SERR | | |
1317 | SCHIZO_PCICTRL_EEN); | |
1318 | ||
1319 | err_no_mask = SCHIZO_PCICTRL_DTO_ERR; | |
1320 | ||
1321 | tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL); | |
1322 | tmp |= err_mask; | |
1323 | tmp &= ~err_no_mask; | |
1324 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1325 | ||
1326 | tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL); | |
1327 | tmp |= err_mask; | |
1328 | tmp &= ~err_no_mask; | |
1329 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1330 | ||
1331 | err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | | |
1332 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | | |
1333 | SCHIZO_PCIAFSR_PTTO | | |
1334 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | | |
1335 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | | |
1336 | SCHIZO_PCIAFSR_STTO); | |
1337 | ||
1338 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, err_mask); | |
1339 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, err_mask); | |
1340 | ||
1341 | err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR | | |
1342 | BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD | | |
1343 | BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA | | |
1344 | BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO | | |
1345 | BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR | | |
1346 | BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B | | |
1347 | BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR | | |
1348 | BUS_ERROR_APERR | BUS_ERROR_UNMAP | | |
1349 | BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT); | |
1350 | ||
1351 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL, | |
1352 | (SCHIZO_SAFERRCTRL_EN | err_mask)); | |
1353 | schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRCTRL, | |
1354 | (SCHIZO_SAFERRCTRL_EN | err_mask)); | |
1355 | ||
1356 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL, | |
1357 | (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); | |
1358 | schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_IRQCTRL, | |
1359 | (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); | |
1360 | } | |
1361 | ||
085ae41f | 1362 | static void schizo_register_error_handlers(struct pci_controller_info *p) |
1da177e4 LT |
1363 | { |
1364 | struct pci_pbm_info *pbm; | |
1365 | unsigned int irq; | |
1366 | struct ino_bucket *bucket; | |
1367 | u64 tmp, err_mask, err_no_mask; | |
1368 | ||
1369 | /* Build IRQs and register handlers. */ | |
1370 | pbm = pbm_for_ino(p, SCHIZO_UE_INO); | |
1371 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO); | |
1372 | if (request_irq(irq, schizo_ue_intr, | |
1373 | SA_SHIRQ, "SCHIZO UE", p) < 0) { | |
1374 | prom_printf("%s: Cannot register UE interrupt.\n", | |
1375 | pbm->name); | |
1376 | prom_halt(); | |
1377 | } | |
1378 | bucket = __bucket(irq); | |
1379 | tmp = upa_readl(bucket->imap); | |
1380 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4)); | |
1381 | ||
1382 | pbm = pbm_for_ino(p, SCHIZO_CE_INO); | |
1383 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO); | |
1384 | if (request_irq(irq, schizo_ce_intr, | |
1385 | SA_SHIRQ, "SCHIZO CE", p) < 0) { | |
1386 | prom_printf("%s: Cannot register CE interrupt.\n", | |
1387 | pbm->name); | |
1388 | prom_halt(); | |
1389 | } | |
1390 | bucket = __bucket(irq); | |
1391 | tmp = upa_readl(bucket->imap); | |
1392 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4)); | |
1393 | ||
1394 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO); | |
1395 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO); | |
1396 | if (request_irq(irq, schizo_pcierr_intr, | |
1397 | SA_SHIRQ, "SCHIZO PCIERR", pbm) < 0) { | |
1398 | prom_printf("%s: Cannot register PBM A PciERR interrupt.\n", | |
1399 | pbm->name); | |
1400 | prom_halt(); | |
1401 | } | |
1402 | bucket = __bucket(irq); | |
1403 | tmp = upa_readl(bucket->imap); | |
1404 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4)); | |
1405 | ||
1406 | pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO); | |
1407 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO); | |
1408 | if (request_irq(irq, schizo_pcierr_intr, | |
1409 | SA_SHIRQ, "SCHIZO PCIERR", &p->pbm_B) < 0) { | |
1410 | prom_printf("%s: Cannot register PBM B PciERR interrupt.\n", | |
1411 | pbm->name); | |
1412 | prom_halt(); | |
1413 | } | |
1414 | bucket = __bucket(irq); | |
1415 | tmp = upa_readl(bucket->imap); | |
1416 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4)); | |
1417 | ||
1418 | pbm = pbm_for_ino(p, SCHIZO_SERR_INO); | |
1419 | irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO); | |
1420 | if (request_irq(irq, schizo_safarierr_intr, | |
1421 | SA_SHIRQ, "SCHIZO SERR", p) < 0) { | |
1422 | prom_printf("%s: Cannot register SafariERR interrupt.\n", | |
1423 | pbm->name); | |
1424 | prom_halt(); | |
1425 | } | |
1426 | bucket = __bucket(irq); | |
1427 | tmp = upa_readl(bucket->imap); | |
1428 | upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4)); | |
1429 | ||
1430 | /* Enable UE and CE interrupts for controller. */ | |
1431 | schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL, | |
1432 | (SCHIZO_ECCCTRL_EE | | |
1433 | SCHIZO_ECCCTRL_UE | | |
1434 | SCHIZO_ECCCTRL_CE)); | |
1435 | ||
1436 | err_mask = (SCHIZO_PCICTRL_BUS_UNUS | | |
1437 | SCHIZO_PCICTRL_ESLCK | | |
1438 | SCHIZO_PCICTRL_TTO_ERR | | |
1439 | SCHIZO_PCICTRL_RTRY_ERR | | |
1440 | SCHIZO_PCICTRL_SBH_ERR | | |
1441 | SCHIZO_PCICTRL_SERR | | |
1442 | SCHIZO_PCICTRL_EEN); | |
1443 | ||
1444 | err_no_mask = (SCHIZO_PCICTRL_DTO_ERR | | |
1445 | SCHIZO_PCICTRL_SBH_INT); | |
1446 | ||
1447 | /* Enable PCI Error interrupts and clear error | |
1448 | * bits for each PBM. | |
1449 | */ | |
1450 | tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL); | |
1451 | tmp |= err_mask; | |
1452 | tmp &= ~err_no_mask; | |
1453 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1454 | ||
1455 | schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, | |
1456 | (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | | |
1457 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | | |
1458 | SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | | |
1459 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | | |
1460 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | | |
1461 | SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS)); | |
1462 | ||
1463 | tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL); | |
1464 | tmp |= err_mask; | |
1465 | tmp &= ~err_no_mask; | |
1466 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1467 | ||
1468 | schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, | |
1469 | (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA | | |
1470 | SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR | | |
1471 | SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS | | |
1472 | SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA | | |
1473 | SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR | | |
1474 | SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS)); | |
1475 | ||
1476 | /* Make all Safari error conditions fatal except unmapped | |
1477 | * errors which we make generate interrupts. | |
1478 | */ | |
1479 | err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS | | |
1480 | BUS_ERROR_BADMA | BUS_ERROR_BADMB | | |
1481 | BUS_ERROR_BADMC | | |
1482 | BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | | |
1483 | BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB | | |
1484 | BUS_ERROR_CIQTO | | |
1485 | BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO | | |
1486 | BUS_ERROR_UFPQTO | BUS_ERROR_APERR | | |
1487 | BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT | | |
1488 | BUS_ERROR_ILL); | |
1489 | #if 1 | |
1490 | /* XXX Something wrong with some Excalibur systems | |
1491 | * XXX Sun is shipping. The behavior on a 2-cpu | |
1492 | * XXX machine is that both CPU1 parity error bits | |
1493 | * XXX are set and are immediately set again when | |
1494 | * XXX their error status bits are cleared. Just | |
1495 | * XXX ignore them for now. -DaveM | |
1496 | */ | |
1497 | err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB | | |
1498 | BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB); | |
1499 | #endif | |
1500 | ||
1501 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL, | |
1502 | (SCHIZO_SAFERRCTRL_EN | err_mask)); | |
1503 | ||
1504 | schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL, | |
1505 | (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP))); | |
1506 | } | |
1507 | ||
085ae41f | 1508 | static void pbm_config_busmastering(struct pci_pbm_info *pbm) |
1da177e4 LT |
1509 | { |
1510 | u8 *addr; | |
1511 | ||
1512 | /* Set cache-line size to 64 bytes, this is actually | |
1513 | * a nop but I do it for completeness. | |
1514 | */ | |
1515 | addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, | |
1516 | 0, PCI_CACHE_LINE_SIZE); | |
1517 | pci_config_write8(addr, 64 / sizeof(u32)); | |
1518 | ||
1519 | /* Set PBM latency timer to 64 PCI clocks. */ | |
1520 | addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno, | |
1521 | 0, PCI_LATENCY_TIMER); | |
1522 | pci_config_write8(addr, 64); | |
1523 | } | |
1524 | ||
085ae41f DM |
1525 | static void pbm_scan_bus(struct pci_controller_info *p, |
1526 | struct pci_pbm_info *pbm) | |
1da177e4 LT |
1527 | { |
1528 | struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL); | |
1529 | ||
1530 | if (!cookie) { | |
1531 | prom_printf("%s: Critical allocation failure.\n", pbm->name); | |
1532 | prom_halt(); | |
1533 | } | |
1534 | ||
1535 | /* All we care about is the PBM. */ | |
1536 | memset(cookie, 0, sizeof(*cookie)); | |
1537 | cookie->pbm = pbm; | |
1538 | ||
1539 | pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno, | |
1540 | p->pci_ops, | |
1541 | pbm); | |
1542 | pci_fixup_host_bridge_self(pbm->pci_bus); | |
1543 | pbm->pci_bus->self->sysdata = cookie; | |
1544 | ||
1545 | pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node); | |
1546 | pci_record_assignments(pbm, pbm->pci_bus); | |
1547 | pci_assign_unassigned(pbm, pbm->pci_bus); | |
1548 | pci_fixup_irq(pbm, pbm->pci_bus); | |
1549 | pci_determine_66mhz_disposition(pbm, pbm->pci_bus); | |
1550 | pci_setup_busmastering(pbm, pbm->pci_bus); | |
1551 | } | |
1552 | ||
085ae41f DM |
1553 | static void __schizo_scan_bus(struct pci_controller_info *p, |
1554 | int chip_type) | |
1da177e4 LT |
1555 | { |
1556 | if (!p->pbm_B.prom_node || !p->pbm_A.prom_node) { | |
1557 | printk("PCI: Only one PCI bus module of controller found.\n"); | |
1558 | printk("PCI: Ignoring entire controller.\n"); | |
1559 | return; | |
1560 | } | |
1561 | ||
1562 | pbm_config_busmastering(&p->pbm_B); | |
1563 | p->pbm_B.is_66mhz_capable = | |
1564 | prom_getbool(p->pbm_B.prom_node, "66mhz-capable"); | |
1565 | pbm_config_busmastering(&p->pbm_A); | |
1566 | p->pbm_A.is_66mhz_capable = | |
1567 | prom_getbool(p->pbm_A.prom_node, "66mhz-capable"); | |
1568 | pbm_scan_bus(p, &p->pbm_B); | |
1569 | pbm_scan_bus(p, &p->pbm_A); | |
1570 | ||
1571 | /* After the PCI bus scan is complete, we can register | |
1572 | * the error interrupt handlers. | |
1573 | */ | |
1574 | if (chip_type == PBM_CHIP_TYPE_TOMATILLO) | |
1575 | tomatillo_register_error_handlers(p); | |
1576 | else | |
1577 | schizo_register_error_handlers(p); | |
1578 | } | |
1579 | ||
085ae41f | 1580 | static void schizo_scan_bus(struct pci_controller_info *p) |
1da177e4 LT |
1581 | { |
1582 | __schizo_scan_bus(p, PBM_CHIP_TYPE_SCHIZO); | |
1583 | } | |
1584 | ||
085ae41f | 1585 | static void tomatillo_scan_bus(struct pci_controller_info *p) |
1da177e4 LT |
1586 | { |
1587 | __schizo_scan_bus(p, PBM_CHIP_TYPE_TOMATILLO); | |
1588 | } | |
1589 | ||
085ae41f | 1590 | static void schizo_base_address_update(struct pci_dev *pdev, int resource) |
1da177e4 LT |
1591 | { |
1592 | struct pcidev_cookie *pcp = pdev->sysdata; | |
1593 | struct pci_pbm_info *pbm = pcp->pbm; | |
1594 | struct resource *res, *root; | |
1595 | u32 reg; | |
1596 | int where, size, is_64bit; | |
1597 | ||
1598 | res = &pdev->resource[resource]; | |
1599 | if (resource < 6) { | |
1600 | where = PCI_BASE_ADDRESS_0 + (resource * 4); | |
1601 | } else if (resource == PCI_ROM_RESOURCE) { | |
1602 | where = pdev->rom_base_reg; | |
1603 | } else { | |
1604 | /* Somebody might have asked allocation of a non-standard resource */ | |
1605 | return; | |
1606 | } | |
1607 | ||
1608 | is_64bit = 0; | |
1609 | if (res->flags & IORESOURCE_IO) | |
1610 | root = &pbm->io_space; | |
1611 | else { | |
1612 | root = &pbm->mem_space; | |
1613 | if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) | |
1614 | == PCI_BASE_ADDRESS_MEM_TYPE_64) | |
1615 | is_64bit = 1; | |
1616 | } | |
1617 | ||
1618 | size = res->end - res->start; | |
1619 | pci_read_config_dword(pdev, where, ®); | |
1620 | reg = ((reg & size) | | |
1621 | (((u32)(res->start - root->start)) & ~size)); | |
1622 | if (resource == PCI_ROM_RESOURCE) { | |
1623 | reg |= PCI_ROM_ADDRESS_ENABLE; | |
1624 | res->flags |= IORESOURCE_ROM_ENABLE; | |
1625 | } | |
1626 | pci_write_config_dword(pdev, where, reg); | |
1627 | ||
1628 | /* This knows that the upper 32-bits of the address | |
1629 | * must be zero. Our PCI common layer enforces this. | |
1630 | */ | |
1631 | if (is_64bit) | |
1632 | pci_write_config_dword(pdev, where + 4, 0); | |
1633 | } | |
1634 | ||
085ae41f DM |
1635 | static void schizo_resource_adjust(struct pci_dev *pdev, |
1636 | struct resource *res, | |
1637 | struct resource *root) | |
1da177e4 LT |
1638 | { |
1639 | res->start += root->start; | |
1640 | res->end += root->start; | |
1641 | } | |
1642 | ||
1643 | /* Use ranges property to determine where PCI MEM, I/O, and Config | |
1644 | * space are for this PCI bus module. | |
1645 | */ | |
1646 | static void schizo_determine_mem_io_space(struct pci_pbm_info *pbm) | |
1647 | { | |
1648 | int i, saw_cfg, saw_mem, saw_io; | |
1649 | ||
1650 | saw_cfg = saw_mem = saw_io = 0; | |
1651 | for (i = 0; i < pbm->num_pbm_ranges; i++) { | |
1652 | struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i]; | |
1653 | unsigned long a; | |
1654 | int type; | |
1655 | ||
1656 | type = (pr->child_phys_hi >> 24) & 0x3; | |
1657 | a = (((unsigned long)pr->parent_phys_hi << 32UL) | | |
1658 | ((unsigned long)pr->parent_phys_lo << 0UL)); | |
1659 | ||
1660 | switch (type) { | |
1661 | case 0: | |
1662 | /* PCI config space, 16MB */ | |
1663 | pbm->config_space = a; | |
1664 | saw_cfg = 1; | |
1665 | break; | |
1666 | ||
1667 | case 1: | |
1668 | /* 16-bit IO space, 16MB */ | |
1669 | pbm->io_space.start = a; | |
1670 | pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL); | |
1671 | pbm->io_space.flags = IORESOURCE_IO; | |
1672 | saw_io = 1; | |
1673 | break; | |
1674 | ||
1675 | case 2: | |
1676 | /* 32-bit MEM space, 2GB */ | |
1677 | pbm->mem_space.start = a; | |
1678 | pbm->mem_space.end = a + (0x80000000UL - 1UL); | |
1679 | pbm->mem_space.flags = IORESOURCE_MEM; | |
1680 | saw_mem = 1; | |
1681 | break; | |
1682 | ||
1683 | default: | |
1684 | break; | |
1685 | }; | |
1686 | } | |
1687 | ||
1688 | if (!saw_cfg || !saw_io || !saw_mem) { | |
1689 | prom_printf("%s: Fatal error, missing %s PBM range.\n", | |
1690 | pbm->name, | |
1691 | ((!saw_cfg ? | |
1692 | "CFG" : | |
1693 | (!saw_io ? | |
1694 | "IO" : "MEM")))); | |
1695 | prom_halt(); | |
1696 | } | |
1697 | ||
1698 | printk("%s: PCI CFG[%lx] IO[%lx] MEM[%lx]\n", | |
1699 | pbm->name, | |
1700 | pbm->config_space, | |
1701 | pbm->io_space.start, | |
1702 | pbm->mem_space.start); | |
1703 | } | |
1704 | ||
085ae41f DM |
1705 | static void pbm_register_toplevel_resources(struct pci_controller_info *p, |
1706 | struct pci_pbm_info *pbm) | |
1da177e4 LT |
1707 | { |
1708 | pbm->io_space.name = pbm->mem_space.name = pbm->name; | |
1709 | ||
1710 | request_resource(&ioport_resource, &pbm->io_space); | |
1711 | request_resource(&iomem_resource, &pbm->mem_space); | |
1712 | pci_register_legacy_regions(&pbm->io_space, | |
1713 | &pbm->mem_space); | |
1714 | } | |
1715 | ||
1716 | #define SCHIZO_STRBUF_CONTROL (0x02800UL) | |
1717 | #define SCHIZO_STRBUF_FLUSH (0x02808UL) | |
1718 | #define SCHIZO_STRBUF_FSYNC (0x02810UL) | |
1719 | #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL) | |
1720 | #define SCHIZO_STRBUF_CTXMATCH (0x10000UL) | |
1721 | ||
1722 | static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm) | |
1723 | { | |
1724 | unsigned long base = pbm->pbm_regs; | |
1725 | u64 control; | |
1726 | ||
1727 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { | |
1728 | /* TOMATILLO lacks streaming cache. */ | |
1729 | return; | |
1730 | } | |
1731 | ||
1732 | /* SCHIZO has context flushing. */ | |
1733 | pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL; | |
1734 | pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH; | |
1735 | pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC; | |
1736 | pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH; | |
1737 | pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH; | |
1738 | ||
1739 | pbm->stc.strbuf_flushflag = (volatile unsigned long *) | |
1740 | ((((unsigned long)&pbm->stc.__flushflag_buf[0]) | |
1741 | + 63UL) | |
1742 | & ~63UL); | |
1743 | pbm->stc.strbuf_flushflag_pa = (unsigned long) | |
1744 | __pa(pbm->stc.strbuf_flushflag); | |
1745 | ||
1746 | /* Turn off LRU locking and diag mode, enable the | |
1747 | * streaming buffer and leave the rerun-disable | |
1748 | * setting however OBP set it. | |
1749 | */ | |
1750 | control = schizo_read(pbm->stc.strbuf_control); | |
1751 | control &= ~(SCHIZO_STRBUF_CTRL_LPTR | | |
1752 | SCHIZO_STRBUF_CTRL_LENAB | | |
1753 | SCHIZO_STRBUF_CTRL_DENAB); | |
1754 | control |= SCHIZO_STRBUF_CTRL_ENAB; | |
1755 | schizo_write(pbm->stc.strbuf_control, control); | |
1756 | ||
1757 | pbm->stc.strbuf_enabled = 1; | |
1758 | } | |
1759 | ||
1760 | #define SCHIZO_IOMMU_CONTROL (0x00200UL) | |
1761 | #define SCHIZO_IOMMU_TSBBASE (0x00208UL) | |
1762 | #define SCHIZO_IOMMU_FLUSH (0x00210UL) | |
1763 | #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL) | |
1764 | ||
1765 | static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm) | |
1766 | { | |
1767 | struct pci_iommu *iommu = pbm->iommu; | |
1768 | unsigned long tsbbase, i, tagbase, database, order; | |
1769 | u32 vdma[2], dma_mask; | |
1770 | u64 control; | |
1771 | int err, tsbsize; | |
1772 | ||
1773 | err = prom_getproperty(pbm->prom_node, "virtual-dma", | |
1774 | (char *)&vdma[0], sizeof(vdma)); | |
1775 | if (err == 0 || err == -1) { | |
1776 | /* No property, use default values. */ | |
1777 | vdma[0] = 0xc0000000; | |
1778 | vdma[1] = 0x40000000; | |
1779 | } | |
1780 | ||
1781 | dma_mask = vdma[0]; | |
1782 | switch (vdma[1]) { | |
1783 | case 0x20000000: | |
1784 | dma_mask |= 0x1fffffff; | |
1785 | tsbsize = 64; | |
1786 | break; | |
1787 | ||
1788 | case 0x40000000: | |
1789 | dma_mask |= 0x3fffffff; | |
1790 | tsbsize = 128; | |
1791 | break; | |
1792 | ||
1793 | case 0x80000000: | |
1794 | dma_mask |= 0x7fffffff; | |
1795 | tsbsize = 128; | |
1796 | break; | |
1797 | ||
1798 | default: | |
1799 | prom_printf("SCHIZO: strange virtual-dma size.\n"); | |
1800 | prom_halt(); | |
1801 | }; | |
1802 | ||
1803 | /* Setup initial software IOMMU state. */ | |
1804 | spin_lock_init(&iommu->lock); | |
7c963ad1 | 1805 | iommu->ctx_lowest_free = 1; |
1da177e4 LT |
1806 | |
1807 | /* Register addresses, SCHIZO has iommu ctx flushing. */ | |
1808 | iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL; | |
1809 | iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE; | |
1810 | iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH; | |
1811 | iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH; | |
1812 | ||
1813 | /* We use the main control/status register of SCHIZO as the write | |
1814 | * completion register. | |
1815 | */ | |
1816 | iommu->write_complete_reg = pbm->controller_regs + 0x10000UL; | |
1817 | ||
1818 | /* | |
1819 | * Invalidate TLB Entries. | |
1820 | */ | |
1821 | control = schizo_read(iommu->iommu_control); | |
1822 | control |= SCHIZO_IOMMU_CTRL_DENAB; | |
1823 | schizo_write(iommu->iommu_control, control); | |
1824 | ||
1825 | tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA; | |
1826 | ||
1827 | for(i = 0; i < 16; i++) { | |
1828 | schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0); | |
1829 | schizo_write(pbm->pbm_regs + database + (i * 8UL), 0); | |
1830 | } | |
1831 | ||
1832 | /* Leave diag mode enabled for full-flushing done | |
1833 | * in pci_iommu.c | |
1834 | */ | |
1835 | ||
1836 | iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0); | |
1837 | if (!iommu->dummy_page) { | |
1838 | prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n"); | |
1839 | prom_halt(); | |
1840 | } | |
1841 | memset((void *)iommu->dummy_page, 0, PAGE_SIZE); | |
1842 | iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page); | |
1843 | ||
1844 | /* Using assumed page size 8K with 128K entries we need 1MB iommu page | |
1845 | * table (128K ioptes * 8 bytes per iopte). This is | |
1846 | * page order 7 on UltraSparc. | |
1847 | */ | |
1848 | order = get_order(tsbsize * 8 * 1024); | |
1849 | tsbbase = __get_free_pages(GFP_KERNEL, order); | |
1850 | if (!tsbbase) { | |
1851 | prom_printf("%s: Error, gfp(tsb) failed.\n", pbm->name); | |
1852 | prom_halt(); | |
1853 | } | |
1854 | ||
1855 | iommu->page_table = (iopte_t *)tsbbase; | |
1856 | iommu->page_table_map_base = vdma[0]; | |
1857 | iommu->dma_addr_mask = dma_mask; | |
1858 | pci_iommu_table_init(iommu, PAGE_SIZE << order); | |
1859 | ||
1860 | switch (tsbsize) { | |
1861 | case 64: | |
1862 | iommu->page_table_sz_bits = 16; | |
1863 | break; | |
1864 | ||
1865 | case 128: | |
1866 | iommu->page_table_sz_bits = 17; | |
1867 | break; | |
1868 | ||
1869 | default: | |
1870 | prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize); | |
1871 | prom_halt(); | |
1872 | break; | |
1873 | }; | |
1874 | ||
1875 | /* We start with no consistent mappings. */ | |
1876 | iommu->lowest_consistent_map = | |
1877 | 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS); | |
1878 | ||
1879 | for (i = 0; i < PBM_NCLUSTERS; i++) { | |
1880 | iommu->alloc_info[i].flush = 0; | |
1881 | iommu->alloc_info[i].next = 0; | |
1882 | } | |
1883 | ||
1884 | schizo_write(iommu->iommu_tsbbase, __pa(tsbbase)); | |
1885 | ||
1886 | control = schizo_read(iommu->iommu_control); | |
1887 | control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ); | |
1888 | switch (tsbsize) { | |
1889 | case 64: | |
1890 | control |= SCHIZO_IOMMU_TSBSZ_64K; | |
1891 | break; | |
1892 | case 128: | |
1893 | control |= SCHIZO_IOMMU_TSBSZ_128K; | |
1894 | break; | |
1895 | }; | |
1896 | ||
1897 | control |= SCHIZO_IOMMU_CTRL_ENAB; | |
1898 | schizo_write(iommu->iommu_control, control); | |
1899 | } | |
1900 | ||
1901 | #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL) | |
1902 | #define SCHIZO_IRQ_RETRY_INF 0xffUL | |
1903 | ||
1904 | #define SCHIZO_PCI_DIAG (0x2020UL) | |
1905 | #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */ | |
1906 | #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */ | |
1907 | #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */ | |
1908 | #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */ | |
1909 | #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */ | |
1910 | #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */ | |
1911 | #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */ | |
1912 | #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */ | |
1913 | #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */ | |
1914 | ||
1915 | #define TOMATILLO_PCI_IOC_CSR (0x2248UL) | |
1916 | #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL | |
1917 | #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL | |
1918 | #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL | |
1919 | #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL | |
1920 | #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL | |
1921 | #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL | |
1922 | #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL | |
1923 | #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL | |
1924 | #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL | |
1925 | #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL | |
1926 | #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL | |
1927 | #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL | |
1928 | #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL | |
1929 | #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL | |
1930 | #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL | |
1931 | ||
1932 | #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL) | |
1933 | #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL) | |
1934 | ||
085ae41f | 1935 | static void schizo_pbm_hw_init(struct pci_pbm_info *pbm) |
1da177e4 LT |
1936 | { |
1937 | u64 tmp; | |
1938 | ||
864ae180 | 1939 | schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5); |
1da177e4 | 1940 | |
1da177e4 | 1941 | tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL); |
1da177e4 | 1942 | |
9fba62a5 DM |
1943 | /* Enable arbiter for all PCI slots. */ |
1944 | tmp |= 0xff; | |
1945 | ||
1da177e4 LT |
1946 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && |
1947 | pbm->chip_version >= 0x2) | |
1948 | tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT; | |
1da177e4 LT |
1949 | |
1950 | if (!prom_getbool(pbm->prom_node, "no-bus-parking")) | |
1951 | tmp |= SCHIZO_PCICTRL_PARK; | |
9fba62a5 DM |
1952 | else |
1953 | tmp &= ~SCHIZO_PCICTRL_PARK; | |
1da177e4 LT |
1954 | |
1955 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO && | |
1956 | pbm->chip_version <= 0x1) | |
9fba62a5 | 1957 | tmp |= SCHIZO_PCICTRL_DTO_INT; |
1da177e4 | 1958 | else |
9fba62a5 | 1959 | tmp &= ~SCHIZO_PCICTRL_DTO_INT; |
1da177e4 LT |
1960 | |
1961 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) | |
1962 | tmp |= (SCHIZO_PCICTRL_MRM_PREF | | |
1963 | SCHIZO_PCICTRL_RDO_PREF | | |
1964 | SCHIZO_PCICTRL_RDL_PREF); | |
1965 | ||
1966 | schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp); | |
1967 | ||
1968 | tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG); | |
1969 | tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB | | |
1970 | SCHIZO_PCIDIAG_D_RETRY | | |
1971 | SCHIZO_PCIDIAG_D_INTSYNC); | |
1972 | schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp); | |
1973 | ||
1974 | if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) { | |
1975 | /* Clear prefetch lengths to workaround a bug in | |
1976 | * Jalapeno... | |
1977 | */ | |
1978 | tmp = (TOMATILLO_IOC_PART_WPENAB | | |
1979 | (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) | | |
1980 | TOMATILLO_IOC_RDMULT_CPENAB | | |
1981 | TOMATILLO_IOC_RDONE_CPENAB | | |
1982 | TOMATILLO_IOC_RDLINE_CPENAB); | |
1983 | ||
1984 | schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR, | |
1985 | tmp); | |
1986 | } | |
1987 | } | |
1988 | ||
085ae41f DM |
1989 | static void schizo_pbm_init(struct pci_controller_info *p, |
1990 | int prom_node, u32 portid, | |
1991 | int chip_type) | |
1da177e4 LT |
1992 | { |
1993 | struct linux_prom64_registers pr_regs[4]; | |
1994 | unsigned int busrange[2]; | |
1995 | struct pci_pbm_info *pbm; | |
1996 | const char *chipset_name; | |
1997 | u32 ino_bitmap[2]; | |
1998 | int is_pbm_a; | |
1999 | int err; | |
2000 | ||
2001 | switch (chip_type) { | |
2002 | case PBM_CHIP_TYPE_TOMATILLO: | |
2003 | chipset_name = "TOMATILLO"; | |
2004 | break; | |
2005 | ||
2006 | case PBM_CHIP_TYPE_SCHIZO_PLUS: | |
2007 | chipset_name = "SCHIZO+"; | |
2008 | break; | |
2009 | ||
2010 | case PBM_CHIP_TYPE_SCHIZO: | |
2011 | default: | |
2012 | chipset_name = "SCHIZO"; | |
2013 | break; | |
2014 | }; | |
2015 | ||
2016 | /* For SCHIZO, three OBP regs: | |
2017 | * 1) PBM controller regs | |
2018 | * 2) Schizo front-end controller regs (same for both PBMs) | |
2019 | * 3) PBM PCI config space | |
2020 | * | |
2021 | * For TOMATILLO, four OBP regs: | |
2022 | * 1) PBM controller regs | |
2023 | * 2) Tomatillo front-end controller regs | |
2024 | * 3) PBM PCI config space | |
2025 | * 4) Ichip regs | |
2026 | */ | |
2027 | err = prom_getproperty(prom_node, "reg", | |
2028 | (char *)&pr_regs[0], | |
2029 | sizeof(pr_regs)); | |
2030 | if (err == 0 || err == -1) { | |
2031 | prom_printf("%s: Fatal error, no reg property.\n", | |
2032 | chipset_name); | |
2033 | prom_halt(); | |
2034 | } | |
2035 | ||
2036 | is_pbm_a = ((pr_regs[0].phys_addr & 0x00700000) == 0x00600000); | |
2037 | ||
2038 | if (is_pbm_a) | |
2039 | pbm = &p->pbm_A; | |
2040 | else | |
2041 | pbm = &p->pbm_B; | |
2042 | ||
2043 | pbm->portid = portid; | |
2044 | pbm->parent = p; | |
2045 | pbm->prom_node = prom_node; | |
2046 | pbm->pci_first_slot = 1; | |
2047 | ||
2048 | pbm->chip_type = chip_type; | |
2049 | pbm->chip_version = | |
2050 | prom_getintdefault(prom_node, "version#", 0); | |
2051 | pbm->chip_revision = | |
2052 | prom_getintdefault(prom_node, "module-revision#", 0); | |
2053 | ||
2054 | pbm->pbm_regs = pr_regs[0].phys_addr; | |
2055 | pbm->controller_regs = pr_regs[1].phys_addr - 0x10000UL; | |
2056 | ||
bb6743f4 DM |
2057 | if (chip_type == PBM_CHIP_TYPE_TOMATILLO) |
2058 | pbm->sync_reg = pr_regs[3].phys_addr + 0x1a18UL; | |
2059 | ||
1da177e4 LT |
2060 | sprintf(pbm->name, |
2061 | (chip_type == PBM_CHIP_TYPE_TOMATILLO ? | |
2062 | "TOMATILLO%d PBM%c" : | |
2063 | "SCHIZO%d PBM%c"), | |
2064 | p->index, | |
2065 | (pbm == &p->pbm_A ? 'A' : 'B')); | |
2066 | ||
2067 | printk("%s: ver[%x:%x], portid %x, " | |
2068 | "cregs[%lx] pregs[%lx]\n", | |
2069 | pbm->name, | |
2070 | pbm->chip_version, pbm->chip_revision, | |
2071 | pbm->portid, | |
2072 | pbm->controller_regs, | |
2073 | pbm->pbm_regs); | |
2074 | ||
2075 | schizo_pbm_hw_init(pbm); | |
2076 | ||
2077 | prom_getstring(prom_node, "name", | |
2078 | pbm->prom_name, | |
2079 | sizeof(pbm->prom_name)); | |
2080 | ||
2081 | err = prom_getproperty(prom_node, "ranges", | |
2082 | (char *) pbm->pbm_ranges, | |
2083 | sizeof(pbm->pbm_ranges)); | |
2084 | if (err == 0 || err == -1) { | |
2085 | prom_printf("%s: Fatal error, no ranges property.\n", | |
2086 | pbm->name); | |
2087 | prom_halt(); | |
2088 | } | |
2089 | ||
2090 | pbm->num_pbm_ranges = | |
2091 | (err / sizeof(struct linux_prom_pci_ranges)); | |
2092 | ||
2093 | schizo_determine_mem_io_space(pbm); | |
2094 | pbm_register_toplevel_resources(p, pbm); | |
2095 | ||
2096 | err = prom_getproperty(prom_node, "interrupt-map", | |
2097 | (char *)pbm->pbm_intmap, | |
2098 | sizeof(pbm->pbm_intmap)); | |
2099 | if (err != -1) { | |
2100 | pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap)); | |
2101 | err = prom_getproperty(prom_node, "interrupt-map-mask", | |
2102 | (char *)&pbm->pbm_intmask, | |
2103 | sizeof(pbm->pbm_intmask)); | |
2104 | if (err == -1) { | |
2105 | prom_printf("%s: Fatal error, no " | |
2106 | "interrupt-map-mask.\n", pbm->name); | |
2107 | prom_halt(); | |
2108 | } | |
2109 | } else { | |
2110 | pbm->num_pbm_intmap = 0; | |
2111 | memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask)); | |
2112 | } | |
2113 | ||
2114 | err = prom_getproperty(prom_node, "ino-bitmap", | |
2115 | (char *) &ino_bitmap[0], | |
2116 | sizeof(ino_bitmap)); | |
2117 | if (err == 0 || err == -1) { | |
2118 | prom_printf("%s: Fatal error, no ino-bitmap.\n", pbm->name); | |
2119 | prom_halt(); | |
2120 | } | |
2121 | pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) | | |
2122 | ((u64)ino_bitmap[0] << 0UL)); | |
2123 | ||
2124 | err = prom_getproperty(prom_node, "bus-range", | |
2125 | (char *)&busrange[0], | |
2126 | sizeof(busrange)); | |
2127 | if (err == 0 || err == -1) { | |
2128 | prom_printf("%s: Fatal error, no bus-range.\n", pbm->name); | |
2129 | prom_halt(); | |
2130 | } | |
2131 | pbm->pci_first_busno = busrange[0]; | |
2132 | pbm->pci_last_busno = busrange[1]; | |
2133 | ||
2134 | schizo_pbm_iommu_init(pbm); | |
2135 | schizo_pbm_strbuf_init(pbm); | |
2136 | } | |
2137 | ||
2138 | static inline int portid_compare(u32 x, u32 y, int chip_type) | |
2139 | { | |
2140 | if (chip_type == PBM_CHIP_TYPE_TOMATILLO) { | |
2141 | if (x == (y ^ 1)) | |
2142 | return 1; | |
2143 | return 0; | |
2144 | } | |
2145 | return (x == y); | |
2146 | } | |
2147 | ||
085ae41f | 2148 | static void __schizo_init(int node, char *model_name, int chip_type) |
1da177e4 LT |
2149 | { |
2150 | struct pci_controller_info *p; | |
2151 | struct pci_iommu *iommu; | |
2152 | int is_pbm_a; | |
2153 | u32 portid; | |
2154 | ||
2155 | portid = prom_getintdefault(node, "portid", 0xff); | |
2156 | ||
2157 | for(p = pci_controller_root; p; p = p->next) { | |
2158 | struct pci_pbm_info *pbm; | |
2159 | ||
2160 | if (p->pbm_A.prom_node && p->pbm_B.prom_node) | |
2161 | continue; | |
2162 | ||
2163 | pbm = (p->pbm_A.prom_node ? | |
2164 | &p->pbm_A : | |
2165 | &p->pbm_B); | |
2166 | ||
2167 | if (portid_compare(pbm->portid, portid, chip_type)) { | |
2168 | is_pbm_a = (p->pbm_A.prom_node == 0); | |
2169 | schizo_pbm_init(p, node, portid, chip_type); | |
2170 | return; | |
2171 | } | |
2172 | } | |
2173 | ||
2174 | p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC); | |
2175 | if (!p) { | |
2176 | prom_printf("SCHIZO: Fatal memory allocation error.\n"); | |
2177 | prom_halt(); | |
2178 | } | |
2179 | memset(p, 0, sizeof(*p)); | |
2180 | ||
2181 | iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC); | |
2182 | if (!iommu) { | |
2183 | prom_printf("SCHIZO: Fatal memory allocation error.\n"); | |
2184 | prom_halt(); | |
2185 | } | |
2186 | memset(iommu, 0, sizeof(*iommu)); | |
2187 | p->pbm_A.iommu = iommu; | |
2188 | ||
2189 | iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC); | |
2190 | if (!iommu) { | |
2191 | prom_printf("SCHIZO: Fatal memory allocation error.\n"); | |
2192 | prom_halt(); | |
2193 | } | |
2194 | memset(iommu, 0, sizeof(*iommu)); | |
2195 | p->pbm_B.iommu = iommu; | |
2196 | ||
2197 | p->next = pci_controller_root; | |
2198 | pci_controller_root = p; | |
2199 | ||
2200 | p->index = pci_num_controllers++; | |
2201 | p->pbms_same_domain = 0; | |
2202 | p->scan_bus = (chip_type == PBM_CHIP_TYPE_TOMATILLO ? | |
2203 | tomatillo_scan_bus : | |
2204 | schizo_scan_bus); | |
2205 | p->irq_build = schizo_irq_build; | |
2206 | p->base_address_update = schizo_base_address_update; | |
2207 | p->resource_adjust = schizo_resource_adjust; | |
2208 | p->pci_ops = &schizo_ops; | |
2209 | ||
2210 | /* Like PSYCHO we have a 2GB aligned area for memory space. */ | |
2211 | pci_memspace_mask = 0x7fffffffUL; | |
2212 | ||
2213 | schizo_pbm_init(p, node, portid, chip_type); | |
2214 | } | |
2215 | ||
085ae41f | 2216 | void schizo_init(int node, char *model_name) |
1da177e4 LT |
2217 | { |
2218 | __schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO); | |
2219 | } | |
2220 | ||
085ae41f | 2221 | void schizo_plus_init(int node, char *model_name) |
1da177e4 LT |
2222 | { |
2223 | __schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS); | |
2224 | } | |
2225 | ||
085ae41f | 2226 | void tomatillo_init(int node, char *model_name) |
1da177e4 LT |
2227 | { |
2228 | __schizo_init(node, model_name, PBM_CHIP_TYPE_TOMATILLO); | |
2229 | } |