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sparc64: Get rid of pci_controller_info.
[mirror_ubuntu-bionic-kernel.git] / arch / sparc64 / kernel / pci_schizo.c
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9fd8b647 1/* pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
1da177e4 2 *
6d19c88f 3 * Copyright (C) 2001, 2002, 2003, 2007, 2008 David S. Miller (davem@davemloft.net)
1da177e4
LT		 4 */
5
6#include <linux/kernel.h>
7#include <linux/types.h>
8#include <linux/pci.h>
9#include <linux/init.h>
10#include <linux/slab.h>
11#include <linux/interrupt.h>
764f2579 12#include <linux/of_device.h>
1da177e4 13
1da177e4
LT		 14#include <asm/iommu.h>
15#include <asm/irq.h>
bb6743f4 16#include <asm/pstate.h>
e87dc350 17#include <asm/prom.h>
1da177e4
LT		 18
19#include "pci_impl.h"
20#include "iommu_common.h"
21
6d19c88f
DM		 22#define DRIVER_NAME "schizo"
23#define PFX DRIVER_NAME ": "
24
1da177e4
LT		 25/* All SCHIZO registers are 64-bits. The following accessor
26 * routines are how they are accessed. The REG parameter
27 * is a physical address.
28 */
29#define schizo_read(__reg) \
30({ u64 __ret; \
31 __asm__ __volatile__("ldxa [%1] %2, %0" \
32 : "=r" (__ret) \
33 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 : "memory"); \
35 __ret; \
36})
37#define schizo_write(__reg, __val) \
38 __asm__ __volatile__("stxa %0, [%1] %2" \
39 : /* no outputs */ \
40 : "r" (__val), "r" (__reg), \
41 "i" (ASI_PHYS_BYPASS_EC_E) \
42 : "memory")
43
44/* This is a convention that at least Excalibur and Merlin
45 * follow. I suppose the SCHIZO used in Starcat and friends
46 * will do similar.
47 *
48 * The only way I could see this changing is if the newlink
49 * block requires more space in Schizo's address space than
50 * they predicted, thus requiring an address space reorg when
51 * the newer Schizo is taped out.
52 */
53
54/* Streaming buffer control register. */
55#define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
56#define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
57#define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
58#define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
59#define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
60
61/* IOMMU control register. */
62#define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
63#define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
64#define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
65#define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
66#define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
67#define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
68#define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
69#define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
70#define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
71#define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
72#define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
73#define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
74#define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
75#define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
76#define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
77#define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
78#define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
79#define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
80
81/* Schizo config space address format is nearly identical to
82 * that of PSYCHO:
83 *
84 * 32 24 23 16 15 11 10 8 7 2 1 0
85 * ---------------------------------------------------------
86 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
87 * ---------------------------------------------------------
88 */
89#define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
90#define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
91 (((unsigned long)(BUS) << 16) | \
92 ((unsigned long)(DEVFN) << 8) | \
93 ((unsigned long)(REG)))
94
95static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
96 unsigned char bus,
97 unsigned int devfn,
98 int where)
99{
100 if (!pbm)
101 return NULL;
102 bus -= pbm->pci_first_busno;
103 return (void *)
104 (SCHIZO_CONFIG_BASE(pbm) |
105 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
106}
107
1da177e4
LT		 108/* SCHIZO error handling support. */
109enum schizo_error_type {
110 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
111};
112
113static DEFINE_SPINLOCK(stc_buf_lock);
114static unsigned long stc_error_buf[128];
115static unsigned long stc_tag_buf[16];
116static unsigned long stc_line_buf[16];
117
118#define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
119#define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
120#define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
121#define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
122#define SCHIZO_SERR_INO 0x34 /* Safari interface error */
123
1da177e4
LT		 124#define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
125#define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
126#define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
127
128#define SCHIZO_STCERR_WRITE 0x2UL
129#define SCHIZO_STCERR_READ 0x1UL
130
131#define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
132#define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
133#define SCHIZO_STCTAG_VALID 0x8000000000000000UL
134#define SCHIZO_STCTAG_READ 0x4000000000000000UL
135
136#define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
137#define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
138#define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
139#define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
140#define SCHIZO_STCLINE_VALID 0x0000000000600000UL
141#define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
142
143static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
144 enum schizo_error_type type)
145{
16ce82d8 146 struct strbuf *strbuf = &pbm->stc;
1da177e4
LT		 147 unsigned long regbase = pbm->pbm_regs;
148 unsigned long err_base, tag_base, line_base;
149 u64 control;
150 int i;
151
152 err_base = regbase + SCHIZO_STC_ERR;
153 tag_base = regbase + SCHIZO_STC_TAG;
154 line_base = regbase + SCHIZO_STC_LINE;
155
156 spin_lock(&stc_buf_lock);
157
158 /* This is __REALLY__ dangerous. When we put the
159 * streaming buffer into diagnostic mode to probe
160 * it's tags and error status, we _must_ clear all
161 * of the line tag valid bits before re-enabling
162 * the streaming buffer. If any dirty data lives
163 * in the STC when we do this, we will end up
164 * invalidating it before it has a chance to reach
165 * main memory.
166 */
167 control = schizo_read(strbuf->strbuf_control);
168 schizo_write(strbuf->strbuf_control,
169 (control | SCHIZO_STRBUF_CTRL_DENAB));
170 for (i = 0; i < 128; i++) {
171 unsigned long val;
172
173 val = schizo_read(err_base + (i * 8UL));
174 schizo_write(err_base + (i * 8UL), 0UL);
175 stc_error_buf[i] = val;
176 }
177 for (i = 0; i < 16; i++) {
178 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
179 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
180 schizo_write(tag_base + (i * 8UL), 0UL);
181 schizo_write(line_base + (i * 8UL), 0UL);
182 }
183
184 /* OK, state is logged, exit diagnostic mode. */
185 schizo_write(strbuf->strbuf_control, control);
186
187 for (i = 0; i < 16; i++) {
188 int j, saw_error, first, last;
189
190 saw_error = 0;
191 first = i * 8;
192 last = first + 8;
193 for (j = first; j < last; j++) {
194 unsigned long errval = stc_error_buf[j];
195 if (errval != 0) {
196 saw_error++;
197 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
198 pbm->name,
199 j,
200 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
201 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
202 }
203 }
204 if (saw_error != 0) {
205 unsigned long tagval = stc_tag_buf[i];
206 unsigned long lineval = stc_line_buf[i];
207 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
208 pbm->name,
209 i,
210 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
211 (tagval & SCHIZO_STCTAG_VPN),
212 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
213 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
214
215 /* XXX Should spit out per-bank error information... -DaveM */
216 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
217 "V(%d)FOFN(%d)]\n",
218 pbm->name,
219 i,
220 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
221 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
222 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
223 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
224 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
225 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
226 }
227 }
228
229 spin_unlock(&stc_buf_lock);
230}
231
232/* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
233 * controller level errors.
234 */
235
236#define SCHIZO_IOMMU_TAG 0xa580UL
237#define SCHIZO_IOMMU_DATA 0xa600UL
238
239#define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
240#define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
241#define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
242#define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
243#define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
244#define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
245#define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
246
247#define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
248#define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
249#define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
250
251static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
252 enum schizo_error_type type)
253{
16ce82d8 254 struct iommu *iommu = pbm->iommu;
1da177e4
LT		 255 unsigned long iommu_tag[16];
256 unsigned long iommu_data[16];
257 unsigned long flags;
258 u64 control;
259 int i;
260
261 spin_lock_irqsave(&iommu->lock, flags);
262 control = schizo_read(iommu->iommu_control);
263 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
264 unsigned long base;
265 char *type_string;
266
267 /* Clear the error encountered bit. */
268 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
269 schizo_write(iommu->iommu_control, control);
270
271 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
272 case 0:
273 type_string = "Protection Error";
274 break;
275 case 1:
276 type_string = "Invalid Error";
277 break;
278 case 2:
279 type_string = "TimeOut Error";
280 break;
281 case 3:
282 default:
283 type_string = "ECC Error";
284 break;
285 };
286 printk("%s: IOMMU Error, type[%s]\n",
287 pbm->name, type_string);
288
289 /* Put the IOMMU into diagnostic mode and probe
290 * it's TLB for entries with error status.
291 *
292 * It is very possible for another DVMA to occur
293 * while we do this probe, and corrupt the system
294 * further. But we are so screwed at this point
295 * that we are likely to crash hard anyways, so
296 * get as much diagnostic information to the
297 * console as we can.
298 */
299 schizo_write(iommu->iommu_control,
300 control | SCHIZO_IOMMU_CTRL_DENAB);
301
302 base = pbm->pbm_regs;
303
304 for (i = 0; i < 16; i++) {
305 iommu_tag[i] =
306 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
307 iommu_data[i] =
308 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
309
310 /* Now clear out the entry. */
311 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
312 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
313 }
314
315 /* Leave diagnostic mode. */
316 schizo_write(iommu->iommu_control, control);
317
318 for (i = 0; i < 16; i++) {
319 unsigned long tag, data;
320
321 tag = iommu_tag[i];
322 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
323 continue;
324
325 data = iommu_data[i];
326 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
327 case 0:
328 type_string = "Protection Error";
329 break;
330 case 1:
331 type_string = "Invalid Error";
332 break;
333 case 2:
334 type_string = "TimeOut Error";
335 break;
336 case 3:
337 default:
338 type_string = "ECC Error";
339 break;
340 };
341 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
342 "sz(%dK) vpg(%08lx)]\n",
343 pbm->name, i, type_string,
344 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
345 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
346 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
347 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
348 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
349 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
350 pbm->name, i,
351 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
352 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
353 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
354 }
355 }
356 if (pbm->stc.strbuf_enabled)
357 __schizo_check_stc_error_pbm(pbm, type);
358 spin_unlock_irqrestore(&iommu->lock, flags);
359}
360
d3ae4b5b 361static void schizo_check_iommu_error(struct pci_pbm_info *pbm,
1da177e4
LT		 362 enum schizo_error_type type)
363{
d3ae4b5b
DM		 364 schizo_check_iommu_error_pbm(pbm, type);
365 if (pbm->sibling)
366 schizo_check_iommu_error_pbm(pbm->sibling, type);
1da177e4
LT		 367}
368
369/* Uncorrectable ECC error status gathering. */
370#define SCHIZO_UE_AFSR 0x10030UL
371#define SCHIZO_UE_AFAR 0x10038UL
372
373#define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
374#define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
375#define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
376#define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
377#define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
378#define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
379#define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
380#define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
381#define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
382#define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
383#define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
384#define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
385#define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
386#define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
387
6d24c8dc 388static irqreturn_t schizo_ue_intr(int irq, void *dev_id)
1da177e4 389{
34768bc8 390 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 391 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_UE_AFSR;
392 unsigned long afar_reg = pbm->controller_regs + SCHIZO_UE_AFAR;
1da177e4
LT		 393 unsigned long afsr, afar, error_bits;
394 int reported, limit;
395
396 /* Latch uncorrectable error status. */
397 afar = schizo_read(afar_reg);
398
399 /* If either of the error pending bits are set in the
400 * AFSR, the error status is being actively updated by
401 * the hardware and we must re-read to get a clean value.
402 */
403 limit = 1000;
404 do {
405 afsr = schizo_read(afsr_reg);
406 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
407
408 /* Clear the primary/secondary error status bits. */
409 error_bits = afsr &
410 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
411 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
412 if (!error_bits)
413 return IRQ_NONE;
414 schizo_write(afsr_reg, error_bits);
415
416 /* Log the error. */
6c108f12
DM		 417 printk("%s: Uncorrectable Error, primary error type[%s]\n",
418 pbm->name,
1da177e4
LT		 419 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
420 "PIO" :
421 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
422 "DMA Read" :
423 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
424 "DMA Write" : "???")))));
6c108f12
DM		 425 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
426 pbm->name,
1da177e4
LT		 427 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
428 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
429 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
6c108f12
DM		 430 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
431 pbm->name,
1da177e4
LT		 432 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
433 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
434 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
435 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
436 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
6c108f12
DM		 437 printk("%s: UE AFAR [%016lx]\n", pbm->name, afar);
438 printk("%s: UE Secondary errors [", pbm->name);
1da177e4
LT		 439 reported = 0;
440 if (afsr & SCHIZO_UEAFSR_SPIO) {
441 reported++;
442 printk("(PIO)");
443 }
444 if (afsr & SCHIZO_UEAFSR_SDMA) {
445 reported++;
446 printk("(DMA)");
447 }
448 if (!reported)
449 printk("(none)");
450 printk("]\n");
451
452 /* Interrogate IOMMU for error status. */
d3ae4b5b 453 schizo_check_iommu_error(pbm, UE_ERR);
1da177e4 454
1da177e4
LT		 455 return IRQ_HANDLED;
456}
457
458#define SCHIZO_CE_AFSR 0x10040UL
459#define SCHIZO_CE_AFAR 0x10048UL
460
461#define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
462#define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
463#define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
464#define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
465#define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
466#define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
467#define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
468#define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
469#define SCHIZO_CEAFSR_AID 0x000000001f000000UL
470#define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
471#define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
472#define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
473#define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
474#define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
475
6d24c8dc 476static irqreturn_t schizo_ce_intr(int irq, void *dev_id)
1da177e4 477{
34768bc8 478 struct pci_pbm_info *pbm = dev_id;
34768bc8
DM		 479 unsigned long afsr_reg = pbm->controller_regs + SCHIZO_CE_AFSR;
480 unsigned long afar_reg = pbm->controller_regs + SCHIZO_CE_AFAR;
1da177e4
LT		 481 unsigned long afsr, afar, error_bits;
482 int reported, limit;
483
484 /* Latch error status. */
485 afar = schizo_read(afar_reg);
486
487 /* If either of the error pending bits are set in the
488 * AFSR, the error status is being actively updated by
489 * the hardware and we must re-read to get a clean value.
490 */
491 limit = 1000;
492 do {
493 afsr = schizo_read(afsr_reg);
494 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
495
496 /* Clear primary/secondary error status bits. */
497 error_bits = afsr &
498 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
499 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
500 if (!error_bits)
501 return IRQ_NONE;
502 schizo_write(afsr_reg, error_bits);
503
504 /* Log the error. */
6c108f12
DM		 505 printk("%s: Correctable Error, primary error type[%s]\n",
506 pbm->name,
1da177e4
LT		 507 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
508 "PIO" :
509 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
510 "DMA Read" :
511 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
512 "DMA Write" : "???")))));
513
514 /* XXX Use syndrome and afar to print out module string just like
515 * XXX UDB CE trap handler does... -DaveM
516 */
6c108f12
DM		 517 printk("%s: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
518 pbm->name,
1da177e4
LT		 519 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
520 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
521 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
6c108f12
DM		 522 printk("%s: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
523 pbm->name,
1da177e4
LT		 524 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
525 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
526 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
527 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
528 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
6c108f12
DM		 529 printk("%s: CE AFAR [%016lx]\n", pbm->name, afar);
530 printk("%s: CE Secondary errors [", pbm->name);
1da177e4
LT		 531 reported = 0;
532 if (afsr & SCHIZO_CEAFSR_SPIO) {
533 reported++;
534 printk("(PIO)");
535 }
536 if (afsr & SCHIZO_CEAFSR_SDMA) {
537 reported++;
538 printk("(DMA)");
539 }
540 if (!reported)
541 printk("(none)");
542 printk("]\n");
543
1da177e4
LT		 544 return IRQ_HANDLED;
545}
546
547#define SCHIZO_PCI_AFSR 0x2010UL
548#define SCHIZO_PCI_AFAR 0x2018UL
549
550#define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
551#define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
552#define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
553#define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
554#define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
555#define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
556#define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
557#define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
558#define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
559#define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
560#define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
561#define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
562#define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
563#define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
564#define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
565#define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
566#define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
567
568#define SCHIZO_PCI_CTRL (0x2000UL)
569#define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
9fba62a5 570#define SCHIZO_PCICTRL_DTO_INT (1UL << 61UL) /* Tomatillo */
1da177e4
LT		 571#define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
572#define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
573#define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
574#define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
575#define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
576#define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
577#define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
578#define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
579#define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
580#define SCHIZO_PCICTRL_MRM_PREF (1UL << 30UL) /* Tomatillo */
581#define SCHIZO_PCICTRL_RDO_PREF (1UL << 29UL) /* Tomatillo */
582#define SCHIZO_PCICTRL_RDL_PREF (1UL << 28UL) /* Tomatillo */
583#define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
584#define SCHIZO_PCICTRL_PTO_SHIFT 24UL
585#define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
586#define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
587#define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
588#define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
589#define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
590#define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
591#define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
592#define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
593#define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
594#define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
595#define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
596
597static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
598{
599 unsigned long csr_reg, csr, csr_error_bits;
600 irqreturn_t ret = IRQ_NONE;
601 u16 stat;
602
603 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
604 csr = schizo_read(csr_reg);
605 csr_error_bits =
606 csr & (SCHIZO_PCICTRL_BUS_UNUS |
607 SCHIZO_PCICTRL_TTO_ERR |
608 SCHIZO_PCICTRL_RTRY_ERR |
609 SCHIZO_PCICTRL_DTO_ERR |
610 SCHIZO_PCICTRL_SBH_ERR |
611 SCHIZO_PCICTRL_SERR);
612 if (csr_error_bits) {
613 /* Clear the errors. */
614 schizo_write(csr_reg, csr);
615
616 /* Log 'em. */
617 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
618 printk("%s: Bus unusable error asserted.\n",
619 pbm->name);
620 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
621 printk("%s: PCI TRDY# timeout error asserted.\n",
622 pbm->name);
623 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
624 printk("%s: PCI excessive retry error asserted.\n",
625 pbm->name);
626 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
627 printk("%s: PCI discard timeout error asserted.\n",
628 pbm->name);
629 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
630 printk("%s: PCI streaming byte hole error asserted.\n",
631 pbm->name);
632 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
633 printk("%s: PCI SERR signal asserted.\n",
634 pbm->name);
635 ret = IRQ_HANDLED;
636 }
637 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
638 if (stat & (PCI_STATUS_PARITY |
639 PCI_STATUS_SIG_TARGET_ABORT |
640 PCI_STATUS_REC_TARGET_ABORT |
641 PCI_STATUS_REC_MASTER_ABORT |
642 PCI_STATUS_SIG_SYSTEM_ERROR)) {
643 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
644 pbm->name, stat);
645 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
646 ret = IRQ_HANDLED;
647 }
648 return ret;
649}
650
6d24c8dc 651static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id)
1da177e4
LT		 652{
653 struct pci_pbm_info *pbm = dev_id;
1da177e4
LT		 654 unsigned long afsr_reg, afar_reg, base;
655 unsigned long afsr, afar, error_bits;
656 int reported;
657
658 base = pbm->pbm_regs;
659
660 afsr_reg = base + SCHIZO_PCI_AFSR;
661 afar_reg = base + SCHIZO_PCI_AFAR;
662
663 /* Latch error status. */
664 afar = schizo_read(afar_reg);
665 afsr = schizo_read(afsr_reg);
666
667 /* Clear primary/secondary error status bits. */
668 error_bits = afsr &
669 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
670 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
671 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
672 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
673 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
674 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
675 if (!error_bits)
676 return schizo_pcierr_intr_other(pbm);
677 schizo_write(afsr_reg, error_bits);
678
679 /* Log the error. */
680 printk("%s: PCI Error, primary error type[%s]\n",
681 pbm->name,
682 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
683 "Master Abort" :
684 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
685 "Target Abort" :
686 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
687 "Excessive Retries" :
688 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
689 "Parity Error" :
690 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
691 "Timeout" :
692 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
693 "Bus Unusable" : "???"))))))));
694 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
695 pbm->name,
696 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
697 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
698 ((afsr & SCHIZO_PCIAFSR_CFG) ?
699 "Config" :
700 ((afsr & SCHIZO_PCIAFSR_MEM) ?
701 "Memory" :
702 ((afsr & SCHIZO_PCIAFSR_IO) ?
703 "I/O" : "???"))));
704 printk("%s: PCI AFAR [%016lx]\n",
705 pbm->name, afar);
706 printk("%s: PCI Secondary errors [",
707 pbm->name);
708 reported = 0;
709 if (afsr & SCHIZO_PCIAFSR_SMA) {
710 reported++;
711 printk("(Master Abort)");
712 }
713 if (afsr & SCHIZO_PCIAFSR_STA) {
714 reported++;
715 printk("(Target Abort)");
716 }
717 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
718 reported++;
719 printk("(Excessive Retries)");
720 }
721 if (afsr & SCHIZO_PCIAFSR_SPERR) {
722 reported++;
723 printk("(Parity Error)");
724 }
725 if (afsr & SCHIZO_PCIAFSR_STTO) {
726 reported++;
727 printk("(Timeout)");
728 }
729 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
730 reported++;
731 printk("(Bus Unusable)");
732 }
733 if (!reported)
734 printk("(none)");
735 printk("]\n");
736
737 /* For the error types shown, scan PBM's PCI bus for devices
738 * which have logged that error type.
739 */
740
741 /* If we see a Target Abort, this could be the result of an
742 * IOMMU translation error of some sort. It is extremely
743 * useful to log this information as usually it indicates
744 * a bug in the IOMMU support code or a PCI device driver.
745 */
746 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
d3ae4b5b 747 schizo_check_iommu_error(pbm, PCI_ERR);
6c108f12 748 pci_scan_for_target_abort(pbm, pbm->pci_bus);
1da177e4
LT		 749 }
750 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
6c108f12 751 pci_scan_for_master_abort(pbm, pbm->pci_bus);
1da177e4
LT		 752
753 /* For excessive retries, PSYCHO/PBM will abort the device
754 * and there is no way to specifically check for excessive
755 * retries in the config space status registers. So what
756 * we hope is that we'll catch it via the master/target
757 * abort events.
758 */
759
760 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
6c108f12 761 pci_scan_for_parity_error(pbm, pbm->pci_bus);
1da177e4 762
1da177e4
LT		 763 return IRQ_HANDLED;
764}
765
766#define SCHIZO_SAFARI_ERRLOG 0x10018UL
767
768#define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
769
770#define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
771#define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
772#define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
773#define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
774#define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
775#define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
776#define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
777#define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
778#define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
779#define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
780#define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
781#define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
782#define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
783#define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
784#define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
785#define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
786#define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
787#define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
788#define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
789#define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
790#define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
791#define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
792#define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
793#define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
794#define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
795#define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
796#define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
797#define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
798#define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
799#define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
800#define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
801
802/* We only expect UNMAP errors here. The rest of the Safari errors
803 * are marked fatal and thus cause a system reset.
804 */
6d24c8dc 805static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id)
1da177e4 806{
34768bc8 807 struct pci_pbm_info *pbm = dev_id;
1da177e4
LT		 808 u64 errlog;
809
34768bc8
DM		 810 errlog = schizo_read(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG);
811 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRLOG,
1da177e4
LT		 812 errlog & ~(SAFARI_ERRLOG_ERROUT));
813
814 if (!(errlog & BUS_ERROR_UNMAP)) {
6c108f12
DM		 815 printk("%s: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
816 pbm->name, errlog);
1da177e4 817
1da177e4
LT		 818 return IRQ_HANDLED;
819 }
820
6c108f12
DM		 821 printk("%s: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
822 pbm->name);
d3ae4b5b 823 schizo_check_iommu_error(pbm, SAFARI_ERR);
1da177e4 824
1da177e4
LT		 825 return IRQ_HANDLED;
826}
827
828/* Nearly identical to PSYCHO equivalents... */
829#define SCHIZO_ECC_CTRL 0x10020UL
830#define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
831#define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
832#define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
833
834#define SCHIZO_SAFARI_ERRCTRL 0x10008UL
835#define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
836#define SCHIZO_SAFARI_IRQCTRL 0x10010UL
837#define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
838
34768bc8
DM		 839static int pbm_routes_this_ino(struct pci_pbm_info *pbm, u32 ino)
840{
841 ino &= IMAP_INO;
842
843 if (pbm->ino_bitmap & (1UL << ino))
844 return 1;
845
846 return 0;
847}
848
1da177e4
LT		 849/* How the Tomatillo IRQs are routed around is pure guesswork here.
850 *
851 * All the Tomatillo devices I see in prtconf dumps seem to have only
33ccc190 852 * a single PCI bus unit attached to it. It would seem they are separate
1da177e4
LT		 853 * devices because their PortID (ie. JBUS ID) values are all different
854 * and thus the registers are mapped to totally different locations.
855 *
856 * However, two Tomatillo's look "similar" in that the only difference
857 * in their PortID is the lowest bit.
858 *
859 * So if we were to ignore this lower bit, it certainly looks like two
860 * PCI bus units of the same Tomatillo. I still have not really
861 * figured this out...
862 */
34768bc8 863static void tomatillo_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 864{
34768bc8 865 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1da177e4 866 u64 tmp, err_mask, err_no_mask;
af80318e 867 int err;
1da177e4 868
2b1e5978
DM		 869 /* Tomatillo IRQ property layout is:
870 * 0: PCIERR
871 * 1: UE ERR
872 * 2: CE ERR
873 * 3: SERR
874 * 4: POWER FAIL?
875 */
876
af80318e
DM		 877 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
878 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
879 "TOMATILLO_UE", pbm);
880 if (err)
881 printk(KERN_WARNING "%s: Could not register UE, "
882 "err=%d\n", pbm->name, err);
883 }
884 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
885 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
886 "TOMATILLO_CE", pbm);
887 if (err)
888 printk(KERN_WARNING "%s: Could not register CE, "
889 "err=%d\n", pbm->name, err);
890 }
891 err = 0;
892 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
893 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
894 "TOMATILLO_PCIERR", pbm);
895 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
896 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
897 "TOMATILLO_PCIERR", pbm);
898 }
899 if (err)
900 printk(KERN_WARNING "%s: Could not register PCIERR, "
901 "err=%d\n", pbm->name, err);
902
903 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
904 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
905 "TOMATILLO_SERR", pbm);
906 if (err)
907 printk(KERN_WARNING "%s: Could not register SERR, "
908 "err=%d\n", pbm->name, err);
909 }
34768bc8
DM		 910
911 /* Enable UE and CE interrupts for controller. */
912 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1da177e4
LT		 913 (SCHIZO_ECCCTRL_EE |
914 SCHIZO_ECCCTRL_UE |
915 SCHIZO_ECCCTRL_CE));
916
917 /* Enable PCI Error interrupts and clear error
918 * bits.
919 */
920 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
921 SCHIZO_PCICTRL_TTO_ERR |
922 SCHIZO_PCICTRL_RTRY_ERR |
923 SCHIZO_PCICTRL_SERR |
924 SCHIZO_PCICTRL_EEN);
925
926 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
927
34768bc8 928 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4
LT		 929 tmp |= err_mask;
930 tmp &= ~err_no_mask;
34768bc8 931 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1da177e4
LT		 932
933 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
934 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
935 SCHIZO_PCIAFSR_PTTO |
936 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
937 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
938 SCHIZO_PCIAFSR_STTO);
939
34768bc8 940 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1da177e4
LT		 941
942 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
943 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
944 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
945 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
946 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
947 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
948 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
949 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
950 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
951
34768bc8 952 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1da177e4
LT		 953 (SCHIZO_SAFERRCTRL_EN | err_mask));
954
34768bc8 955 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_IRQCTRL,
1da177e4
LT		 956 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
957}
958
34768bc8 959static void schizo_register_error_handlers(struct pci_pbm_info *pbm)
1da177e4 960{
34768bc8 961 struct of_device *op = of_find_device_by_node(pbm->prom_node);
1da177e4 962 u64 tmp, err_mask, err_no_mask;
af80318e 963 int err;
1da177e4 964
2b1e5978
DM		 965 /* Schizo IRQ property layout is:
966 * 0: PCIERR
967 * 1: UE ERR
968 * 2: CE ERR
969 * 3: SERR
970 * 4: POWER FAIL?
971 */
972
af80318e
DM		 973 if (pbm_routes_this_ino(pbm, SCHIZO_UE_INO)) {
974 err = request_irq(op->irqs[1], schizo_ue_intr, 0,
975 "SCHIZO_UE", pbm);
976 if (err)
977 printk(KERN_WARNING "%s: Could not register UE, "
978 "err=%d\n", pbm->name, err);
979 }
980 if (pbm_routes_this_ino(pbm, SCHIZO_CE_INO)) {
981 err = request_irq(op->irqs[2], schizo_ce_intr, 0,
982 "SCHIZO_CE", pbm);
983 if (err)
984 printk(KERN_WARNING "%s: Could not register CE, "
985 "err=%d\n", pbm->name, err);
986 }
987 err = 0;
988 if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_A_INO)) {
989 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
990 "SCHIZO_PCIERR", pbm);
991 } else if (pbm_routes_this_ino(pbm, SCHIZO_PCIERR_B_INO)) {
992 err = request_irq(op->irqs[0], schizo_pcierr_intr, 0,
993 "SCHIZO_PCIERR", pbm);
994 }
995 if (err)
996 printk(KERN_WARNING "%s: Could not register PCIERR, "
997 "err=%d\n", pbm->name, err);
998
999 if (pbm_routes_this_ino(pbm, SCHIZO_SERR_INO)) {
1000 err = request_irq(op->irqs[3], schizo_safarierr_intr, 0,
1001 "SCHIZO_SERR", pbm);
1002 if (err)
1003 printk(KERN_WARNING "%s: Could not register SERR, "
1004 "err=%d\n", pbm->name, err);
1005 }
1da177e4
LT		 1006
1007 /* Enable UE and CE interrupts for controller. */
34768bc8 1008 schizo_write(pbm->controller_regs + SCHIZO_ECC_CTRL,
1da177e4
LT		 1009 (SCHIZO_ECCCTRL_EE |
1010 SCHIZO_ECCCTRL_UE |
1011 SCHIZO_ECCCTRL_CE));
1012
1013 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1014 SCHIZO_PCICTRL_ESLCK |
1015 SCHIZO_PCICTRL_TTO_ERR |
1016 SCHIZO_PCICTRL_RTRY_ERR |
1017 SCHIZO_PCICTRL_SBH_ERR |
1018 SCHIZO_PCICTRL_SERR |
1019 SCHIZO_PCICTRL_EEN);
1020
1021 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1022 SCHIZO_PCICTRL_SBH_INT);
1023
1024 /* Enable PCI Error interrupts and clear error
1025 * bits for each PBM.
1026 */
34768bc8 1027 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4
LT		 1028 tmp |= err_mask;
1029 tmp &= ~err_no_mask;
34768bc8 1030 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1da177e4 1031
34768bc8 1032 schizo_write(pbm->pbm_regs + SCHIZO_PCI_AFSR,
1da177e4
LT		 1033 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1034 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1035 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1036 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1037 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1038 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1039
1040 /* Make all Safari error conditions fatal except unmapped
1041 * errors which we make generate interrupts.
1042 */
1043 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1044 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1045 BUS_ERROR_BADMC |
1046 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1047 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1048 BUS_ERROR_CIQTO |
1049 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1050 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1051 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1052 BUS_ERROR_ILL);
1053#if 1
1054 /* XXX Something wrong with some Excalibur systems
1055 * XXX Sun is shipping. The behavior on a 2-cpu
1056 * XXX machine is that both CPU1 parity error bits
1057 * XXX are set and are immediately set again when
1058 * XXX their error status bits are cleared. Just
1059 * XXX ignore them for now. -DaveM
1060 */
1061 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1062 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1063#endif
1064
34768bc8 1065 schizo_write(pbm->controller_regs + SCHIZO_SAFARI_ERRCTRL,
1da177e4 1066 (SCHIZO_SAFERRCTRL_EN | err_mask));
1da177e4
LT		 1067}
1068
085ae41f 1069static void pbm_config_busmastering(struct pci_pbm_info *pbm)
1da177e4
LT		 1070{
1071 u8 *addr;
1072
1073 /* Set cache-line size to 64 bytes, this is actually
1074 * a nop but I do it for completeness.
1075 */
1076 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1077 0, PCI_CACHE_LINE_SIZE);
1078 pci_config_write8(addr, 64 / sizeof(u32));
1079
1080 /* Set PBM latency timer to 64 PCI clocks. */
1081 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1082 0, PCI_LATENCY_TIMER);
1083 pci_config_write8(addr, 64);
1084}
1085
e822358a
DM		 1086static void __devinit schizo_scan_bus(struct pci_pbm_info *pbm,
1087 struct device *parent)
1da177e4 1088{
34768bc8
DM		 1089 pbm_config_busmastering(pbm);
1090 pbm->is_66mhz_capable =
1091 (of_find_property(pbm->prom_node, "66mhz-capable", NULL)
e87dc350 1092 != NULL);
bc606f3c 1093
e822358a 1094 pbm->pci_bus = pci_scan_one_pbm(pbm, parent);
1da177e4 1095
34768bc8
DM		 1096 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1097 tomatillo_register_error_handlers(pbm);
1da177e4 1098 else
34768bc8 1099 schizo_register_error_handlers(pbm);
1da177e4
LT		 1100}
1101
1da177e4
LT		 1102#define SCHIZO_STRBUF_CONTROL (0x02800UL)
1103#define SCHIZO_STRBUF_FLUSH (0x02808UL)
1104#define SCHIZO_STRBUF_FSYNC (0x02810UL)
1105#define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1106#define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1107
1108static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1109{
1110 unsigned long base = pbm->pbm_regs;
1111 u64 control;
1112
1113 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1114 /* TOMATILLO lacks streaming cache. */
1115 return;
1116 }
1117
1118 /* SCHIZO has context flushing. */
1119 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1120 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1121 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1122 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1123 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1124
1125 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1126 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1127 + 63UL)
1128 & ~63UL);
1129 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1130 __pa(pbm->stc.strbuf_flushflag);
1131
1132 /* Turn off LRU locking and diag mode, enable the
1133 * streaming buffer and leave the rerun-disable
1134 * setting however OBP set it.
1135 */
1136 control = schizo_read(pbm->stc.strbuf_control);
1137 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1138 SCHIZO_STRBUF_CTRL_LENAB |
1139 SCHIZO_STRBUF_CTRL_DENAB);
1140 control |= SCHIZO_STRBUF_CTRL_ENAB;
1141 schizo_write(pbm->stc.strbuf_control, control);
1142
1143 pbm->stc.strbuf_enabled = 1;
1144}
1145
1146#define SCHIZO_IOMMU_CONTROL (0x00200UL)
1147#define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1148#define SCHIZO_IOMMU_FLUSH (0x00210UL)
1149#define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1150
ad7ad57c 1151static int schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1da177e4 1152{
463801b3 1153 static const u32 vdma_default[] = { 0xc0000000, 0x40000000 };
51e85136 1154 unsigned long i, tagbase, database;
463801b3 1155 struct iommu *iommu = pbm->iommu;
ad7ad57c 1156 int tsbsize, err;
463801b3
DM		 1157 const u32 *vdma;
1158 u32 dma_mask;
1da177e4 1159 u64 control;
1da177e4 1160
463801b3
DM		 1161 vdma = of_get_property(pbm->prom_node, "virtual-dma", NULL);
1162 if (!vdma)
1163 vdma = vdma_default;
1da177e4
LT		 1164
1165 dma_mask = vdma[0];
1166 switch (vdma[1]) {
1167 case 0x20000000:
1168 dma_mask |= 0x1fffffff;
1169 tsbsize = 64;
1170 break;
1171
1172 case 0x40000000:
1173 dma_mask |= 0x3fffffff;
1174 tsbsize = 128;
1175 break;
1176
1177 case 0x80000000:
1178 dma_mask |= 0x7fffffff;
1179 tsbsize = 128;
1180 break;
1181
1182 default:
6d19c88f
DM		 1183 printk(KERN_ERR PFX "Strange virtual-dma size.\n");
1184 return -EINVAL;
1185 }
1da177e4 1186
1da177e4
LT		 1187 /* Register addresses, SCHIZO has iommu ctx flushing. */
1188 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1189 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1190 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
ad7ad57c 1191 iommu->iommu_tags = iommu->iommu_flush + (0xa580UL - 0x0210UL);
1da177e4
LT		 1192 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1193
1194 /* We use the main control/status register of SCHIZO as the write
1195 * completion register.
1196 */
1197 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1198
1199 /*
1200 * Invalidate TLB Entries.
1201 */
1202 control = schizo_read(iommu->iommu_control);
1203 control |= SCHIZO_IOMMU_CTRL_DENAB;
1204 schizo_write(iommu->iommu_control, control);
1205
1206 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1207
6d19c88f 1208 for (i = 0; i < 16; i++) {
1da177e4
LT		 1209 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1210 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1211 }
1212
1213 /* Leave diag mode enabled for full-flushing done
1214 * in pci_iommu.c
1215 */
c1b1a5f1
DM		 1216 err = iommu_table_init(iommu, tsbsize * 8 * 1024, vdma[0], dma_mask,
1217 pbm->numa_node);
6d19c88f
DM		 1218 if (err) {
1219 printk(KERN_ERR PFX "iommu_table_init() fails with %d\n", err);
ad7ad57c 1220 return err;
6d19c88f 1221 }
1da177e4 1222
51e85136 1223 schizo_write(iommu->iommu_tsbbase, __pa(iommu->page_table));
1da177e4
LT		 1224
1225 control = schizo_read(iommu->iommu_control);
1226 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1227 switch (tsbsize) {
1228 case 64:
1229 control |= SCHIZO_IOMMU_TSBSZ_64K;
1230 break;
1231 case 128:
1232 control |= SCHIZO_IOMMU_TSBSZ_128K;
1233 break;
6d19c88f 1234 }
1da177e4
LT		 1235
1236 control |= SCHIZO_IOMMU_CTRL_ENAB;
1237 schizo_write(iommu->iommu_control, control);
ad7ad57c
DM		 1238
1239 return 0;
1da177e4
LT		 1240}
1241
1242#define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1243#define SCHIZO_IRQ_RETRY_INF 0xffUL
1244
1245#define SCHIZO_PCI_DIAG (0x2020UL)
1246#define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1247#define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1248#define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1249#define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1250#define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1251#define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1252#define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1253#define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1254#define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1255
1256#define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1257#define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1258#define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1259#define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1260#define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1261#define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1262#define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1263#define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1264#define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1265#define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1266#define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1267#define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1268#define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1269#define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1270#define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1271#define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1272
1273#define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1274#define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1275
085ae41f 1276static void schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1da177e4
LT		 1277{
1278 u64 tmp;
1279
864ae180 1280 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY, 5);
1da177e4 1281
1da177e4 1282 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1da177e4 1283
9fba62a5
DM		 1284 /* Enable arbiter for all PCI slots. */
1285 tmp |= 0xff;
1286
1da177e4
LT		 1287 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1288 pbm->chip_version >= 0x2)
1289 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1da177e4 1290
463801b3 1291 if (!of_find_property(pbm->prom_node, "no-bus-parking", NULL))
1da177e4 1292 tmp |= SCHIZO_PCICTRL_PARK;
9fba62a5
DM		 1293 else
1294 tmp &= ~SCHIZO_PCICTRL_PARK;
1da177e4
LT		 1295
1296 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1297 pbm->chip_version <= 0x1)
9fba62a5 1298 tmp |= SCHIZO_PCICTRL_DTO_INT;
1da177e4 1299 else
9fba62a5 1300 tmp &= ~SCHIZO_PCICTRL_DTO_INT;
1da177e4
LT		 1301
1302 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1303 tmp |= (SCHIZO_PCICTRL_MRM_PREF |
1304 SCHIZO_PCICTRL_RDO_PREF |
1305 SCHIZO_PCICTRL_RDL_PREF);
1306
1307 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1308
1309 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1310 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1311 SCHIZO_PCIDIAG_D_RETRY |
1312 SCHIZO_PCIDIAG_D_INTSYNC);
1313 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1314
1315 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1316 /* Clear prefetch lengths to workaround a bug in
1317 * Jalapeno...
1318 */
1319 tmp = (TOMATILLO_IOC_PART_WPENAB |
1320 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1321 TOMATILLO_IOC_RDMULT_CPENAB |
1322 TOMATILLO_IOC_RDONE_CPENAB |
1323 TOMATILLO_IOC_RDLINE_CPENAB);
1324
1325 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1326 tmp);
1327 }
1328}
1329
d3ae4b5b 1330static int __devinit schizo_pbm_init(struct pci_pbm_info *pbm,
e822358a 1331 struct of_device *op, u32 portid,
6d19c88f 1332 int chip_type)
1da177e4 1333{
a165b420 1334 const struct linux_prom64_registers *regs;
e822358a 1335 struct device_node *dp = op->node;
1da177e4 1336 const char *chipset_name;
ad7ad57c 1337 int is_pbm_a, err;
1da177e4
LT		 1338
1339 switch (chip_type) {
1340 case PBM_CHIP_TYPE_TOMATILLO:
1341 chipset_name = "TOMATILLO";
1342 break;
1343
1344 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1345 chipset_name = "SCHIZO+";
1346 break;
1347
1348 case PBM_CHIP_TYPE_SCHIZO:
1349 default:
1350 chipset_name = "SCHIZO";
1351 break;
1352 };
1353
1354 /* For SCHIZO, three OBP regs:
1355 * 1) PBM controller regs
1356 * 2) Schizo front-end controller regs (same for both PBMs)
1357 * 3) PBM PCI config space
1358 *
1359 * For TOMATILLO, four OBP regs:
1360 * 1) PBM controller regs
1361 * 2) Tomatillo front-end controller regs
1362 * 3) PBM PCI config space
1363 * 4) Ichip regs
1364 */
bc606f3c 1365 regs = of_get_property(dp, "reg", NULL);
1da177e4 1366
e87dc350 1367 is_pbm_a = ((regs[0].phys_addr & 0x00700000) == 0x00600000);
1da177e4 1368
34768bc8
DM		 1369 pbm->next = pci_pbm_root;
1370 pci_pbm_root = pbm;
1371
c1b1a5f1
DM		 1372 pbm->numa_node = -1;
1373
ca3dd88e
DM		 1374 pbm->pci_ops = &sun4u_pci_ops;
1375 pbm->config_space_reg_bits = 8;
34768bc8 1376
6c108f12
DM		 1377 pbm->index = pci_num_pbms++;
1378
1da177e4 1379 pbm->portid = portid;
e87dc350 1380 pbm->prom_node = dp;
1da177e4
LT		 1381
1382 pbm->chip_type = chip_type;
bc606f3c
DM		 1383 pbm->chip_version = of_getintprop_default(dp, "version#", 0);
1384 pbm->chip_revision = of_getintprop_default(dp, "module-version#", 0);
e87dc350
DM		 1385
1386 pbm->pbm_regs = regs[0].phys_addr;
1387 pbm->controller_regs = regs[1].phys_addr - 0x10000UL;
1da177e4 1388
bb6743f4 1389 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
e87dc350 1390 pbm->sync_reg = regs[3].phys_addr + 0x1a18UL;
bb6743f4 1391
e87dc350 1392 pbm->name = dp->full_name;
1da177e4 1393
e87dc350 1394 printk("%s: %s PCI Bus Module ver[%x:%x]\n",
bc606f3c 1395 pbm->name, chipset_name,
e87dc350 1396 pbm->chip_version, pbm->chip_revision);
1da177e4
LT		 1397
1398 schizo_pbm_hw_init(pbm);
1399
9fd8b647 1400 pci_determine_mem_io_space(pbm);
1da177e4 1401
cfa0652c 1402 pci_get_pbm_props(pbm);
1da177e4 1403
ad7ad57c
DM		 1404 err = schizo_pbm_iommu_init(pbm);
1405 if (err)
1406 return err;
1407
1da177e4 1408 schizo_pbm_strbuf_init(pbm);
ad7ad57c 1409
e822358a 1410 schizo_scan_bus(pbm, &op->dev);
6d19c88f 1411
ad7ad57c 1412 return 0;
1da177e4
LT		 1413}
1414
1415static inline int portid_compare(u32 x, u32 y, int chip_type)
1416{
1417 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1418 if (x == (y ^ 1))
1419 return 1;
1420 return 0;
1421 }
1422 return (x == y);
1423}
1424
d3ae4b5b
DM		 1425static struct pci_pbm_info * __devinit schizo_find_sibling(u32 portid,
1426 int chip_type)
1427{
1428 struct pci_pbm_info *pbm;
1429
1430 for (pbm = pci_pbm_root; pbm; pbm = pbm->next) {
1431 if (portid_compare(pbm->portid, portid, chip_type))
1432 return pbm;
1433 }
1434 return NULL;
1435}
1436
e822358a 1437static int __devinit __schizo_init(struct of_device *op, unsigned long chip_type)
1da177e4 1438{
e822358a 1439 struct device_node *dp = op->node;
34768bc8 1440 struct pci_pbm_info *pbm;
16ce82d8 1441 struct iommu *iommu;
1da177e4 1442 u32 portid;
d7472c38 1443 int err;
1da177e4 1444
bc606f3c 1445 portid = of_getintprop_default(dp, "portid", 0xff);
1da177e4 1446
d7472c38 1447 err = -ENOMEM;
d3ae4b5b
DM		 1448 pbm = kzalloc(sizeof(*pbm), GFP_KERNEL);
1449 if (!pbm) {
1450 printk(KERN_ERR PFX "Cannot allocate pci_pbm_info.\n");
d7472c38 1451 goto out_err;
6d19c88f 1452 }
1da177e4 1453
d3ae4b5b
DM		 1454 pbm->sibling = schizo_find_sibling(portid, chip_type);
1455
1456 iommu = kzalloc(sizeof(struct iommu), GFP_KERNEL);
6d19c88f
DM		 1457 if (!iommu) {
1458 printk(KERN_ERR PFX "Cannot allocate PBM A iommu.\n");
d3ae4b5b 1459 goto out_free_pbm;
6d19c88f 1460 }
bc606f3c 1461
d3ae4b5b 1462 pbm->iommu = iommu;
1da177e4 1463
d3ae4b5b
DM		 1464 if (schizo_pbm_init(pbm, op, portid, chip_type))
1465 goto out_free_iommu;
bc606f3c 1466
d3ae4b5b
DM		 1467 if (pbm->sibling)
1468 pbm->sibling->sibling = pbm;
1da177e4 1469
d3ae4b5b 1470 dev_set_drvdata(&op->dev, pbm);
ad7ad57c 1471
6d19c88f 1472 return 0;
bc606f3c 1473
d3ae4b5b
DM		 1474out_free_iommu:
1475 kfree(pbm->iommu);
d7472c38 1476
d3ae4b5b
DM		 1477out_free_pbm:
1478 kfree(pbm);
d7472c38
DM		 1479
1480out_err:
1481 return err;
1da177e4
LT		 1482}
1483
6d19c88f
DM		 1484static int __devinit schizo_probe(struct of_device *op,
1485 const struct of_device_id *match)
1da177e4 1486{
e822358a 1487 return __schizo_init(op, (unsigned long) match->data);
1da177e4
LT		 1488}
1489
6d19c88f
DM		 1490/* The ordering of this table is very important. Some Tomatillo
1491 * nodes announce that they are compatible with both pci108e,a801
1492 * and pci108e,8001. So list the chips in reverse chronological
1493 * order.
1494 */
fd098316 1495static struct of_device_id __initdata schizo_match[] = {
6d19c88f
DM		 1496 {
1497 .name = "pci",
1498 .compatible = "pci108e,a801",
1499 .data = (void *) PBM_CHIP_TYPE_TOMATILLO,
1500 },
1501 {
1502 .name = "pci",
1503 .compatible = "pci108e,8002",
1504 .data = (void *) PBM_CHIP_TYPE_SCHIZO_PLUS,
1505 },
1506 {
1507 .name = "pci",
1508 .compatible = "pci108e,8001",
1509 .data = (void *) PBM_CHIP_TYPE_SCHIZO,
1510 },
1511 {},
1512};
1da177e4 1513
6d19c88f
DM		 1514static struct of_platform_driver schizo_driver = {
1515 .name = DRIVER_NAME,
1516 .match_table = schizo_match,
1517 .probe = schizo_probe,
1518};
1519
1520static int __init schizo_init(void)
1da177e4 1521{
6d19c88f 1522 return of_register_driver(&schizo_driver, &of_bus_type);
1da177e4 1523}
6d19c88f
DM		 1524
1525subsys_initcall(schizo_init);
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