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1da177e4 LT |
1 | /* $Id: rtrap.S,v 1.61 2002/02/09 19:49:31 davem Exp $ |
2 | * rtrap.S: Preparing for return from trap on Sparc V9. | |
3 | * | |
4 | * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz) | |
5 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
6 | */ | |
7 | ||
8 | #include <linux/config.h> | |
9 | ||
10 | #include <asm/asi.h> | |
11 | #include <asm/pstate.h> | |
12 | #include <asm/ptrace.h> | |
13 | #include <asm/spitfire.h> | |
14 | #include <asm/head.h> | |
15 | #include <asm/visasm.h> | |
16 | #include <asm/processor.h> | |
17 | ||
18 | #define RTRAP_PSTATE (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_IE) | |
19 | #define RTRAP_PSTATE_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV) | |
20 | #define RTRAP_PSTATE_AG_IRQOFF (PSTATE_RMO|PSTATE_PEF|PSTATE_PRIV|PSTATE_AG) | |
21 | ||
22 | /* Register %l6 keeps track of whether we are returning | |
23 | * from a system call or not. It is cleared if we call | |
24 | * do_notify_resume, and it must not be otherwise modified | |
25 | * until we fully commit to returning to userspace. | |
26 | */ | |
27 | ||
28 | .text | |
29 | .align 32 | |
30 | __handle_softirq: | |
31 | call do_softirq | |
32 | nop | |
33 | ba,a,pt %xcc, __handle_softirq_continue | |
34 | nop | |
35 | __handle_preemption: | |
36 | call schedule | |
37 | wrpr %g0, RTRAP_PSTATE, %pstate | |
38 | ba,pt %xcc, __handle_preemption_continue | |
39 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
40 | ||
41 | __handle_user_windows: | |
42 | call fault_in_user_windows | |
43 | wrpr %g0, RTRAP_PSTATE, %pstate | |
44 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
45 | /* Redo sched+sig checks */ | |
46 | ldx [%g6 + TI_FLAGS], %l0 | |
47 | andcc %l0, _TIF_NEED_RESCHED, %g0 | |
48 | ||
49 | be,pt %xcc, 1f | |
50 | nop | |
51 | call schedule | |
52 | wrpr %g0, RTRAP_PSTATE, %pstate | |
53 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
54 | ldx [%g6 + TI_FLAGS], %l0 | |
55 | ||
2d7d5f05 | 56 | 1: andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0 |
1da177e4 LT |
57 | be,pt %xcc, __handle_user_windows_continue |
58 | nop | |
2d7d5f05 DM |
59 | mov %l5, %o1 |
60 | mov %l6, %o2 | |
61 | add %sp, PTREGS_OFF, %o0 | |
62 | mov %l0, %o3 | |
1da177e4 LT |
63 | |
64 | call do_notify_resume | |
65 | wrpr %g0, RTRAP_PSTATE, %pstate | |
66 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
67 | clr %l6 | |
68 | /* Signal delivery can modify pt_regs tstate, so we must | |
69 | * reload it. | |
70 | */ | |
71 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 | |
72 | sethi %hi(0xf << 20), %l4 | |
73 | and %l1, %l4, %l4 | |
74 | ba,pt %xcc, __handle_user_windows_continue | |
75 | ||
76 | andn %l1, %l4, %l1 | |
77 | __handle_perfctrs: | |
78 | call update_perfctrs | |
79 | wrpr %g0, RTRAP_PSTATE, %pstate | |
80 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
81 | ldub [%g6 + TI_WSAVED], %o2 | |
82 | brz,pt %o2, 1f | |
83 | nop | |
84 | /* Redo userwin+sched+sig checks */ | |
85 | call fault_in_user_windows | |
86 | ||
87 | wrpr %g0, RTRAP_PSTATE, %pstate | |
88 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
89 | ldx [%g6 + TI_FLAGS], %l0 | |
90 | andcc %l0, _TIF_NEED_RESCHED, %g0 | |
91 | be,pt %xcc, 1f | |
92 | ||
93 | nop | |
94 | call schedule | |
95 | wrpr %g0, RTRAP_PSTATE, %pstate | |
96 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
97 | ldx [%g6 + TI_FLAGS], %l0 | |
2d7d5f05 | 98 | 1: andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0 |
1da177e4 LT |
99 | |
100 | be,pt %xcc, __handle_perfctrs_continue | |
101 | sethi %hi(TSTATE_PEF), %o0 | |
2d7d5f05 DM |
102 | mov %l5, %o1 |
103 | mov %l6, %o2 | |
104 | add %sp, PTREGS_OFF, %o0 | |
105 | mov %l0, %o3 | |
1da177e4 LT |
106 | call do_notify_resume |
107 | ||
108 | wrpr %g0, RTRAP_PSTATE, %pstate | |
109 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
110 | clr %l6 | |
111 | /* Signal delivery can modify pt_regs tstate, so we must | |
112 | * reload it. | |
113 | */ | |
114 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 | |
115 | sethi %hi(0xf << 20), %l4 | |
116 | and %l1, %l4, %l4 | |
117 | andn %l1, %l4, %l1 | |
118 | ba,pt %xcc, __handle_perfctrs_continue | |
119 | ||
120 | sethi %hi(TSTATE_PEF), %o0 | |
121 | __handle_userfpu: | |
122 | rd %fprs, %l5 | |
123 | andcc %l5, FPRS_FEF, %g0 | |
124 | sethi %hi(TSTATE_PEF), %o0 | |
125 | be,a,pn %icc, __handle_userfpu_continue | |
126 | andn %l1, %o0, %l1 | |
127 | ba,a,pt %xcc, __handle_userfpu_continue | |
128 | ||
129 | __handle_signal: | |
2d7d5f05 DM |
130 | mov %l5, %o1 |
131 | mov %l6, %o2 | |
132 | add %sp, PTREGS_OFF, %o0 | |
133 | mov %l0, %o3 | |
1da177e4 LT |
134 | call do_notify_resume |
135 | wrpr %g0, RTRAP_PSTATE, %pstate | |
136 | wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
137 | clr %l6 | |
138 | ||
139 | /* Signal delivery can modify pt_regs tstate, so we must | |
140 | * reload it. | |
141 | */ | |
142 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 | |
143 | sethi %hi(0xf << 20), %l4 | |
144 | and %l1, %l4, %l4 | |
145 | ba,pt %xcc, __handle_signal_continue | |
146 | andn %l1, %l4, %l1 | |
147 | ||
148 | .align 64 | |
149 | .globl rtrap_irq, rtrap_clr_l6, rtrap, irqsz_patchme, rtrap_xcall | |
150 | rtrap_irq: | |
151 | rtrap_clr_l6: clr %l6 | |
152 | rtrap: | |
d7ce78fd DM |
153 | #ifndef CONFIG_SMP |
154 | sethi %hi(per_cpu____cpu_data), %l0 | |
155 | lduw [%l0 + %lo(per_cpu____cpu_data)], %l1 | |
156 | #else | |
157 | sethi %hi(per_cpu____cpu_data), %l0 | |
158 | or %l0, %lo(per_cpu____cpu_data), %l0 | |
159 | lduw [%l0 + %g5], %l1 | |
160 | #endif | |
1da177e4 LT |
161 | cmp %l1, 0 |
162 | ||
163 | /* mm/ultra.S:xcall_report_regs KNOWS about this load. */ | |
164 | bne,pn %icc, __handle_softirq | |
165 | ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1 | |
166 | __handle_softirq_continue: | |
167 | rtrap_xcall: | |
168 | sethi %hi(0xf << 20), %l4 | |
169 | andcc %l1, TSTATE_PRIV, %l3 | |
170 | and %l1, %l4, %l4 | |
171 | bne,pn %icc, to_kernel | |
172 | andn %l1, %l4, %l1 | |
173 | ||
174 | /* We must hold IRQs off and atomically test schedule+signal | |
175 | * state, then hold them off all the way back to userspace. | |
176 | * If we are returning to kernel, none of this matters. | |
177 | * | |
178 | * If we do not do this, there is a window where we would do | |
179 | * the tests, later the signal/resched event arrives but we do | |
180 | * not process it since we are still in kernel mode. It would | |
181 | * take until the next local IRQ before the signal/resched | |
182 | * event would be handled. | |
183 | * | |
184 | * This also means that if we have to deal with performance | |
185 | * counters or user windows, we have to redo all of these | |
186 | * sched+signal checks with IRQs disabled. | |
187 | */ | |
188 | to_user: wrpr %g0, RTRAP_PSTATE_IRQOFF, %pstate | |
189 | wrpr 0, %pil | |
190 | __handle_preemption_continue: | |
191 | ldx [%g6 + TI_FLAGS], %l0 | |
192 | sethi %hi(_TIF_USER_WORK_MASK), %o0 | |
193 | or %o0, %lo(_TIF_USER_WORK_MASK), %o0 | |
194 | andcc %l0, %o0, %g0 | |
195 | sethi %hi(TSTATE_PEF), %o0 | |
196 | be,pt %xcc, user_nowork | |
197 | andcc %l1, %o0, %g0 | |
198 | andcc %l0, _TIF_NEED_RESCHED, %g0 | |
199 | bne,pn %xcc, __handle_preemption | |
2d7d5f05 | 200 | andcc %l0, (_TIF_SIGPENDING | _TIF_RESTORE_SIGMASK), %g0 |
1da177e4 LT |
201 | bne,pn %xcc, __handle_signal |
202 | __handle_signal_continue: | |
203 | ldub [%g6 + TI_WSAVED], %o2 | |
204 | brnz,pn %o2, __handle_user_windows | |
205 | nop | |
206 | __handle_user_windows_continue: | |
207 | ldx [%g6 + TI_FLAGS], %l5 | |
208 | andcc %l5, _TIF_PERFCTR, %g0 | |
209 | sethi %hi(TSTATE_PEF), %o0 | |
210 | bne,pn %xcc, __handle_perfctrs | |
211 | __handle_perfctrs_continue: | |
212 | andcc %l1, %o0, %g0 | |
213 | ||
214 | /* This fpdepth clear is necessary for non-syscall rtraps only */ | |
215 | user_nowork: | |
216 | bne,pn %xcc, __handle_userfpu | |
217 | stb %g0, [%g6 + TI_FPDEPTH] | |
218 | __handle_userfpu_continue: | |
219 | ||
220 | rt_continue: ldx [%sp + PTREGS_OFF + PT_V9_G1], %g1 | |
221 | ldx [%sp + PTREGS_OFF + PT_V9_G2], %g2 | |
222 | ||
223 | ldx [%sp + PTREGS_OFF + PT_V9_G3], %g3 | |
224 | ldx [%sp + PTREGS_OFF + PT_V9_G4], %g4 | |
225 | ldx [%sp + PTREGS_OFF + PT_V9_G5], %g5 | |
56fb4df6 DM |
226 | brz,pt %l3, 1f |
227 | nop | |
228 | /* Must do this before thread reg is clobbered below. */ | |
ffe483d5 | 229 | LOAD_PER_CPU_BASE(%g5, %g6, %i0, %i1, %i2) |
74bf4312 DM |
230 | 1: |
231 | ldx [%sp + PTREGS_OFF + PT_V9_G6], %g6 | |
1da177e4 | 232 | ldx [%sp + PTREGS_OFF + PT_V9_G7], %g7 |
936f482a DM |
233 | |
234 | /* Normal globals are restored, go to trap globals. */ | |
235 | 661: wrpr %g0, RTRAP_PSTATE_AG_IRQOFF, %pstate | |
236 | .section .gl_1insn_patch, "ax" | |
237 | .word 661b | |
238 | SET_GL(1) | |
239 | .previous | |
240 | ||
1da177e4 LT |
241 | ldx [%sp + PTREGS_OFF + PT_V9_I0], %i0 |
242 | ldx [%sp + PTREGS_OFF + PT_V9_I1], %i1 | |
243 | ||
244 | ldx [%sp + PTREGS_OFF + PT_V9_I2], %i2 | |
245 | ldx [%sp + PTREGS_OFF + PT_V9_I3], %i3 | |
246 | ldx [%sp + PTREGS_OFF + PT_V9_I4], %i4 | |
247 | ldx [%sp + PTREGS_OFF + PT_V9_I5], %i5 | |
248 | ldx [%sp + PTREGS_OFF + PT_V9_I6], %i6 | |
249 | ldx [%sp + PTREGS_OFF + PT_V9_I7], %i7 | |
250 | ldx [%sp + PTREGS_OFF + PT_V9_TPC], %l2 | |
251 | ldx [%sp + PTREGS_OFF + PT_V9_TNPC], %o2 | |
252 | ||
253 | ld [%sp + PTREGS_OFF + PT_V9_Y], %o3 | |
254 | wr %o3, %g0, %y | |
255 | srl %l4, 20, %l4 | |
256 | wrpr %l4, 0x0, %pil | |
257 | wrpr %g0, 0x1, %tl | |
258 | wrpr %l1, %g0, %tstate | |
259 | wrpr %l2, %g0, %tpc | |
260 | wrpr %o2, %g0, %tnpc | |
261 | ||
262 | brnz,pn %l3, kern_rtt | |
263 | mov PRIMARY_CONTEXT, %l7 | |
264 | ldxa [%l7 + %l7] ASI_DMMU, %l0 | |
0835ae0f DM |
265 | sethi %hi(sparc64_kern_pri_nuc_bits), %l1 |
266 | ldx [%l1 + %lo(sparc64_kern_pri_nuc_bits)], %l1 | |
1da177e4 LT |
267 | or %l0, %l1, %l0 |
268 | stxa %l0, [%l7] ASI_DMMU | |
4da808c3 DM |
269 | sethi %hi(KERNBASE), %l7 |
270 | flush %l7 | |
1da177e4 LT |
271 | rdpr %wstate, %l1 |
272 | rdpr %otherwin, %l2 | |
273 | srl %l1, 3, %l1 | |
274 | ||
275 | wrpr %l2, %g0, %canrestore | |
276 | wrpr %l1, %g0, %wstate | |
314ef685 DM |
277 | brnz,pt %l2, user_rtt_restore |
278 | wrpr %g0, %g0, %otherwin | |
279 | ||
280 | ldx [%g6 + TI_FLAGS], %g3 | |
281 | wr %g0, ASI_AIUP, %asi | |
282 | rdpr %cwp, %g1 | |
283 | andcc %g3, _TIF_32BIT, %g0 | |
284 | sub %g1, 1, %g1 | |
285 | bne,pt %xcc, user_rtt_fill_32bit | |
286 | wrpr %g1, %cwp | |
287 | ba,a,pt %xcc, user_rtt_fill_64bit | |
288 | ||
289 | user_rtt_fill_fixup: | |
290 | rdpr %cwp, %g1 | |
291 | add %g1, 1, %g1 | |
292 | wrpr %g1, 0x0, %cwp | |
293 | ||
294 | rdpr %wstate, %g2 | |
295 | sll %g2, 3, %g2 | |
296 | wrpr %g2, 0x0, %wstate | |
297 | ||
298 | /* We know %canrestore and %otherwin are both zero. */ | |
299 | ||
300 | sethi %hi(sparc64_kern_pri_context), %g2 | |
301 | ldx [%g2 + %lo(sparc64_kern_pri_context)], %g2 | |
302 | mov PRIMARY_CONTEXT, %g1 | |
303 | stxa %g2, [%g1] ASI_DMMU | |
304 | sethi %hi(KERNBASE), %g1 | |
305 | flush %g1 | |
306 | ||
307 | or %g4, FAULT_CODE_WINFIXUP, %g4 | |
308 | stb %g4, [%g6 + TI_FAULT_CODE] | |
309 | stx %g5, [%g6 + TI_FAULT_ADDR] | |
310 | ||
311 | mov %g6, %l1 | |
312 | wrpr %g0, 0x0, %tl | |
313 | wrpr %g0, RTRAP_PSTATE, %pstate | |
936f482a DM |
314 | |
315 | 661: nop | |
316 | .section .gl_1insn_patch, "ax" | |
317 | .word 661b | |
318 | SET_GL(0) | |
319 | .previous | |
320 | ||
314ef685 DM |
321 | mov %l1, %g6 |
322 | ldx [%g6 + TI_TASK], %g4 | |
323 | LOAD_PER_CPU_BASE(%g5, %g6, %g1, %g2, %g3) | |
324 | call do_sparc64_fault | |
325 | add %sp, PTREGS_OFF, %o0 | |
326 | ba,pt %xcc, rtrap | |
327 | nop | |
328 | ||
329 | user_rtt_pre_restore: | |
330 | add %g1, 1, %g1 | |
331 | wrpr %g1, 0x0, %cwp | |
332 | ||
333 | user_rtt_restore: | |
1da177e4 LT |
334 | restore |
335 | rdpr %canrestore, %g1 | |
336 | wrpr %g1, 0x0, %cleanwin | |
337 | retry | |
338 | nop | |
339 | ||
314ef685 DM |
340 | kern_rtt: rdpr %canrestore, %g1 |
341 | brz,pn %g1, kern_rtt_fill | |
342 | nop | |
343 | kern_rtt_restore: | |
344 | restore | |
1da177e4 | 345 | retry |
314ef685 | 346 | |
1da177e4 LT |
347 | to_kernel: |
348 | #ifdef CONFIG_PREEMPT | |
349 | ldsw [%g6 + TI_PRE_COUNT], %l5 | |
350 | brnz %l5, kern_fpucheck | |
351 | ldx [%g6 + TI_FLAGS], %l5 | |
352 | andcc %l5, _TIF_NEED_RESCHED, %g0 | |
353 | be,pt %xcc, kern_fpucheck | |
354 | srl %l4, 20, %l5 | |
355 | cmp %l5, 0 | |
356 | bne,pn %xcc, kern_fpucheck | |
357 | sethi %hi(PREEMPT_ACTIVE), %l6 | |
358 | stw %l6, [%g6 + TI_PRE_COUNT] | |
359 | call schedule | |
360 | nop | |
361 | ba,pt %xcc, rtrap | |
362 | stw %g0, [%g6 + TI_PRE_COUNT] | |
363 | #endif | |
364 | kern_fpucheck: ldub [%g6 + TI_FPDEPTH], %l5 | |
365 | brz,pt %l5, rt_continue | |
366 | srl %l5, 1, %o0 | |
367 | add %g6, TI_FPSAVED, %l6 | |
368 | ldub [%l6 + %o0], %l2 | |
369 | sub %l5, 2, %l5 | |
370 | ||
371 | add %g6, TI_GSR, %o1 | |
372 | andcc %l2, (FPRS_FEF|FPRS_DU), %g0 | |
373 | be,pt %icc, 2f | |
374 | and %l2, FPRS_DL, %l6 | |
375 | andcc %l2, FPRS_FEF, %g0 | |
376 | be,pn %icc, 5f | |
377 | sll %o0, 3, %o5 | |
378 | rd %fprs, %g1 | |
379 | ||
380 | wr %g1, FPRS_FEF, %fprs | |
381 | ldx [%o1 + %o5], %g1 | |
382 | add %g6, TI_XFSR, %o1 | |
1da177e4 LT |
383 | sll %o0, 8, %o2 |
384 | add %g6, TI_FPREGS, %o3 | |
385 | brz,pn %l6, 1f | |
386 | add %g6, TI_FPREGS+0x40, %o4 | |
387 | ||
ba639933 | 388 | membar #Sync |
1da177e4 LT |
389 | ldda [%o3 + %o2] ASI_BLK_P, %f0 |
390 | ldda [%o4 + %o2] ASI_BLK_P, %f16 | |
ba639933 | 391 | membar #Sync |
1da177e4 LT |
392 | 1: andcc %l2, FPRS_DU, %g0 |
393 | be,pn %icc, 1f | |
394 | wr %g1, 0, %gsr | |
395 | add %o2, 0x80, %o2 | |
ba639933 | 396 | membar #Sync |
1da177e4 LT |
397 | ldda [%o3 + %o2] ASI_BLK_P, %f32 |
398 | ldda [%o4 + %o2] ASI_BLK_P, %f48 | |
1da177e4 LT |
399 | 1: membar #Sync |
400 | ldx [%o1 + %o5], %fsr | |
401 | 2: stb %l5, [%g6 + TI_FPDEPTH] | |
402 | ba,pt %xcc, rt_continue | |
403 | nop | |
404 | 5: wr %g0, FPRS_FEF, %fprs | |
1da177e4 LT |
405 | sll %o0, 8, %o2 |
406 | ||
407 | add %g6, TI_FPREGS+0x80, %o3 | |
408 | add %g6, TI_FPREGS+0xc0, %o4 | |
ba639933 | 409 | membar #Sync |
1da177e4 LT |
410 | ldda [%o3 + %o2] ASI_BLK_P, %f32 |
411 | ldda [%o4 + %o2] ASI_BLK_P, %f48 | |
412 | membar #Sync | |
413 | wr %g0, FPRS_DU, %fprs | |
414 | ba,pt %xcc, rt_continue | |
415 | stb %l5, [%g6 + TI_FPDEPTH] |