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Commit | Line | Data |
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1da177e4 LT |
1 | /* smp.c: Sparc64 SMP support. |
2 | * | |
3 | * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu) | |
4 | */ | |
5 | ||
6 | #include <linux/module.h> | |
7 | #include <linux/kernel.h> | |
8 | #include <linux/sched.h> | |
9 | #include <linux/mm.h> | |
10 | #include <linux/pagemap.h> | |
11 | #include <linux/threads.h> | |
12 | #include <linux/smp.h> | |
1da177e4 LT |
13 | #include <linux/interrupt.h> |
14 | #include <linux/kernel_stat.h> | |
15 | #include <linux/delay.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/spinlock.h> | |
18 | #include <linux/fs.h> | |
19 | #include <linux/seq_file.h> | |
20 | #include <linux/cache.h> | |
21 | #include <linux/jiffies.h> | |
22 | #include <linux/profile.h> | |
23 | #include <linux/bootmem.h> | |
24 | ||
25 | #include <asm/head.h> | |
26 | #include <asm/ptrace.h> | |
27 | #include <asm/atomic.h> | |
28 | #include <asm/tlbflush.h> | |
29 | #include <asm/mmu_context.h> | |
30 | #include <asm/cpudata.h> | |
31 | ||
32 | #include <asm/irq.h> | |
6d24c8dc | 33 | #include <asm/irq_regs.h> |
1da177e4 LT |
34 | #include <asm/page.h> |
35 | #include <asm/pgtable.h> | |
36 | #include <asm/oplib.h> | |
37 | #include <asm/uaccess.h> | |
38 | #include <asm/timer.h> | |
39 | #include <asm/starfire.h> | |
40 | #include <asm/tlb.h> | |
56fb4df6 | 41 | #include <asm/sections.h> |
07f8e5f3 | 42 | #include <asm/prom.h> |
5cbc3073 | 43 | #include <asm/mdesc.h> |
1da177e4 | 44 | |
1da177e4 LT |
45 | extern void calibrate_delay(void); |
46 | ||
a2f9f6bb DM |
47 | int sparc64_multi_core __read_mostly; |
48 | ||
1da177e4 | 49 | /* Please don't make this stuff initdata!!! --DaveM */ |
777a4475 | 50 | unsigned char boot_cpu_id; |
1da177e4 | 51 | |
c12a8289 AM |
52 | cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE; |
53 | cpumask_t phys_cpu_present_map __read_mostly = CPU_MASK_NONE; | |
8935dced DM |
54 | cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly = |
55 | { [0 ... NR_CPUS-1] = CPU_MASK_NONE }; | |
f78eae2e DM |
56 | cpumask_t cpu_core_map[NR_CPUS] __read_mostly = |
57 | { [0 ... NR_CPUS-1] = CPU_MASK_NONE }; | |
1da177e4 LT |
58 | static cpumask_t smp_commenced_mask; |
59 | static cpumask_t cpu_callout_map; | |
60 | ||
61 | void smp_info(struct seq_file *m) | |
62 | { | |
63 | int i; | |
64 | ||
65 | seq_printf(m, "State:\n"); | |
394e3902 AM |
66 | for_each_online_cpu(i) |
67 | seq_printf(m, "CPU%d:\t\tonline\n", i); | |
1da177e4 LT |
68 | } |
69 | ||
70 | void smp_bogo(struct seq_file *m) | |
71 | { | |
72 | int i; | |
73 | ||
394e3902 AM |
74 | for_each_online_cpu(i) |
75 | seq_printf(m, | |
76 | "Cpu%dBogo\t: %lu.%02lu\n" | |
77 | "Cpu%dClkTck\t: %016lx\n", | |
78 | i, cpu_data(i).udelay_val / (500000/HZ), | |
79 | (cpu_data(i).udelay_val / (5000/HZ)) % 100, | |
80 | i, cpu_data(i).clock_tick); | |
1da177e4 LT |
81 | } |
82 | ||
112f4871 | 83 | extern void setup_sparc64_timer(void); |
1da177e4 LT |
84 | |
85 | static volatile unsigned long callin_flag = 0; | |
86 | ||
1da177e4 LT |
87 | void __init smp_callin(void) |
88 | { | |
89 | int cpuid = hard_smp_processor_id(); | |
90 | ||
56fb4df6 | 91 | __local_per_cpu_offset = __per_cpu_offset(cpuid); |
1da177e4 | 92 | |
4a07e646 | 93 | if (tlb_type == hypervisor) |
490384e7 | 94 | sun4v_ktsb_register(); |
481295f9 | 95 | |
56fb4df6 | 96 | __flush_tlb_all(); |
1da177e4 | 97 | |
112f4871 | 98 | setup_sparc64_timer(); |
1da177e4 | 99 | |
816242da DM |
100 | if (cheetah_pcache_forced_on) |
101 | cheetah_enable_pcache(); | |
102 | ||
1da177e4 LT |
103 | local_irq_enable(); |
104 | ||
105 | calibrate_delay(); | |
5cbc3073 | 106 | cpu_data(cpuid).udelay_val = loops_per_jiffy; |
1da177e4 LT |
107 | callin_flag = 1; |
108 | __asm__ __volatile__("membar #Sync\n\t" | |
109 | "flush %%g6" : : : "memory"); | |
110 | ||
111 | /* Clear this or we will die instantly when we | |
112 | * schedule back to this idler... | |
113 | */ | |
db7d9a4e | 114 | current_thread_info()->new_child = 0; |
1da177e4 LT |
115 | |
116 | /* Attach to the address space of init_task. */ | |
117 | atomic_inc(&init_mm.mm_count); | |
118 | current->active_mm = &init_mm; | |
119 | ||
120 | while (!cpu_isset(cpuid, smp_commenced_mask)) | |
4f07118f | 121 | rmb(); |
1da177e4 LT |
122 | |
123 | cpu_set(cpuid, cpu_online_map); | |
5bfb5d69 NP |
124 | |
125 | /* idle thread is expected to have preempt disabled */ | |
126 | preempt_disable(); | |
1da177e4 LT |
127 | } |
128 | ||
129 | void cpu_panic(void) | |
130 | { | |
131 | printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id()); | |
132 | panic("SMP bolixed\n"); | |
133 | } | |
134 | ||
1da177e4 LT |
135 | /* This tick register synchronization scheme is taken entirely from |
136 | * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit. | |
137 | * | |
138 | * The only change I've made is to rework it so that the master | |
139 | * initiates the synchonization instead of the slave. -DaveM | |
140 | */ | |
141 | ||
142 | #define MASTER 0 | |
143 | #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long)) | |
144 | ||
145 | #define NUM_ROUNDS 64 /* magic value */ | |
146 | #define NUM_ITERS 5 /* likewise */ | |
147 | ||
148 | static DEFINE_SPINLOCK(itc_sync_lock); | |
149 | static unsigned long go[SLAVE + 1]; | |
150 | ||
151 | #define DEBUG_TICK_SYNC 0 | |
152 | ||
153 | static inline long get_delta (long *rt, long *master) | |
154 | { | |
155 | unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0; | |
156 | unsigned long tcenter, t0, t1, tm; | |
157 | unsigned long i; | |
158 | ||
159 | for (i = 0; i < NUM_ITERS; i++) { | |
160 | t0 = tick_ops->get_tick(); | |
161 | go[MASTER] = 1; | |
4f07118f | 162 | membar_storeload(); |
1da177e4 | 163 | while (!(tm = go[SLAVE])) |
4f07118f | 164 | rmb(); |
1da177e4 | 165 | go[SLAVE] = 0; |
4f07118f | 166 | wmb(); |
1da177e4 LT |
167 | t1 = tick_ops->get_tick(); |
168 | ||
169 | if (t1 - t0 < best_t1 - best_t0) | |
170 | best_t0 = t0, best_t1 = t1, best_tm = tm; | |
171 | } | |
172 | ||
173 | *rt = best_t1 - best_t0; | |
174 | *master = best_tm - best_t0; | |
175 | ||
176 | /* average best_t0 and best_t1 without overflow: */ | |
177 | tcenter = (best_t0/2 + best_t1/2); | |
178 | if (best_t0 % 2 + best_t1 % 2 == 2) | |
179 | tcenter++; | |
180 | return tcenter - best_tm; | |
181 | } | |
182 | ||
183 | void smp_synchronize_tick_client(void) | |
184 | { | |
185 | long i, delta, adj, adjust_latency = 0, done = 0; | |
186 | unsigned long flags, rt, master_time_stamp, bound; | |
187 | #if DEBUG_TICK_SYNC | |
188 | struct { | |
189 | long rt; /* roundtrip time */ | |
190 | long master; /* master's timestamp */ | |
191 | long diff; /* difference between midpoint and master's timestamp */ | |
192 | long lat; /* estimate of itc adjustment latency */ | |
193 | } t[NUM_ROUNDS]; | |
194 | #endif | |
195 | ||
196 | go[MASTER] = 1; | |
197 | ||
198 | while (go[MASTER]) | |
4f07118f | 199 | rmb(); |
1da177e4 LT |
200 | |
201 | local_irq_save(flags); | |
202 | { | |
203 | for (i = 0; i < NUM_ROUNDS; i++) { | |
204 | delta = get_delta(&rt, &master_time_stamp); | |
205 | if (delta == 0) { | |
206 | done = 1; /* let's lock on to this... */ | |
207 | bound = rt; | |
208 | } | |
209 | ||
210 | if (!done) { | |
211 | if (i > 0) { | |
212 | adjust_latency += -delta; | |
213 | adj = -delta + adjust_latency/4; | |
214 | } else | |
215 | adj = -delta; | |
216 | ||
112f4871 | 217 | tick_ops->add_tick(adj); |
1da177e4 LT |
218 | } |
219 | #if DEBUG_TICK_SYNC | |
220 | t[i].rt = rt; | |
221 | t[i].master = master_time_stamp; | |
222 | t[i].diff = delta; | |
223 | t[i].lat = adjust_latency/4; | |
224 | #endif | |
225 | } | |
226 | } | |
227 | local_irq_restore(flags); | |
228 | ||
229 | #if DEBUG_TICK_SYNC | |
230 | for (i = 0; i < NUM_ROUNDS; i++) | |
231 | printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n", | |
232 | t[i].rt, t[i].master, t[i].diff, t[i].lat); | |
233 | #endif | |
234 | ||
235 | printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles," | |
236 | "maxerr %lu cycles)\n", smp_processor_id(), delta, rt); | |
237 | } | |
238 | ||
239 | static void smp_start_sync_tick_client(int cpu); | |
240 | ||
241 | static void smp_synchronize_one_tick(int cpu) | |
242 | { | |
243 | unsigned long flags, i; | |
244 | ||
245 | go[MASTER] = 0; | |
246 | ||
247 | smp_start_sync_tick_client(cpu); | |
248 | ||
249 | /* wait for client to be ready */ | |
250 | while (!go[MASTER]) | |
4f07118f | 251 | rmb(); |
1da177e4 LT |
252 | |
253 | /* now let the client proceed into his loop */ | |
254 | go[MASTER] = 0; | |
4f07118f | 255 | membar_storeload(); |
1da177e4 LT |
256 | |
257 | spin_lock_irqsave(&itc_sync_lock, flags); | |
258 | { | |
259 | for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) { | |
260 | while (!go[MASTER]) | |
4f07118f | 261 | rmb(); |
1da177e4 | 262 | go[MASTER] = 0; |
4f07118f | 263 | wmb(); |
1da177e4 | 264 | go[SLAVE] = tick_ops->get_tick(); |
4f07118f | 265 | membar_storeload(); |
1da177e4 LT |
266 | } |
267 | } | |
268 | spin_unlock_irqrestore(&itc_sync_lock, flags); | |
269 | } | |
270 | ||
72aff53f DM |
271 | extern void sun4v_init_mondo_queues(int use_bootmem, int cpu, int alloc, int load); |
272 | ||
1da177e4 LT |
273 | extern unsigned long sparc64_cpu_startup; |
274 | ||
275 | /* The OBP cpu startup callback truncates the 3rd arg cookie to | |
276 | * 32-bits (I think) so to be safe we have it read the pointer | |
277 | * contained here so we work on >4GB machines. -DaveM | |
278 | */ | |
279 | static struct thread_info *cpu_new_thread = NULL; | |
280 | ||
281 | static int __devinit smp_boot_one_cpu(unsigned int cpu) | |
282 | { | |
283 | unsigned long entry = | |
284 | (unsigned long)(&sparc64_cpu_startup); | |
285 | unsigned long cookie = | |
286 | (unsigned long)(&cpu_new_thread); | |
287 | struct task_struct *p; | |
7890f794 | 288 | int timeout, ret; |
1da177e4 LT |
289 | |
290 | p = fork_idle(cpu); | |
291 | callin_flag = 0; | |
f3169641 | 292 | cpu_new_thread = task_thread_info(p); |
1da177e4 LT |
293 | cpu_set(cpu, cpu_callout_map); |
294 | ||
7890f794 | 295 | if (tlb_type == hypervisor) { |
72aff53f DM |
296 | /* Alloc the mondo queues, cpu will load them. */ |
297 | sun4v_init_mondo_queues(0, cpu, 1, 0); | |
298 | ||
7890f794 DM |
299 | prom_startcpu_cpuid(cpu, entry, cookie); |
300 | } else { | |
5cbc3073 | 301 | struct device_node *dp = of_find_node_by_cpuid(cpu); |
7890f794 | 302 | |
07f8e5f3 | 303 | prom_startcpu(dp->node, entry, cookie); |
7890f794 | 304 | } |
1da177e4 LT |
305 | |
306 | for (timeout = 0; timeout < 5000000; timeout++) { | |
307 | if (callin_flag) | |
308 | break; | |
309 | udelay(100); | |
310 | } | |
72aff53f | 311 | |
1da177e4 LT |
312 | if (callin_flag) { |
313 | ret = 0; | |
314 | } else { | |
315 | printk("Processor %d is stuck.\n", cpu); | |
316 | cpu_clear(cpu, cpu_callout_map); | |
317 | ret = -ENODEV; | |
318 | } | |
319 | cpu_new_thread = NULL; | |
320 | ||
321 | return ret; | |
322 | } | |
323 | ||
324 | static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu) | |
325 | { | |
326 | u64 result, target; | |
327 | int stuck, tmp; | |
328 | ||
329 | if (this_is_starfire) { | |
330 | /* map to real upaid */ | |
331 | cpu = (((cpu & 0x3c) << 1) | | |
332 | ((cpu & 0x40) >> 4) | | |
333 | (cpu & 0x3)); | |
334 | } | |
335 | ||
336 | target = (cpu << 14) | 0x70; | |
337 | again: | |
338 | /* Ok, this is the real Spitfire Errata #54. | |
339 | * One must read back from a UDB internal register | |
340 | * after writes to the UDB interrupt dispatch, but | |
341 | * before the membar Sync for that write. | |
342 | * So we use the high UDB control register (ASI 0x7f, | |
343 | * ADDR 0x20) for the dummy read. -DaveM | |
344 | */ | |
345 | tmp = 0x40; | |
346 | __asm__ __volatile__( | |
347 | "wrpr %1, %2, %%pstate\n\t" | |
348 | "stxa %4, [%0] %3\n\t" | |
349 | "stxa %5, [%0+%8] %3\n\t" | |
350 | "add %0, %8, %0\n\t" | |
351 | "stxa %6, [%0+%8] %3\n\t" | |
352 | "membar #Sync\n\t" | |
353 | "stxa %%g0, [%7] %3\n\t" | |
354 | "membar #Sync\n\t" | |
355 | "mov 0x20, %%g1\n\t" | |
356 | "ldxa [%%g1] 0x7f, %%g0\n\t" | |
357 | "membar #Sync" | |
358 | : "=r" (tmp) | |
359 | : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W), | |
360 | "r" (data0), "r" (data1), "r" (data2), "r" (target), | |
361 | "r" (0x10), "0" (tmp) | |
362 | : "g1"); | |
363 | ||
364 | /* NOTE: PSTATE_IE is still clear. */ | |
365 | stuck = 100000; | |
366 | do { | |
367 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
368 | : "=r" (result) | |
369 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
370 | if (result == 0) { | |
371 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
372 | : : "r" (pstate)); | |
373 | return; | |
374 | } | |
375 | stuck -= 1; | |
376 | if (stuck == 0) | |
377 | break; | |
378 | } while (result & 0x1); | |
379 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
380 | : : "r" (pstate)); | |
381 | if (stuck == 0) { | |
382 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
383 | smp_processor_id(), result); | |
384 | } else { | |
385 | udelay(2); | |
386 | goto again; | |
387 | } | |
388 | } | |
389 | ||
390 | static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
391 | { | |
392 | u64 pstate; | |
393 | int i; | |
394 | ||
395 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
396 | for_each_cpu_mask(i, mask) | |
397 | spitfire_xcall_helper(data0, data1, data2, pstate, i); | |
398 | } | |
399 | ||
400 | /* Cheetah now allows to send the whole 64-bytes of data in the interrupt | |
401 | * packet, but we have no use for that. However we do take advantage of | |
402 | * the new pipelining feature (ie. dispatch to multiple cpus simultaneously). | |
403 | */ | |
404 | static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) | |
405 | { | |
406 | u64 pstate, ver; | |
22adb358 | 407 | int nack_busy_id, is_jbus, need_more; |
1da177e4 LT |
408 | |
409 | if (cpus_empty(mask)) | |
410 | return; | |
411 | ||
412 | /* Unfortunately, someone at Sun had the brilliant idea to make the | |
413 | * busy/nack fields hard-coded by ITID number for this Ultra-III | |
414 | * derivative processor. | |
415 | */ | |
416 | __asm__ ("rdpr %%ver, %0" : "=r" (ver)); | |
92704a1c DM |
417 | is_jbus = ((ver >> 32) == __JALAPENO_ID || |
418 | (ver >> 32) == __SERRANO_ID); | |
1da177e4 LT |
419 | |
420 | __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate)); | |
421 | ||
422 | retry: | |
22adb358 | 423 | need_more = 0; |
1da177e4 LT |
424 | __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t" |
425 | : : "r" (pstate), "i" (PSTATE_IE)); | |
426 | ||
427 | /* Setup the dispatch data registers. */ | |
428 | __asm__ __volatile__("stxa %0, [%3] %6\n\t" | |
429 | "stxa %1, [%4] %6\n\t" | |
430 | "stxa %2, [%5] %6\n\t" | |
431 | "membar #Sync\n\t" | |
432 | : /* no outputs */ | |
433 | : "r" (data0), "r" (data1), "r" (data2), | |
434 | "r" (0x40), "r" (0x50), "r" (0x60), | |
435 | "i" (ASI_INTR_W)); | |
436 | ||
437 | nack_busy_id = 0; | |
438 | { | |
439 | int i; | |
440 | ||
441 | for_each_cpu_mask(i, mask) { | |
442 | u64 target = (i << 14) | 0x70; | |
443 | ||
92704a1c | 444 | if (!is_jbus) |
1da177e4 LT |
445 | target |= (nack_busy_id << 24); |
446 | __asm__ __volatile__( | |
447 | "stxa %%g0, [%0] %1\n\t" | |
448 | "membar #Sync\n\t" | |
449 | : /* no outputs */ | |
450 | : "r" (target), "i" (ASI_INTR_W)); | |
451 | nack_busy_id++; | |
22adb358 DM |
452 | if (nack_busy_id == 32) { |
453 | need_more = 1; | |
454 | break; | |
455 | } | |
1da177e4 LT |
456 | } |
457 | } | |
458 | ||
459 | /* Now, poll for completion. */ | |
460 | { | |
461 | u64 dispatch_stat; | |
462 | long stuck; | |
463 | ||
464 | stuck = 100000 * nack_busy_id; | |
465 | do { | |
466 | __asm__ __volatile__("ldxa [%%g0] %1, %0" | |
467 | : "=r" (dispatch_stat) | |
468 | : "i" (ASI_INTR_DISPATCH_STAT)); | |
469 | if (dispatch_stat == 0UL) { | |
470 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
471 | : : "r" (pstate)); | |
22adb358 DM |
472 | if (unlikely(need_more)) { |
473 | int i, cnt = 0; | |
474 | for_each_cpu_mask(i, mask) { | |
475 | cpu_clear(i, mask); | |
476 | cnt++; | |
477 | if (cnt == 32) | |
478 | break; | |
479 | } | |
480 | goto retry; | |
481 | } | |
1da177e4 LT |
482 | return; |
483 | } | |
484 | if (!--stuck) | |
485 | break; | |
486 | } while (dispatch_stat & 0x5555555555555555UL); | |
487 | ||
488 | __asm__ __volatile__("wrpr %0, 0x0, %%pstate" | |
489 | : : "r" (pstate)); | |
490 | ||
491 | if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) { | |
492 | /* Busy bits will not clear, continue instead | |
493 | * of freezing up on this cpu. | |
494 | */ | |
495 | printk("CPU[%d]: mondo stuckage result[%016lx]\n", | |
496 | smp_processor_id(), dispatch_stat); | |
497 | } else { | |
498 | int i, this_busy_nack = 0; | |
499 | ||
500 | /* Delay some random time with interrupts enabled | |
501 | * to prevent deadlock. | |
502 | */ | |
503 | udelay(2 * nack_busy_id); | |
504 | ||
505 | /* Clear out the mask bits for cpus which did not | |
506 | * NACK us. | |
507 | */ | |
508 | for_each_cpu_mask(i, mask) { | |
509 | u64 check_mask; | |
510 | ||
92704a1c | 511 | if (is_jbus) |
1da177e4 LT |
512 | check_mask = (0x2UL << (2*i)); |
513 | else | |
514 | check_mask = (0x2UL << | |
515 | this_busy_nack); | |
516 | if ((dispatch_stat & check_mask) == 0) | |
517 | cpu_clear(i, mask); | |
518 | this_busy_nack += 2; | |
22adb358 DM |
519 | if (this_busy_nack == 64) |
520 | break; | |
1da177e4 LT |
521 | } |
522 | ||
523 | goto retry; | |
524 | } | |
525 | } | |
526 | } | |
527 | ||
1d2f1f90 | 528 | /* Multi-cpu list version. */ |
a43fe0e7 DM |
529 | static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask) |
530 | { | |
b830ab66 DM |
531 | struct trap_per_cpu *tb; |
532 | u16 *cpu_list; | |
533 | u64 *mondo; | |
534 | cpumask_t error_mask; | |
535 | unsigned long flags, status; | |
3cab0c3e | 536 | int cnt, retries, this_cpu, prev_sent, i; |
b830ab66 | 537 | |
17f34f0e DM |
538 | if (cpus_empty(mask)) |
539 | return; | |
540 | ||
b830ab66 DM |
541 | /* We have to do this whole thing with interrupts fully disabled. |
542 | * Otherwise if we send an xcall from interrupt context it will | |
543 | * corrupt both our mondo block and cpu list state. | |
544 | * | |
545 | * One consequence of this is that we cannot use timeout mechanisms | |
546 | * that depend upon interrupts being delivered locally. So, for | |
547 | * example, we cannot sample jiffies and expect it to advance. | |
548 | * | |
549 | * Fortunately, udelay() uses %stick/%tick so we can use that. | |
550 | */ | |
551 | local_irq_save(flags); | |
552 | ||
553 | this_cpu = smp_processor_id(); | |
554 | tb = &trap_block[this_cpu]; | |
1d2f1f90 | 555 | |
b830ab66 | 556 | mondo = __va(tb->cpu_mondo_block_pa); |
1d2f1f90 DM |
557 | mondo[0] = data0; |
558 | mondo[1] = data1; | |
559 | mondo[2] = data2; | |
560 | wmb(); | |
561 | ||
b830ab66 DM |
562 | cpu_list = __va(tb->cpu_list_pa); |
563 | ||
564 | /* Setup the initial cpu list. */ | |
565 | cnt = 0; | |
566 | for_each_cpu_mask(i, mask) | |
567 | cpu_list[cnt++] = i; | |
568 | ||
569 | cpus_clear(error_mask); | |
1d2f1f90 | 570 | retries = 0; |
3cab0c3e | 571 | prev_sent = 0; |
1d2f1f90 | 572 | do { |
3cab0c3e | 573 | int forward_progress, n_sent; |
1d2f1f90 | 574 | |
b830ab66 DM |
575 | status = sun4v_cpu_mondo_send(cnt, |
576 | tb->cpu_list_pa, | |
577 | tb->cpu_mondo_block_pa); | |
578 | ||
579 | /* HV_EOK means all cpus received the xcall, we're done. */ | |
580 | if (likely(status == HV_EOK)) | |
1d2f1f90 | 581 | break; |
b830ab66 | 582 | |
3cab0c3e DM |
583 | /* First, see if we made any forward progress. |
584 | * | |
585 | * The hypervisor indicates successful sends by setting | |
586 | * cpu list entries to the value 0xffff. | |
b830ab66 | 587 | */ |
3cab0c3e | 588 | n_sent = 0; |
b830ab66 | 589 | for (i = 0; i < cnt; i++) { |
3cab0c3e DM |
590 | if (likely(cpu_list[i] == 0xffff)) |
591 | n_sent++; | |
1d2f1f90 DM |
592 | } |
593 | ||
3cab0c3e DM |
594 | forward_progress = 0; |
595 | if (n_sent > prev_sent) | |
596 | forward_progress = 1; | |
597 | ||
598 | prev_sent = n_sent; | |
599 | ||
b830ab66 DM |
600 | /* If we get a HV_ECPUERROR, then one or more of the cpus |
601 | * in the list are in error state. Use the cpu_state() | |
602 | * hypervisor call to find out which cpus are in error state. | |
603 | */ | |
604 | if (unlikely(status == HV_ECPUERROR)) { | |
605 | for (i = 0; i < cnt; i++) { | |
606 | long err; | |
607 | u16 cpu; | |
608 | ||
609 | cpu = cpu_list[i]; | |
610 | if (cpu == 0xffff) | |
611 | continue; | |
612 | ||
613 | err = sun4v_cpu_state(cpu); | |
614 | if (err >= 0 && | |
615 | err == HV_CPU_STATE_ERROR) { | |
3cab0c3e | 616 | cpu_list[i] = 0xffff; |
b830ab66 DM |
617 | cpu_set(cpu, error_mask); |
618 | } | |
619 | } | |
620 | } else if (unlikely(status != HV_EWOULDBLOCK)) | |
621 | goto fatal_mondo_error; | |
622 | ||
3cab0c3e DM |
623 | /* Don't bother rewriting the CPU list, just leave the |
624 | * 0xffff and non-0xffff entries in there and the | |
625 | * hypervisor will do the right thing. | |
626 | * | |
627 | * Only advance timeout state if we didn't make any | |
628 | * forward progress. | |
629 | */ | |
b830ab66 DM |
630 | if (unlikely(!forward_progress)) { |
631 | if (unlikely(++retries > 10000)) | |
632 | goto fatal_mondo_timeout; | |
633 | ||
634 | /* Delay a little bit to let other cpus catch up | |
635 | * on their cpu mondo queue work. | |
636 | */ | |
637 | udelay(2 * cnt); | |
638 | } | |
1d2f1f90 DM |
639 | } while (1); |
640 | ||
b830ab66 DM |
641 | local_irq_restore(flags); |
642 | ||
643 | if (unlikely(!cpus_empty(error_mask))) | |
644 | goto fatal_mondo_cpu_error; | |
645 | ||
646 | return; | |
647 | ||
648 | fatal_mondo_cpu_error: | |
649 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus " | |
650 | "were in error state\n", | |
651 | this_cpu); | |
652 | printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu); | |
653 | for_each_cpu_mask(i, error_mask) | |
654 | printk("%d ", i); | |
655 | printk("]\n"); | |
656 | return; | |
657 | ||
658 | fatal_mondo_timeout: | |
659 | local_irq_restore(flags); | |
660 | printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward " | |
661 | " progress after %d retries.\n", | |
662 | this_cpu, retries); | |
663 | goto dump_cpu_list_and_out; | |
664 | ||
665 | fatal_mondo_error: | |
666 | local_irq_restore(flags); | |
667 | printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n", | |
668 | this_cpu, status); | |
669 | printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) " | |
670 | "mondo_block_pa(%lx)\n", | |
671 | this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa); | |
672 | ||
673 | dump_cpu_list_and_out: | |
674 | printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu); | |
675 | for (i = 0; i < cnt; i++) | |
676 | printk("%u ", cpu_list[i]); | |
677 | printk("]\n"); | |
1d2f1f90 | 678 | } |
a43fe0e7 | 679 | |
1da177e4 LT |
680 | /* Send cross call to all processors mentioned in MASK |
681 | * except self. | |
682 | */ | |
683 | static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask) | |
684 | { | |
685 | u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff)); | |
686 | int this_cpu = get_cpu(); | |
687 | ||
688 | cpus_and(mask, mask, cpu_online_map); | |
689 | cpu_clear(this_cpu, mask); | |
690 | ||
691 | if (tlb_type == spitfire) | |
692 | spitfire_xcall_deliver(data0, data1, data2, mask); | |
a43fe0e7 | 693 | else if (tlb_type == cheetah || tlb_type == cheetah_plus) |
1da177e4 | 694 | cheetah_xcall_deliver(data0, data1, data2, mask); |
a43fe0e7 DM |
695 | else |
696 | hypervisor_xcall_deliver(data0, data1, data2, mask); | |
1da177e4 LT |
697 | /* NOTE: Caller runs local copy on master. */ |
698 | ||
699 | put_cpu(); | |
700 | } | |
701 | ||
702 | extern unsigned long xcall_sync_tick; | |
703 | ||
704 | static void smp_start_sync_tick_client(int cpu) | |
705 | { | |
706 | cpumask_t mask = cpumask_of_cpu(cpu); | |
707 | ||
708 | smp_cross_call_masked(&xcall_sync_tick, | |
709 | 0, 0, 0, mask); | |
710 | } | |
711 | ||
712 | /* Send cross call to all processors except self. */ | |
713 | #define smp_cross_call(func, ctx, data1, data2) \ | |
714 | smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map) | |
715 | ||
716 | struct call_data_struct { | |
717 | void (*func) (void *info); | |
718 | void *info; | |
719 | atomic_t finished; | |
720 | int wait; | |
721 | }; | |
722 | ||
aa1d1a0a | 723 | static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock); |
1da177e4 LT |
724 | static struct call_data_struct *call_data; |
725 | ||
726 | extern unsigned long xcall_call_function; | |
727 | ||
aa1d1a0a DM |
728 | /** |
729 | * smp_call_function(): Run a function on all other CPUs. | |
730 | * @func: The function to run. This must be fast and non-blocking. | |
731 | * @info: An arbitrary pointer to pass to the function. | |
732 | * @nonatomic: currently unused. | |
733 | * @wait: If true, wait (atomically) until function has completed on other CPUs. | |
734 | * | |
735 | * Returns 0 on success, else a negative status code. Does not return until | |
736 | * remote CPUs are nearly ready to execute <<func>> or are or have executed. | |
737 | * | |
1da177e4 LT |
738 | * You must not call this function with disabled interrupts or from a |
739 | * hardware interrupt handler or from a bottom half handler. | |
740 | */ | |
bd40791e DM |
741 | static int smp_call_function_mask(void (*func)(void *info), void *info, |
742 | int nonatomic, int wait, cpumask_t mask) | |
1da177e4 LT |
743 | { |
744 | struct call_data_struct data; | |
ee29074d | 745 | int cpus; |
1da177e4 | 746 | |
1da177e4 LT |
747 | /* Can deadlock when called with interrupts disabled */ |
748 | WARN_ON(irqs_disabled()); | |
749 | ||
750 | data.func = func; | |
751 | data.info = info; | |
752 | atomic_set(&data.finished, 0); | |
753 | data.wait = wait; | |
754 | ||
755 | spin_lock(&call_lock); | |
756 | ||
ee29074d DM |
757 | cpu_clear(smp_processor_id(), mask); |
758 | cpus = cpus_weight(mask); | |
759 | if (!cpus) | |
760 | goto out_unlock; | |
761 | ||
1da177e4 | 762 | call_data = &data; |
aa1d1a0a | 763 | mb(); |
1da177e4 | 764 | |
bd40791e | 765 | smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask); |
1da177e4 | 766 | |
aa1d1a0a DM |
767 | /* Wait for response */ |
768 | while (atomic_read(&data.finished) != cpus) | |
769 | cpu_relax(); | |
1da177e4 | 770 | |
ee29074d | 771 | out_unlock: |
1da177e4 LT |
772 | spin_unlock(&call_lock); |
773 | ||
774 | return 0; | |
1da177e4 LT |
775 | } |
776 | ||
bd40791e DM |
777 | int smp_call_function(void (*func)(void *info), void *info, |
778 | int nonatomic, int wait) | |
779 | { | |
780 | return smp_call_function_mask(func, info, nonatomic, wait, | |
781 | cpu_online_map); | |
782 | } | |
783 | ||
1da177e4 LT |
784 | void smp_call_function_client(int irq, struct pt_regs *regs) |
785 | { | |
786 | void (*func) (void *info) = call_data->func; | |
787 | void *info = call_data->info; | |
788 | ||
789 | clear_softint(1 << irq); | |
790 | if (call_data->wait) { | |
791 | /* let initiator proceed only after completion */ | |
792 | func(info); | |
793 | atomic_inc(&call_data->finished); | |
794 | } else { | |
795 | /* let initiator proceed after getting data */ | |
796 | atomic_inc(&call_data->finished); | |
797 | func(info); | |
798 | } | |
799 | } | |
800 | ||
bd40791e DM |
801 | static void tsb_sync(void *info) |
802 | { | |
6f25f398 | 803 | struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()]; |
bd40791e DM |
804 | struct mm_struct *mm = info; |
805 | ||
6f25f398 DM |
806 | /* It is not valid to test "currrent->active_mm == mm" here. |
807 | * | |
808 | * The value of "current" is not changed atomically with | |
809 | * switch_mm(). But that's OK, we just need to check the | |
810 | * current cpu's trap block PGD physical address. | |
811 | */ | |
812 | if (tp->pgd_paddr == __pa(mm->pgd)) | |
bd40791e DM |
813 | tsb_context_switch(mm); |
814 | } | |
815 | ||
816 | void smp_tsb_sync(struct mm_struct *mm) | |
817 | { | |
818 | smp_call_function_mask(tsb_sync, mm, 0, 1, mm->cpu_vm_mask); | |
819 | } | |
820 | ||
1da177e4 LT |
821 | extern unsigned long xcall_flush_tlb_mm; |
822 | extern unsigned long xcall_flush_tlb_pending; | |
823 | extern unsigned long xcall_flush_tlb_kernel_range; | |
1da177e4 LT |
824 | extern unsigned long xcall_report_regs; |
825 | extern unsigned long xcall_receive_signal; | |
ee29074d | 826 | extern unsigned long xcall_new_mmu_context_version; |
1da177e4 LT |
827 | |
828 | #ifdef DCACHE_ALIASING_POSSIBLE | |
829 | extern unsigned long xcall_flush_dcache_page_cheetah; | |
830 | #endif | |
831 | extern unsigned long xcall_flush_dcache_page_spitfire; | |
832 | ||
833 | #ifdef CONFIG_DEBUG_DCFLUSH | |
834 | extern atomic_t dcpage_flushes; | |
835 | extern atomic_t dcpage_flushes_xcall; | |
836 | #endif | |
837 | ||
838 | static __inline__ void __local_flush_dcache_page(struct page *page) | |
839 | { | |
840 | #ifdef DCACHE_ALIASING_POSSIBLE | |
841 | __flush_dcache_page(page_address(page), | |
842 | ((tlb_type == spitfire) && | |
843 | page_mapping(page) != NULL)); | |
844 | #else | |
845 | if (page_mapping(page) != NULL && | |
846 | tlb_type == spitfire) | |
847 | __flush_icache_page(__pa(page_address(page))); | |
848 | #endif | |
849 | } | |
850 | ||
851 | void smp_flush_dcache_page_impl(struct page *page, int cpu) | |
852 | { | |
853 | cpumask_t mask = cpumask_of_cpu(cpu); | |
a43fe0e7 DM |
854 | int this_cpu; |
855 | ||
856 | if (tlb_type == hypervisor) | |
857 | return; | |
1da177e4 LT |
858 | |
859 | #ifdef CONFIG_DEBUG_DCFLUSH | |
860 | atomic_inc(&dcpage_flushes); | |
861 | #endif | |
a43fe0e7 DM |
862 | |
863 | this_cpu = get_cpu(); | |
864 | ||
1da177e4 LT |
865 | if (cpu == this_cpu) { |
866 | __local_flush_dcache_page(page); | |
867 | } else if (cpu_online(cpu)) { | |
868 | void *pg_addr = page_address(page); | |
869 | u64 data0; | |
870 | ||
871 | if (tlb_type == spitfire) { | |
872 | data0 = | |
873 | ((u64)&xcall_flush_dcache_page_spitfire); | |
874 | if (page_mapping(page) != NULL) | |
875 | data0 |= ((u64)1 << 32); | |
876 | spitfire_xcall_deliver(data0, | |
877 | __pa(pg_addr), | |
878 | (u64) pg_addr, | |
879 | mask); | |
a43fe0e7 | 880 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
881 | #ifdef DCACHE_ALIASING_POSSIBLE |
882 | data0 = | |
883 | ((u64)&xcall_flush_dcache_page_cheetah); | |
884 | cheetah_xcall_deliver(data0, | |
885 | __pa(pg_addr), | |
886 | 0, mask); | |
887 | #endif | |
888 | } | |
889 | #ifdef CONFIG_DEBUG_DCFLUSH | |
890 | atomic_inc(&dcpage_flushes_xcall); | |
891 | #endif | |
892 | } | |
893 | ||
894 | put_cpu(); | |
895 | } | |
896 | ||
897 | void flush_dcache_page_all(struct mm_struct *mm, struct page *page) | |
898 | { | |
899 | void *pg_addr = page_address(page); | |
900 | cpumask_t mask = cpu_online_map; | |
901 | u64 data0; | |
a43fe0e7 DM |
902 | int this_cpu; |
903 | ||
904 | if (tlb_type == hypervisor) | |
905 | return; | |
906 | ||
907 | this_cpu = get_cpu(); | |
1da177e4 LT |
908 | |
909 | cpu_clear(this_cpu, mask); | |
910 | ||
911 | #ifdef CONFIG_DEBUG_DCFLUSH | |
912 | atomic_inc(&dcpage_flushes); | |
913 | #endif | |
914 | if (cpus_empty(mask)) | |
915 | goto flush_self; | |
916 | if (tlb_type == spitfire) { | |
917 | data0 = ((u64)&xcall_flush_dcache_page_spitfire); | |
918 | if (page_mapping(page) != NULL) | |
919 | data0 |= ((u64)1 << 32); | |
920 | spitfire_xcall_deliver(data0, | |
921 | __pa(pg_addr), | |
922 | (u64) pg_addr, | |
923 | mask); | |
a43fe0e7 | 924 | } else if (tlb_type == cheetah || tlb_type == cheetah_plus) { |
1da177e4 LT |
925 | #ifdef DCACHE_ALIASING_POSSIBLE |
926 | data0 = ((u64)&xcall_flush_dcache_page_cheetah); | |
927 | cheetah_xcall_deliver(data0, | |
928 | __pa(pg_addr), | |
929 | 0, mask); | |
930 | #endif | |
931 | } | |
932 | #ifdef CONFIG_DEBUG_DCFLUSH | |
933 | atomic_inc(&dcpage_flushes_xcall); | |
934 | #endif | |
935 | flush_self: | |
936 | __local_flush_dcache_page(page); | |
937 | ||
938 | put_cpu(); | |
939 | } | |
940 | ||
a0663a79 DM |
941 | static void __smp_receive_signal_mask(cpumask_t mask) |
942 | { | |
943 | smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask); | |
944 | } | |
945 | ||
1da177e4 LT |
946 | void smp_receive_signal(int cpu) |
947 | { | |
948 | cpumask_t mask = cpumask_of_cpu(cpu); | |
949 | ||
a0663a79 DM |
950 | if (cpu_online(cpu)) |
951 | __smp_receive_signal_mask(mask); | |
1da177e4 LT |
952 | } |
953 | ||
954 | void smp_receive_signal_client(int irq, struct pt_regs *regs) | |
ee29074d DM |
955 | { |
956 | clear_softint(1 << irq); | |
957 | } | |
958 | ||
959 | void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs) | |
1da177e4 | 960 | { |
a0663a79 | 961 | struct mm_struct *mm; |
ee29074d | 962 | unsigned long flags; |
a0663a79 | 963 | |
1da177e4 | 964 | clear_softint(1 << irq); |
a0663a79 DM |
965 | |
966 | /* See if we need to allocate a new TLB context because | |
967 | * the version of the one we are using is now out of date. | |
968 | */ | |
969 | mm = current->active_mm; | |
ee29074d DM |
970 | if (unlikely(!mm || (mm == &init_mm))) |
971 | return; | |
a0663a79 | 972 | |
ee29074d | 973 | spin_lock_irqsave(&mm->context.lock, flags); |
aac0aadf | 974 | |
ee29074d DM |
975 | if (unlikely(!CTX_VALID(mm->context))) |
976 | get_new_mmu_context(mm); | |
aac0aadf | 977 | |
ee29074d | 978 | spin_unlock_irqrestore(&mm->context.lock, flags); |
aac0aadf | 979 | |
ee29074d DM |
980 | load_secondary_context(mm); |
981 | __flush_tlb_mm(CTX_HWBITS(mm->context), | |
982 | SECONDARY_CONTEXT); | |
a0663a79 DM |
983 | } |
984 | ||
985 | void smp_new_mmu_context_version(void) | |
986 | { | |
ee29074d | 987 | smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0); |
1da177e4 LT |
988 | } |
989 | ||
990 | void smp_report_regs(void) | |
991 | { | |
992 | smp_cross_call(&xcall_report_regs, 0, 0, 0); | |
993 | } | |
994 | ||
1da177e4 LT |
995 | /* We know that the window frames of the user have been flushed |
996 | * to the stack before we get here because all callers of us | |
997 | * are flush_tlb_*() routines, and these run after flush_cache_*() | |
998 | * which performs the flushw. | |
999 | * | |
1000 | * The SMP TLB coherency scheme we use works as follows: | |
1001 | * | |
1002 | * 1) mm->cpu_vm_mask is a bit mask of which cpus an address | |
1003 | * space has (potentially) executed on, this is the heuristic | |
1004 | * we use to avoid doing cross calls. | |
1005 | * | |
1006 | * Also, for flushing from kswapd and also for clones, we | |
1007 | * use cpu_vm_mask as the list of cpus to make run the TLB. | |
1008 | * | |
1009 | * 2) TLB context numbers are shared globally across all processors | |
1010 | * in the system, this allows us to play several games to avoid | |
1011 | * cross calls. | |
1012 | * | |
1013 | * One invariant is that when a cpu switches to a process, and | |
1014 | * that processes tsk->active_mm->cpu_vm_mask does not have the | |
1015 | * current cpu's bit set, that tlb context is flushed locally. | |
1016 | * | |
1017 | * If the address space is non-shared (ie. mm->count == 1) we avoid | |
1018 | * cross calls when we want to flush the currently running process's | |
1019 | * tlb state. This is done by clearing all cpu bits except the current | |
1020 | * processor's in current->active_mm->cpu_vm_mask and performing the | |
1021 | * flush locally only. This will force any subsequent cpus which run | |
1022 | * this task to flush the context from the local tlb if the process | |
1023 | * migrates to another cpu (again). | |
1024 | * | |
1025 | * 3) For shared address spaces (threads) and swapping we bite the | |
1026 | * bullet for most cases and perform the cross call (but only to | |
1027 | * the cpus listed in cpu_vm_mask). | |
1028 | * | |
1029 | * The performance gain from "optimizing" away the cross call for threads is | |
1030 | * questionable (in theory the big win for threads is the massive sharing of | |
1031 | * address space state across processors). | |
1032 | */ | |
62dbec78 DM |
1033 | |
1034 | /* This currently is only used by the hugetlb arch pre-fault | |
1035 | * hook on UltraSPARC-III+ and later when changing the pagesize | |
1036 | * bits of the context register for an address space. | |
1037 | */ | |
1da177e4 LT |
1038 | void smp_flush_tlb_mm(struct mm_struct *mm) |
1039 | { | |
62dbec78 DM |
1040 | u32 ctx = CTX_HWBITS(mm->context); |
1041 | int cpu = get_cpu(); | |
1da177e4 | 1042 | |
62dbec78 DM |
1043 | if (atomic_read(&mm->mm_users) == 1) { |
1044 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); | |
1045 | goto local_flush_and_out; | |
1046 | } | |
1da177e4 | 1047 | |
62dbec78 DM |
1048 | smp_cross_call_masked(&xcall_flush_tlb_mm, |
1049 | ctx, 0, 0, | |
1050 | mm->cpu_vm_mask); | |
1da177e4 | 1051 | |
62dbec78 DM |
1052 | local_flush_and_out: |
1053 | __flush_tlb_mm(ctx, SECONDARY_CONTEXT); | |
1da177e4 | 1054 | |
62dbec78 | 1055 | put_cpu(); |
1da177e4 LT |
1056 | } |
1057 | ||
1058 | void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs) | |
1059 | { | |
1060 | u32 ctx = CTX_HWBITS(mm->context); | |
1061 | int cpu = get_cpu(); | |
1062 | ||
dedeb002 | 1063 | if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) |
1da177e4 | 1064 | mm->cpu_vm_mask = cpumask_of_cpu(cpu); |
dedeb002 HD |
1065 | else |
1066 | smp_cross_call_masked(&xcall_flush_tlb_pending, | |
1067 | ctx, nr, (unsigned long) vaddrs, | |
1068 | mm->cpu_vm_mask); | |
1da177e4 | 1069 | |
1da177e4 LT |
1070 | __flush_tlb_pending(ctx, nr, vaddrs); |
1071 | ||
1072 | put_cpu(); | |
1073 | } | |
1074 | ||
1075 | void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end) | |
1076 | { | |
1077 | start &= PAGE_MASK; | |
1078 | end = PAGE_ALIGN(end); | |
1079 | if (start != end) { | |
1080 | smp_cross_call(&xcall_flush_tlb_kernel_range, | |
1081 | 0, start, end); | |
1082 | ||
1083 | __flush_tlb_kernel_range(start, end); | |
1084 | } | |
1085 | } | |
1086 | ||
1087 | /* CPU capture. */ | |
1088 | /* #define CAPTURE_DEBUG */ | |
1089 | extern unsigned long xcall_capture; | |
1090 | ||
1091 | static atomic_t smp_capture_depth = ATOMIC_INIT(0); | |
1092 | static atomic_t smp_capture_registry = ATOMIC_INIT(0); | |
1093 | static unsigned long penguins_are_doing_time; | |
1094 | ||
1095 | void smp_capture(void) | |
1096 | { | |
1097 | int result = atomic_add_ret(1, &smp_capture_depth); | |
1098 | ||
1099 | if (result == 1) { | |
1100 | int ncpus = num_online_cpus(); | |
1101 | ||
1102 | #ifdef CAPTURE_DEBUG | |
1103 | printk("CPU[%d]: Sending penguins to jail...", | |
1104 | smp_processor_id()); | |
1105 | #endif | |
1106 | penguins_are_doing_time = 1; | |
4f07118f | 1107 | membar_storestore_loadstore(); |
1da177e4 LT |
1108 | atomic_inc(&smp_capture_registry); |
1109 | smp_cross_call(&xcall_capture, 0, 0, 0); | |
1110 | while (atomic_read(&smp_capture_registry) != ncpus) | |
4f07118f | 1111 | rmb(); |
1da177e4 LT |
1112 | #ifdef CAPTURE_DEBUG |
1113 | printk("done\n"); | |
1114 | #endif | |
1115 | } | |
1116 | } | |
1117 | ||
1118 | void smp_release(void) | |
1119 | { | |
1120 | if (atomic_dec_and_test(&smp_capture_depth)) { | |
1121 | #ifdef CAPTURE_DEBUG | |
1122 | printk("CPU[%d]: Giving pardon to " | |
1123 | "imprisoned penguins\n", | |
1124 | smp_processor_id()); | |
1125 | #endif | |
1126 | penguins_are_doing_time = 0; | |
4f07118f | 1127 | membar_storeload_storestore(); |
1da177e4 LT |
1128 | atomic_dec(&smp_capture_registry); |
1129 | } | |
1130 | } | |
1131 | ||
1132 | /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they | |
1133 | * can service tlb flush xcalls... | |
1134 | */ | |
1135 | extern void prom_world(int); | |
96c6e0d8 | 1136 | |
1da177e4 LT |
1137 | void smp_penguin_jailcell(int irq, struct pt_regs *regs) |
1138 | { | |
1da177e4 LT |
1139 | clear_softint(1 << irq); |
1140 | ||
1141 | preempt_disable(); | |
1142 | ||
1143 | __asm__ __volatile__("flushw"); | |
1da177e4 LT |
1144 | prom_world(1); |
1145 | atomic_inc(&smp_capture_registry); | |
4f07118f | 1146 | membar_storeload_storestore(); |
1da177e4 | 1147 | while (penguins_are_doing_time) |
4f07118f | 1148 | rmb(); |
1da177e4 LT |
1149 | atomic_dec(&smp_capture_registry); |
1150 | prom_world(0); | |
1151 | ||
1152 | preempt_enable(); | |
1153 | } | |
1154 | ||
1da177e4 LT |
1155 | void __init smp_tick_init(void) |
1156 | { | |
1157 | boot_cpu_id = hard_smp_processor_id(); | |
1da177e4 LT |
1158 | } |
1159 | ||
1160 | /* /proc/profile writes can call this, don't __init it please. */ | |
1da177e4 LT |
1161 | int setup_profiling_timer(unsigned int multiplier) |
1162 | { | |
777a4475 | 1163 | return -EINVAL; |
1da177e4 LT |
1164 | } |
1165 | ||
7abea921 | 1166 | /* Constrain the number of cpus to max_cpus. */ |
1da177e4 LT |
1167 | void __init smp_prepare_cpus(unsigned int max_cpus) |
1168 | { | |
8935dced DM |
1169 | int i; |
1170 | ||
1da177e4 | 1171 | if (num_possible_cpus() > max_cpus) { |
5cbc3073 DM |
1172 | for_each_possible_cpu(i) { |
1173 | if (i != boot_cpu_id) { | |
1174 | cpu_clear(i, phys_cpu_present_map); | |
1175 | cpu_clear(i, cpu_present_map); | |
1da177e4 LT |
1176 | if (num_possible_cpus() <= max_cpus) |
1177 | break; | |
1178 | } | |
8935dced DM |
1179 | } |
1180 | } | |
1181 | ||
5cbc3073 | 1182 | cpu_data(boot_cpu_id).udelay_val = loops_per_jiffy; |
1da177e4 LT |
1183 | } |
1184 | ||
5cbc3073 | 1185 | void __devinit smp_prepare_boot_cpu(void) |
7abea921 | 1186 | { |
7abea921 DM |
1187 | } |
1188 | ||
5cbc3073 | 1189 | void __devinit smp_fill_in_sib_core_maps(void) |
1da177e4 | 1190 | { |
5cbc3073 DM |
1191 | unsigned int i; |
1192 | ||
1193 | for_each_possible_cpu(i) { | |
1194 | unsigned int j; | |
1195 | ||
1196 | if (cpu_data(i).core_id == 0) { | |
f78eae2e | 1197 | cpu_set(i, cpu_core_map[i]); |
5cbc3073 DM |
1198 | continue; |
1199 | } | |
1200 | ||
1201 | for_each_possible_cpu(j) { | |
1202 | if (cpu_data(i).core_id == | |
1203 | cpu_data(j).core_id) | |
f78eae2e DM |
1204 | cpu_set(j, cpu_core_map[i]); |
1205 | } | |
1206 | } | |
1207 | ||
1208 | for_each_possible_cpu(i) { | |
1209 | unsigned int j; | |
1210 | ||
1211 | if (cpu_data(i).proc_id == -1) { | |
1212 | cpu_set(i, cpu_sibling_map[i]); | |
1213 | continue; | |
1214 | } | |
1215 | ||
1216 | for_each_possible_cpu(j) { | |
1217 | if (cpu_data(i).proc_id == | |
1218 | cpu_data(j).proc_id) | |
5cbc3073 DM |
1219 | cpu_set(j, cpu_sibling_map[i]); |
1220 | } | |
1221 | } | |
1da177e4 LT |
1222 | } |
1223 | ||
b282b6f8 | 1224 | int __cpuinit __cpu_up(unsigned int cpu) |
1da177e4 LT |
1225 | { |
1226 | int ret = smp_boot_one_cpu(cpu); | |
1227 | ||
1228 | if (!ret) { | |
1229 | cpu_set(cpu, smp_commenced_mask); | |
1230 | while (!cpu_isset(cpu, cpu_online_map)) | |
1231 | mb(); | |
1232 | if (!cpu_isset(cpu, cpu_online_map)) { | |
1233 | ret = -ENODEV; | |
1234 | } else { | |
02fead75 DM |
1235 | /* On SUN4V, writes to %tick and %stick are |
1236 | * not allowed. | |
1237 | */ | |
1238 | if (tlb_type != hypervisor) | |
1239 | smp_synchronize_one_tick(cpu); | |
1da177e4 LT |
1240 | } |
1241 | } | |
1242 | return ret; | |
1243 | } | |
1244 | ||
1245 | void __init smp_cpus_done(unsigned int max_cpus) | |
1246 | { | |
1247 | unsigned long bogosum = 0; | |
1248 | int i; | |
1249 | ||
394e3902 AM |
1250 | for_each_online_cpu(i) |
1251 | bogosum += cpu_data(i).udelay_val; | |
1da177e4 LT |
1252 | printk("Total of %ld processors activated " |
1253 | "(%lu.%02lu BogoMIPS).\n", | |
1254 | (long) num_online_cpus(), | |
1255 | bogosum/(500000/HZ), | |
1256 | (bogosum/(5000/HZ))%100); | |
1257 | } | |
1258 | ||
1da177e4 LT |
1259 | void smp_send_reschedule(int cpu) |
1260 | { | |
64c7c8f8 | 1261 | smp_receive_signal(cpu); |
1da177e4 LT |
1262 | } |
1263 | ||
1264 | /* This is a nop because we capture all other cpus | |
1265 | * anyways when making the PROM active. | |
1266 | */ | |
1267 | void smp_send_stop(void) | |
1268 | { | |
1269 | } | |
1270 | ||
d369ddd2 DM |
1271 | unsigned long __per_cpu_base __read_mostly; |
1272 | unsigned long __per_cpu_shift __read_mostly; | |
1da177e4 LT |
1273 | |
1274 | EXPORT_SYMBOL(__per_cpu_base); | |
1275 | EXPORT_SYMBOL(__per_cpu_shift); | |
1276 | ||
5cbc3073 | 1277 | void __init real_setup_per_cpu_areas(void) |
1da177e4 LT |
1278 | { |
1279 | unsigned long goal, size, i; | |
1280 | char *ptr; | |
1da177e4 LT |
1281 | |
1282 | /* Copy section for each CPU (we discard the original) */ | |
5a089006 DM |
1283 | goal = PERCPU_ENOUGH_ROOM; |
1284 | ||
b6e3590f JF |
1285 | __per_cpu_shift = PAGE_SHIFT; |
1286 | for (size = PAGE_SIZE; size < goal; size <<= 1UL) | |
1da177e4 LT |
1287 | __per_cpu_shift++; |
1288 | ||
b6e3590f | 1289 | ptr = alloc_bootmem_pages(size * NR_CPUS); |
1da177e4 LT |
1290 | |
1291 | __per_cpu_base = ptr - __per_cpu_start; | |
1292 | ||
1da177e4 LT |
1293 | for (i = 0; i < NR_CPUS; i++, ptr += size) |
1294 | memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start); | |
951bc82c DM |
1295 | |
1296 | /* Setup %g5 for the boot cpu. */ | |
1297 | __local_per_cpu_offset = __per_cpu_offset(smp_processor_id()); | |
1da177e4 | 1298 | } |